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/openbmc/linux/Documentation/devicetree/bindings/fpga/
H A Dxlnx,fpga-slave-serial.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/xlnx,fpga-slave-serial.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Slave Serial SPI FPGA
10 - Nava kishore Manne <nava.kishore.manne@amd.com>
13 Xilinx Spartan-6 and 7 Series FPGAs support a method of loading the bitstream
14 over what is referred to as slave serial interface.The slave serial link is
21 https://www.xilinx.com/support/documentation/application_notes/xapp583-fpga-configuration.pdf
24 - $ref: /schemas/spi/spi-peripheral-props.yaml#
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H A Dlattice,sysconfig.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/lattice,sysconfig.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Lattice Slave SPI sysCONFIG FPGA manager
10 - Vladimir Georgiev <v.georgiev@metrotek.ru>
13 Lattice sysCONFIG port, which is used for FPGA configuration, among others,
14 have Slave Serial Peripheral Interface. Only full reconfiguration is
18 format into FPGA's SRAM configuration memory.
23 - lattice,sysconfig-ecp5
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/openbmc/linux/drivers/fpga/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # FPGA framework configuration
6 menuconfig FPGA config
7 tristate "FPGA Configuration Framework"
10 kernel. The FPGA framework adds an FPGA manager class and FPGA
13 if FPGA
16 tristate "Altera SOCFPGA FPGA Manager"
19 FPGA manager driver support for Altera SOCFPGA.
26 FPGA manager driver support for Altera Arria10 SoCFPGA.
41 tristate "Altera FPGA Passive Serial over SPI"
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H A Dxilinx-spi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Xilinx Spartan6 and 7 Series Slave Serial SPI Driver
9 * Manage Xilinx FPGA firmware that is loaded over SPI using
10 * the slave serial configuration interface.
15 #include <linux/fpga/fpga-mgr.h>
32 struct xilinx_spi_conf *conf = mgr->priv; in get_done_gpio()
35 ret = gpiod_get_value(conf->done); in get_done_gpio()
38 dev_err(&mgr->dev, "Error reading DONE (%d)\n", ret); in get_done_gpio()
52 * wait_for_init_b - wait for the INIT_B pin to have a given state, or wait
55 * @mgr: The FPGA manager object
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H A Dmachxo2-spi.c1 // SPDX-License-Identifier: GPL-2.0
3 * Lattice MachXO2 Slave SPI Driver
5 * Manage Lattice FPGA firmware that is loaded over SPI using
6 * the slave serial configuration interface.
12 #include <linux/fpga/fpga-mgr.h>
18 /* MachXO2 Programming Guide - sysCONFIG Programming Commands */
29 * Max CCLK in Slave SPI mode according to 'MachXO2 Family Data
30 * Sheet' sysCONFIG Port Timing Specifications (3-36)
112 pr_debug("machxo2 status: 0x%08lX - done=%d, cfgena=%d, busy=%d, fail=%d, devver=%d, err=%s\n", in dump_status_reg()
129 return -EBUSY; in wait_until_not_busy()
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/openbmc/u-boot/drivers/fpga/
H A Dvirtex2.c1 // SPDX-License-Identifier: GPL-2.0+
30 * file and add board-specific support for checking BUSY status. By default,
80 /* Default timeout for waiting for FPGA to enter operational mode after
98 switch (desc->iface) { in virtex2_load()
100 PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__); in virtex2_load()
105 PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__); in virtex2_load()
111 __FUNCTION__, desc->iface); in virtex2_load()
120 switch (desc->iface) { in virtex2_dump()
122 PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__); in virtex2_dump()
127 PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__); in virtex2_dump()
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H A DACEX1K.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Steven Scholz, imc Measurement & Control, steven.scholz@imc-berlin.de
10 #include <common.h> /* core U-Boot definitions */
22 * overrun the device (the Slave Parallel mode can free run at 50MHz).
38 /* ------------------------------------------------------------------------- */
44 switch (desc->iface) { in ACEX1K_load()
46 PRINTF ("%s: Launching Passive Serial Loader\n", __FUNCTION__); in ACEX1K_load()
54 __FUNCTION__, desc->iface); in ACEX1K_load()
64 switch (desc->iface) { in ACEX1K_dump()
66 PRINTF ("%s: Launching Passive Serial Dump\n", __FUNCTION__); in ACEX1K_dump()
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H A Dspartan2.c1 // SPDX-License-Identifier: GPL-2.0+
7 #include <common.h> /* core U-Boot definitions */
8 #include <spartan2.h> /* Spartan-II device family */
21 * overrun the device (the Slave Parallel mode can free run at 50MHz).
41 /* ------------------------------------------------------------------------- */
42 /* Spartan-II Generic Implementation */
48 switch (desc->iface) { in spartan2_load()
50 PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__); in spartan2_load()
55 PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__); in spartan2_load()
61 __FUNCTION__, desc->iface); in spartan2_load()
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H A Dcyclon2.c1 // SPDX-License-Identifier: GPL-2.0+
8 #include <common.h> /* core U-Boot definitions */
20 * overrun the device (the Slave Parallel mode can free run at 50MHz).
36 /* ------------------------------------------------------------------------- */
42 switch (desc->iface) { in CYC2_load()
44 PRINTF ("%s: Launching Passive Serial Loader\n", __FUNCTION__); in CYC2_load()
62 __FUNCTION__, desc->iface); in CYC2_load()
72 switch (desc->iface) { in CYC2_dump()
74 PRINTF ("%s: Launching Passive Serial Dump\n", __FUNCTION__); in CYC2_dump()
82 __FUNCTION__, desc->iface); in CYC2_dump()
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H A Dspartan3.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include <common.h> /* core U-Boot definitions */
13 #include <spartan3.h> /* Spartan-II device family */
25 * overrun the device (the Slave Parallel mode can free run at 50MHz).
45 /* ------------------------------------------------------------------------- */
46 /* Spartan-II Generic Implementation */
52 switch (desc->iface) { in spartan3_load()
54 PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__); in spartan3_load()
59 PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__); in spartan3_load()
65 __FUNCTION__, desc->iface); in spartan3_load()
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H A Dxilinx.c1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2012-2013, Xilinx, Michal Simek
11 * Xilinx FPGA support
15 #include <fpga.h>
24 /* ------------------------------------------------------------------------- */
29 xilinx_desc *desc_xilinx = desc->devdesc; in fpga_is_partial_data()
31 /* Check datasize against FPGA size */ in fpga_is_partial_data()
32 if (img_len >= desc_xilinx->size) in fpga_is_partial_data()
53 xdesc = desc->devdesc; in fpga_loadbitstream()
84 if (xdesc->name) { in fpga_loadbitstream()
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/openbmc/linux/arch/sh/include/mach-common/mach/
H A Dhighlander.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 #define PA_BCR 0xa4000000 /* FPGA */
11 #define PA_SDPOW (-1)
38 #define PA_SCSMR0 (PA_BCR+0x0400) /* SCIF0 Serial mode control */
40 #define PA_SCSCR0 (PA_BCR+0x0408) /* SCIF0 Serial control */
42 #define PA_SCFSR0 (PA_BCR+0x0410) /* SCIF0 Serial status control */
47 #define PA_SCSPTR0 (PA_BCR+0x0424) /* SCIF0 Serial Port control */
49 #define PA_SCRER0 (PA_BCR+0x042c) /* SCIF0 Serial Error control */
50 #define PA_SCSMR1 (PA_BCR+0x0500) /* SCIF1 Serial mode control */
52 #define PA_SCSCR1 (PA_BCR+0x0508) /* SCIF1 Serial control */
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/openbmc/u-boot/board/spear/x600/
H A Dfpga.c1 // SPDX-License-Identifier: GPL-2.0+
16 * FPGA program pin configuration on X600:
20 * 16bit serial writes via this SSP port to write the data bits into the
21 * FPGA.
27 * Set the active-low FPGA reset signal.
32 * On x600 we have no means to toggle the FPGA reset signal in fpga_reset()
38 * Set the FPGA's active-low SelectMap program line to the specified level
42 debug("%s:%d: FPGA PROG (%d)\n", __func__, __LINE__, assert); in fpga_pgm_fn()
50 * Test the state of the active-low FPGA INIT line. Return 1 on INIT
60 * On x600, the FPGA INIT signal is not connected to the SoC. in fpga_init_fn()
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/openbmc/linux/drivers/spi/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
9 The "Serial Peripheral Interface" is a low level synchronous
13 dynamic device discovery; some are even write-only or read-only.
17 chips, analog to digital (and d-to-a) converters, and more.
36 # MASTER side ... talking to discrete SPI slave chips including microcontrollers
44 If your system has an master-capable SPI controller (which
46 controller and the protocol drivers for the SPI slave chips
56 by providing a high-level interface to send memory-like commands.
80 to a SPI slave to Avalon bridge in a Intel MAX BMC.
145 supports spi-mem interface.
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/openbmc/u-boot/board/renesas/ap325rxa/
H A Dcpld-ap325rxa.c17 * to configure Xilinx Virtex, Virtex-E, Virtex-EM, Virtex-II,
18 * and Spartan-II devices via the SlaveSerial Configuration Mode.
22 * 3-October-2001 MN/MP - Created
23 * 20-August-2008 Renesas Solutions - Modified to SH7723
28 /* Serial */
119 * Calls ShiftDataOut() to output serial data
136 * to bring the Virtex Program Pin to High-Z in slave_serial()
143 * Bring Program High-Z in slave_serial()
144 * (Drive Program_OE bit low to bring Virtex Program Pin to High-Z in slave_serial()
153 /* Begin Slave-Serial Configuration */ in slave_serial()
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/openbmc/linux/Documentation/userspace-api/media/
H A Dglossary.rst1 .. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
50 FPGA
51 **Field-programmable Gate Array**
56 See https://en.wikipedia.org/wiki/Field-programmable_gate_array.
61 :term:`SoC` or :term:`FPGA`.
65 together make a larger user-facing functional peripheral. For
73 **Inter-Integrated Circuit**
75 A multi-master, multi-slave, packet switched, single-ended,
76 serial computer bus used to control some hardware components
77 like sub-device hardware components.
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/openbmc/u-boot/board/gdsys/mpc8308/
H A Dhrcon.c1 // SPDX-License-Identifier: GPL-2.0+
24 #include "../common/ioep-fpga.h"
58 int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data) in fpga_set_reg() argument
62 switch (fpga) { in fpga_set_reg()
67 res = mclink_send(fpga - 1, regoff, data); in fpga_set_reg()
79 int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data) in fpga_get_reg() argument
83 switch (fpga) { in fpga_get_reg()
88 if (fpga > mclink_fpgacount) in fpga_get_reg()
89 return -EINVAL; in fpga_get_reg()
90 res = mclink_receive(fpga - 1, regoff, data); in fpga_get_reg()
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H A Dstrider.c1 // SPDX-License-Identifier: GPL-2.0+
27 #include "../common/ioep-fpga.h"
61 int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data) in fpga_set_reg() argument
65 switch (fpga) { in fpga_set_reg()
70 res = mclink_send(fpga - 1, regoff, data); in fpga_set_reg()
82 int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data) in fpga_get_reg() argument
86 switch (fpga) { in fpga_get_reg()
91 if (fpga > mclink_fpgacount) in fpga_get_reg()
92 return -EINVAL; in fpga_get_reg()
93 res = mclink_receive(fpga - 1, regoff, data); in fpga_get_reg()
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/openbmc/linux/arch/sh/include/mach-sdk7786/mach/
H A Dfpga.h1 /* SPDX-License-Identifier: GPL-2.0 */
71 #define SCBR_I2CMEN BIT(0) /* FPGA I2C master enable */
77 #define PWRCR_SCIEN BIT(2) /* Serial port enable */
131 /* arch/sh/boards/mach-sdk7786/fpga.c */
135 /* arch/sh/boards/mach-sdk7786/nmi.c */
142 * when the FPGA is in I2C slave mode.
/openbmc/u-boot/include/configs/
H A Dsocfpga_common.h1 /* SPDX-License-Identifier: GPL-2.0+ */
50 * U-Boot general configurations
69 * EPCS/EPCQx1 Serial Flash Controller
74 * base address based on it's particular FPGA configuration. Please note
89 * FPGA Driver
122 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */
149 /* Address of device when used as slave */
179 * Serial Driver
200 * U-Boot environment
219 * mtd partitioning for serial NOR flash
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H A DBSC9132QDS.h1 /* SPDX-License-Identifier: GPL-2.0+ */
33 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
39 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
40 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
43 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
64 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
68 * Memory space is mapped 1-1, but I/O space must start from 0.
248 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
351 - GENERATED_GBL_DATA_SIZE)
357 /* Serial Port */
[all …]
/openbmc/u-boot/include/
H A Dxilinx.h1 /* SPDX-License-Identifier: GPL-2.0+ */
7 #include <fpga.h>
16 slave_serial, /* serial data and external clock */
17 master_serial, /* serial data w/ internal clock (not used) */
19 jtag_mode, /* jtag/tap serial (not used ) */
21 slave_selectmap, /* slave SelectMap (virtex2) */
29 xilinx_spartan2, /* Spartan-II Family */
30 xilinx_virtexE, /* Virtex-E Family */
32 xilinx_spartan3, /* Spartan-III Family */
/openbmc/linux/drivers/bus/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
37 Driver for the Broadcom Set Top Box System-on-a-chip internal bus
42 bool "Baikal-T1 APB-bus driver"
46 Baikal-T1 AXI-APB bridge is used to access the SoC subsystem CSRs.
48 Interconnect. In case of any APB protocol collisions, slave device
53 errors counter. The counter and the APB-bus operations timeout can be
57 bool "Baikal-T1 AXI-bus driver"
61 AXI3-bus is the main communication bus connecting all high-speed
62 peripheral IP-cores with RAM controller and with MIPS P5600 cores on
63 Baikal-T1 SoC. Traffic arbitration is done by means of DW AMBA 3 AXI
[all …]
/openbmc/linux/drivers/i2c/busses/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
16 for Cypress CCGx Type-C controller. Individual bus drivers
25 controller is part of the 7101 device, which is an ACPI-compliant
29 will be called i2c-ali1535.
37 controller is part of the 7101 device, which is an ACPI-compliant
41 will be called i2c-ali1563.
51 will be called i2c-ali15x3.
63 will be called i2c-amd756.
70 S4882 motherboard. On this 4-CPU board, the SMBus is multiplexed
76 will be called i2c-amd756-s4882.
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/openbmc/u-boot/
H A DREADME1 # SPDX-License-Identifier: GPL-2.0+
3 # (C) Copyright 2000 - 2013
9 This directory contains the source code for U-Boot, a boot loader for
15 The development of U-Boot is closely related to Linux: some parts of
37 scattered throughout the U-Boot source identifying the people or
41 actual U-Boot source tree; however, it can be created dynamically
51 U-Boot, you should send a message to the U-Boot mailing list at
52 <u-boot@lists.denx.de>. There is also an archive of previous traffic
53 on the mailing list - please search the archive before asking FAQ's.
54 Please see http://lists.denx.de/pipermail/u-boot and
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