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/openbmc/u-boot/doc/device-tree-bindings/net/
H A Daltera_tse.txt1 * Altera Triple-Speed Ethernet MAC driver (TSE)
4 - compatible: Should be "altr,tse-1.0" for legacy SGDMA based TSE, and should
5 be "altr,tse-msgdma-1.0" for the preferred MSGDMA based TSE.
6 - reg: Address and length of the register set for the device. It contains
7 the information of registers in the same order as described by reg-names
8 - reg-names: Should contain the reg names
16 - interrupts: Should contain the TSE interrupts and it's mode.
17 - interrupt-names: Should contain the interrupt names
20 - rx-fifo-depth: MAC receive FIFO buffer depth in bytes
21 - tx-fifo-depth: MAC transmit FIFO buffer depth in bytes
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dadi,adin.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandru Tachici <alexandru.tachici@analog.com>
16 - $ref: ethernet-phy.yaml#
19 adi,rx-internal-delay-ps:
22 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
26 adi,tx-internal-delay-ps:
29 internal delay (phy-mode is 'rgmii-id' or 'rgmii-txid') in pico-seconds.
33 adi,fifo-depth-bits:
[all …]
/openbmc/linux/include/linux/soc/qcom/
H A Dgeni-se.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
15 * @GENI_SE_FIFO: FIFO mode. Data is transferred with SE FIFO
56 * struct geni_se - GENI Serial Engine
258 * For QUP HW Version >= 3.10 Tx fifo depth support is increased
259 * to 256bytes and corresponding bits are 16 to 23
269 * For QUP HW Version >= 3.10 Rx fifo depth support is increased
270 * to 256bytes and corresponding bits are 16 to 23
309 * geni_se_read_proto() - Read the protocol configured for a serial engine
318 val = readl_relaxed(se->base + GENI_FW_REVISION_RO); in geni_se_read_proto()
[all …]
/openbmc/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-sm1.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "meson-g12-common.dtsi"
8 #include <dt-bindings/clock/axg-audio-clkc.h>
9 #include <dt-bindings/power/meson-sm1-power.h>
10 #include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
11 #include <dt-bindings/reset/amlogic,meson-g12a-audio-reset.h>
16 tdmif_a: audio-controller-0 {
17 compatible = "amlogic,axg-tdm-iface";
18 #sound-dai-cells = <0>;
19 sound-name-prefix = "TDM_A";
[all …]
/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dspi-sifive.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-sifive.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Pragnesh Patel <pragnesh.patel@sifive.com>
11 - Paul Walmsley <paul.walmsley@sifive.com>
12 - Palmer Dabbelt <palmer@sifive.com>
15 - $ref: spi-controller.yaml#
20 - enum:
21 - sifive,fu540-c000-spi
[all …]
/openbmc/qemu/hw/audio/
H A Dpl041.c5 * Written by Mathieu Sonet - www.elasticsheep.com
15 * - Supports only a playback on one channel (Versatile/Vexpress)
16 * - Supports only one TX FIFO in compact-mode or non-compact mode.
17 * - Supports playback of 12, 16, 18 and 20 bits samples.
18 * - Record is not supported.
19 * - The PL041 is hardwired to a LM4549 codec.
25 #include "hw/qdev-properties.h"
61 /* This FIFO only stores 20-bit samples on 32-bit words.
89 uint32_t fifo_depth; /* FIFO depth in non-compact mode */
125 /* Add the fifo depth information */ in pl041_compute_periphid3()
[all …]
/openbmc/linux/drivers/net/ethernet/sgi/
H A Dmeth.h4 #define TX_RING_ENTRIES 64 /* 64-512?*/
11 #define METH_RX_HEAD 34 /* status + 3 quad garbage-fill + 2 byte zero-pad */
32 * It consists of header, 0-3 concatination
43 u64 data_len:16; /*Length of valid data in bytes-1*/
48 u64 len:16; /*length of buffer data - 1*/
91 u64 pad[3]; /* For whatever reason, there needs to be 4 double-word offset */
93 char buf[METH_RX_BUFF_SIZE-sizeof(rx_status_vector)-3*sizeof(u64)-sizeof(u16)];/* data */
99 /* Bits in METH_MAC */
110 /* Bits 5 and 6 are used to determine the Destination address filter mode */
122 … /* Bits 8 through 14 are used to determine Inter-Packet Gap between "Back to Back" packets */
[all …]
/openbmc/linux/drivers/net/phy/
H A Ddp83867.c1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/nvmem-consumer.h>
19 #include <dt-bindings/net/ti-dp83867.h>
63 /* MICR Interrupt bits */
77 /* RGMIICTL bits */
81 /* SGMIICTL bits */
84 /* RXFCFG bits*/
91 /* STRAP_STS1 bits */
94 /* STRAP_STS2 bits */
102 /* PHY CTRL bits */
[all …]
/openbmc/linux/drivers/spi/
H A Dspi-sifive.c1 // SPDX-License-Identifier: GPL-2.0
34 #define SIFIVE_SPI_REG_TXDATA 0x48 /* Tx FIFO data */
35 #define SIFIVE_SPI_REG_RXDATA 0x4c /* Rx FIFO data */
36 #define SIFIVE_SPI_REG_TXMARK 0x50 /* Tx FIFO watermark */
37 #define SIFIVE_SPI_REG_RXMARK 0x54 /* Rx FIFO watermark */
43 /* sckdiv bits */
46 /* sckmode bits */
52 /* csmode bits */
57 /* delay0 bits */
63 /* delay1 bits */
[all …]
H A Dspi-cadence.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2008 - 2014 Xilinx, Inc.
7 * based on Blackfin On-Chip SPI Driver (spi_bfin5xx.c)
24 #define CDNS_SPI_NAME "cdns-spi"
37 #define CDNS_SPI_THLD 0x28 /* Transmit FIFO Watermark Register,RW */
43 * This register contains various control bits that affect the operation
62 * SPI Configuration Register - Baud rate and target select
81 #define CDNS_SPI_IXR_TXOW 0x00000004 /* SPI TX FIFO Overwater */
83 #define CDNS_SPI_IXR_RXNEMTY 0x00000010 /* SPI RX FIFO Not Empty */
101 * struct cdns_spi - This definition defines spi driver instance
[all …]
/openbmc/linux/include/media/drv-intf/
H A Dexynos-fimc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2010 - 2013 Samsung Electronics Co., Ltd.
12 #include <media/media-entity.h>
13 #include <media/v4l2-dev.h>
14 #include <media/v4l2-mediabus.h>
37 /* Camera MIPI-CSI2 serial bus */
39 /* FIFO link from LCD controller (WriteBack A) */
41 /* FIFO link from LCD controller (WriteBack B) */
43 /* FIFO link from FIMC-IS */
62 * struct fimc_source_info - video source description required for the host
[all …]
/openbmc/linux/arch/nios2/boot/dts/
H A D10m50_devboard.dts1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
10 compatible = "altr,niosii-max10";
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "altr,nios2-1.1";
22 interrupt-controller;
23 #interrupt-cells = <1>;
[all …]
H A D3c120_devboard.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
13 #address-cells = <1>;
14 #size-cells = <1>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "altr,nios2-1.0";
24 interrupt-controller;
25 #interrupt-cells = <1>;
26 clock-frequency = <125000000>;
[all …]
/openbmc/u-boot/drivers/spi/
H A Ddesignware_spi.c1 // SPDX-License-Identifier: GPL-2.0
8 * drivers/spi/spi-dw.c, which is:
13 #include <asm-generic/gpio.h>
78 /* Bit fields in SR, 7 bits */
79 #define SR_MASK GENMASK(6, 0) /* cover 7 bits */
91 s32 frequency; /* Default clock frequency, -1 for none */
102 struct gpio_desc cs_gpio; /* External chip-select gpio */
110 u32 fifo_len; /* depth of the FIFO buffer */
121 return __raw_readl(priv->regs + offset); in dw_read()
126 __raw_writel(val, priv->regs + offset); in dw_write()
[all …]
H A Dpic32_spi.c1 // SPDX-License-Identifier: GPL-2.0+
19 #include <dt-bindings/clock/microchip,clock.h>
38 #define PIC32_SPI_CTRL_BPW_MASK 0x03 /* Bits per word */
61 u32 fifo_depth; /* FIFO depth in bytes */
62 u32 fifo_n_word; /* FIFO depth in words */
67 u32 speed_hz; /* spi-clk rate */
77 /* SPI FiFo accessor */
84 writel(PIC32_SPI_CTRL_ON, &priv->regs->ctrl.set); in pic32_spi_enable()
89 writel(PIC32_SPI_CTRL_ON, &priv->regs->ctrl.clr); in pic32_spi_disable()
94 u32 sr = readl(&priv->regs->status.raw); in pic32_spi_rx_fifo_level()
[all …]
/openbmc/linux/drivers/staging/axis-fifo/
H A Daxis-fifo.c1 // SPDX-License-Identifier: GPL-2.0
3 * Xilinx AXIS FIFO: interface to the Xilinx AXI-Stream FIFO IP core
12 /* ----------------------------
14 * ----------------------------
37 /* ----------------------------
39 * ----------------------------
47 /* ----------------------------
49 * ----------------------------
68 /* ----------------------------
70 * ----------------------------
[all …]
/openbmc/qemu/rust/hw/char/pl011/src/
H A Ddevice.rs3 // SPDX-License-Identifier: GPL-2.0-or-later
45 fn index(&self, idx: hwaddr) -> &Self::Output { in index()
90 /// * sysbus IRQ 1: `UARTRXINTR` (receive FIFO interrupt line)
91 /// * sysbus IRQ 2: `UARTTXINTR` (transmit FIFO interrupt line)
131 /// Initializes a pre-allocated, unitialized instance of `PL011State`.
181 pub fn read(&mut self, offset: hwaddr, _size: c_uint) -> std::ops::ControlFlow<u64, u64> { in read()
186 u64::from(self.device_id[(offset - 0xfe0) >> 2]) in read()
196 self.read_count -= 1; in read()
197 self.read_pos = (self.read_pos + 1) & (self.fifo_depth() - 1); in read()
205 // Update error bits. in read()
[all …]
/openbmc/u-boot/arch/nios2/dts/
H A D10m50_devboard.dts1 // SPDX-License-Identifier: GPL-2.0+
8 /dts-v1/;
12 compatible = "altr,niosii-max10";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 #address-cells = <1>;
18 #size-cells = <0>;
21 u-boot,dm-pre-reloc;
23 compatible = "altr,nios2-1.1";
25 interrupt-controller;
[all …]
H A D3c120_devboard.dts1 // SPDX-License-Identifier: GPL-2.0+
8 /dts-v1/;
13 #address-cells = <1>;
14 #size-cells = <1>;
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "altr,nios2-1.0";
24 interrupt-controller;
25 #interrupt-cells = <1>;
26 clock-frequency = <125000000>;
[all …]
/openbmc/linux/drivers/i2c/busses/
H A Di2c-cadence.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2009 - 2014 Xilinx, Inc.
40 /* 1 = Auto init FIFO to zeroes */
61 * Normal addressing mode uses [6:0] bits. Extended addressing mode uses [9:0]
62 * bits. A write access to this register always initiates a transfer if the I2C
120 /* Transfer size in multiples of data interrupt depth */
121 #define CDNS_I2C_TRANSFER_SIZE(max) ((max) - 3)
123 #define DRIVER_NAME "cdns-i2c"
134 #define cdns_i2c_readreg(offset) readl_relaxed(id->membase + offset)
135 #define cdns_i2c_writereg(val, offset) writel_relaxed(val, id->membase + offset)
[all …]
/openbmc/linux/sound/soc/fsl/
H A Dfsl_dma.c1 // SPDX-License-Identifier: GPL-2.0
7 // Copyright 2007-2010 Freescale Semiconductor, Inc.
16 #include <linux/dma-mapping.h>
40 * that is 8, 16, or 32 bits.
72 /** fsl_dma_private: p-substream DMA data
74 * Each substream has a 1-to-1 association with a DMA channel.
76 * The link[] array is first because it needs to be aligned on a 32-byte
120 * Since each link descriptor has a 32-bit byte count field, we set
121 * period_bytes_max to the largest 32-bit number. We also have no maximum
137 .period_bytes_max = (u32) -1,
[all …]
H A Dfsl_ssi.c1 // SPDX-License-Identifier: GPL-2.0
7 // Copyright 2007-2010 Freescale Semiconductor, Inc.
9 // Some notes why imx-pcm-fiq is used instead of DMA on some boards:
12 // sane processor vendors have a FIFO per AC97 slot, the i.MX has only
13 // one FIFO which combines all valid receive slots. We cannot even select
16 // we receive in our (PCM-) data stream. The only chance we have is to
23 // provides us status bits when the read register is updated with *another*
25 // contains the same value) these status bits are not set. We work
26 // around this by not polling these bits but only wait a fixed delay.
43 #include <linux/dma/imx-dma.h>
[all …]
/openbmc/linux/arch/riscv/boot/dts/starfive/
H A Djh7110.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive,jh7110-crg.h>
9 #include <dt-bindings/power/starfive,jh7110-pmu.h>
10 #include <dt-bindings/reset/starfive,jh7110-crg.h>
11 #include <dt-bindings/thermal/thermal.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
19 #address-cells = <1>;
20 #size-cells = <0>;
[all …]
/openbmc/linux/drivers/tty/serial/
H A Dsifive.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2018-2019 SiFive
8 * - drivers/tty/serial/pxa.c
9 * - drivers/tty/serial/amba-pl011.c
10 * - drivers/tty/serial/uartlite.c
11 * - drivers/tty/serial/omap-serial.c
12 * - drivers/pwm/pwm-sifive.c
15 * - Chapter 19 "Universal Asynchronous Receiver/Transmitter (UART)" of
16 * SiFive FE310-G000 v2p3
17 * - The tree/master/src/main/scala/devices/uart directory of
[all …]
/openbmc/linux/drivers/mmc/host/
H A Ddw_mmc.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
17 #include <linux/fault-inject.h>
59 * struct dw_mci - MMC controller state shared between all slots
63 * @fifo_reg: Pointer to MMIO registers for data FIFO
77 * @dma_64bit_address: Whether DMA supports 64-bit address mode or not.
80 * @dma_ops: Pointer to platform-specific DMA callbacks.
84 * @dms: structure of slave-dma private data.
112 * @fifo_depth: depth of FIFO.
113 * @data_addr_override: override fifo reg offset with this value.
114 * @wm_aligned: force fifo watermark equal with data length in PIO mode.
[all …]

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