18862bf1eSJeff Kirsher /* version dependencies have been confined to a separate file */ 28862bf1eSJeff Kirsher 38862bf1eSJeff Kirsher /* Tunable parameters */ 48862bf1eSJeff Kirsher #define TX_RING_ENTRIES 64 /* 64-512?*/ 58862bf1eSJeff Kirsher 68862bf1eSJeff Kirsher #define RX_RING_ENTRIES 16 /* Do not change */ 78862bf1eSJeff Kirsher /* Internal constants */ 88862bf1eSJeff Kirsher #define TX_RING_BUFFER_SIZE (TX_RING_ENTRIES*sizeof(tx_packet)) 98862bf1eSJeff Kirsher #define RX_BUFFER_SIZE 1546 /* ethenet packet size */ 108862bf1eSJeff Kirsher #define METH_RX_BUFF_SIZE 4096 118862bf1eSJeff Kirsher #define METH_RX_HEAD 34 /* status + 3 quad garbage-fill + 2 byte zero-pad */ 128862bf1eSJeff Kirsher #define RX_BUFFER_OFFSET (sizeof(rx_status_vector)+2) /* staus vector + 2 bytes of padding */ 138862bf1eSJeff Kirsher #define RX_BUCKET_SIZE 256 148862bf1eSJeff Kirsher 158862bf1eSJeff Kirsher /* For more detailed explanations of what each field menas, 168862bf1eSJeff Kirsher see Nick's great comments to #defines below (or docs, if 178862bf1eSJeff Kirsher you are lucky enough toget hold of them :)*/ 188862bf1eSJeff Kirsher 198862bf1eSJeff Kirsher /* tx status vector is written over tx command header upon 208862bf1eSJeff Kirsher dma completion. */ 218862bf1eSJeff Kirsher 228862bf1eSJeff Kirsher typedef struct tx_status_vector { 238862bf1eSJeff Kirsher u64 sent:1; /* always set to 1...*/ 248862bf1eSJeff Kirsher u64 pad0:34;/* always set to 0 */ 258862bf1eSJeff Kirsher u64 flags:9; /*I'm too lazy to specify each one separately at the moment*/ 268862bf1eSJeff Kirsher u64 col_retry_cnt:4; /*collision retry count*/ 278862bf1eSJeff Kirsher u64 len:16; /*Transmit length in bytes*/ 288862bf1eSJeff Kirsher } tx_status_vector; 298862bf1eSJeff Kirsher 308862bf1eSJeff Kirsher /* 318862bf1eSJeff Kirsher * Each packet is 128 bytes long. 328862bf1eSJeff Kirsher * It consists of header, 0-3 concatination 338862bf1eSJeff Kirsher * buffer pointers and up to 120 data bytes. 348862bf1eSJeff Kirsher */ 358862bf1eSJeff Kirsher typedef struct tx_packet_hdr { 368862bf1eSJeff Kirsher u64 pad1:36; /*should be filled with 0 */ 378862bf1eSJeff Kirsher u64 cat_ptr3_valid:1, /*Concatination pointer valid flags*/ 388862bf1eSJeff Kirsher cat_ptr2_valid:1, 398862bf1eSJeff Kirsher cat_ptr1_valid:1; 408862bf1eSJeff Kirsher u64 tx_int_flag:1; /*Generate TX intrrupt when packet has been sent*/ 418862bf1eSJeff Kirsher u64 term_dma_flag:1; /*Terminate transmit DMA on transmit abort conditions*/ 428862bf1eSJeff Kirsher u64 data_offset:7; /*Starting byte offset in ring data block*/ 438862bf1eSJeff Kirsher u64 data_len:16; /*Length of valid data in bytes-1*/ 448862bf1eSJeff Kirsher } tx_packet_hdr; 458862bf1eSJeff Kirsher typedef union tx_cat_ptr { 468862bf1eSJeff Kirsher struct { 478862bf1eSJeff Kirsher u64 pad2:16; /* should be 0 */ 488862bf1eSJeff Kirsher u64 len:16; /*length of buffer data - 1*/ 498862bf1eSJeff Kirsher u64 start_addr:29; /*Physical starting address*/ 508862bf1eSJeff Kirsher u64 pad1:3; /* should be zero */ 518862bf1eSJeff Kirsher } form; 528862bf1eSJeff Kirsher u64 raw; 538862bf1eSJeff Kirsher } tx_cat_ptr; 548862bf1eSJeff Kirsher 558862bf1eSJeff Kirsher typedef struct tx_packet { 568862bf1eSJeff Kirsher union { 578862bf1eSJeff Kirsher tx_packet_hdr header; 588862bf1eSJeff Kirsher tx_status_vector res; 598862bf1eSJeff Kirsher u64 raw; 608862bf1eSJeff Kirsher }header; 618862bf1eSJeff Kirsher union { 628862bf1eSJeff Kirsher tx_cat_ptr cat_buf[3]; 638862bf1eSJeff Kirsher char dt[120]; 648862bf1eSJeff Kirsher } data; 658862bf1eSJeff Kirsher } tx_packet; 668862bf1eSJeff Kirsher 678862bf1eSJeff Kirsher typedef union rx_status_vector { 688862bf1eSJeff Kirsher volatile struct { 698862bf1eSJeff Kirsher u64 pad1:1;/*fill it with ones*/ 708862bf1eSJeff Kirsher u64 pad2:15;/*fill with 0*/ 718862bf1eSJeff Kirsher u64 ip_chk_sum:16; 728862bf1eSJeff Kirsher u64 seq_num:5; 738862bf1eSJeff Kirsher u64 mac_addr_match:1; 748862bf1eSJeff Kirsher u64 mcast_addr_match:1; 758862bf1eSJeff Kirsher u64 carrier_event_seen:1; 768862bf1eSJeff Kirsher u64 bad_packet:1; 778862bf1eSJeff Kirsher u64 long_event_seen:1; 788862bf1eSJeff Kirsher u64 invalid_preamble:1; 798862bf1eSJeff Kirsher u64 broadcast:1; 808862bf1eSJeff Kirsher u64 multicast:1; 818862bf1eSJeff Kirsher u64 crc_error:1; 828862bf1eSJeff Kirsher u64 huh:1;/*???*/ 838862bf1eSJeff Kirsher u64 rx_code_violation:1; 848862bf1eSJeff Kirsher u64 rx_len:16; 858862bf1eSJeff Kirsher } parsed; 868862bf1eSJeff Kirsher volatile u64 raw; 878862bf1eSJeff Kirsher } rx_status_vector; 888862bf1eSJeff Kirsher 898862bf1eSJeff Kirsher typedef struct rx_packet { 908862bf1eSJeff Kirsher rx_status_vector status; 918862bf1eSJeff Kirsher u64 pad[3]; /* For whatever reason, there needs to be 4 double-word offset */ 928862bf1eSJeff Kirsher u16 pad2; 938862bf1eSJeff Kirsher char buf[METH_RX_BUFF_SIZE-sizeof(rx_status_vector)-3*sizeof(u64)-sizeof(u16)];/* data */ 948862bf1eSJeff Kirsher } rx_packet; 958862bf1eSJeff Kirsher 968862bf1eSJeff Kirsher #define TX_INFO_RPTR 0x00FF0000 978862bf1eSJeff Kirsher #define TX_INFO_WPTR 0x000000FF 988862bf1eSJeff Kirsher 998862bf1eSJeff Kirsher /* Bits in METH_MAC */ 1008862bf1eSJeff Kirsher 1018862bf1eSJeff Kirsher #define SGI_MAC_RESET BIT(0) /* 0: MAC110 active in run mode, 1: Global reset signal to MAC110 core is active */ 1028862bf1eSJeff Kirsher #define METH_PHY_FDX BIT(1) /* 0: Disable full duplex, 1: Enable full duplex */ 1038862bf1eSJeff Kirsher #define METH_PHY_LOOP BIT(2) /* 0: Normal operation, follows 10/100mbit and M10T/MII select, 1: loops internal MII bus */ 1048862bf1eSJeff Kirsher /* selects ignored */ 1058862bf1eSJeff Kirsher #define METH_100MBIT BIT(3) /* 0: 10meg mode, 1: 100meg mode */ 1068862bf1eSJeff Kirsher #define METH_PHY_MII BIT(4) /* 0: MII selected, 1: SIA selected */ 1078862bf1eSJeff Kirsher /* Note: when loopback is set this bit becomes collision control. Setting this bit will */ 1088862bf1eSJeff Kirsher /* cause a collision to be reported. */ 1098862bf1eSJeff Kirsher 1108862bf1eSJeff Kirsher /* Bits 5 and 6 are used to determine the Destination address filter mode */ 1118862bf1eSJeff Kirsher #define METH_ACCEPT_MY 0 /* 00: Accept PHY address only */ 1128862bf1eSJeff Kirsher #define METH_ACCEPT_MCAST 0x20 /* 01: Accept physical, broadcast, and multicast filter matches only */ 1138862bf1eSJeff Kirsher #define METH_ACCEPT_AMCAST 0x40 /* 10: Accept physical, broadcast, and all multicast packets */ 1148862bf1eSJeff Kirsher #define METH_PROMISC 0x60 /* 11: Promiscious mode */ 1158862bf1eSJeff Kirsher 1168862bf1eSJeff Kirsher #define METH_PHY_LINK_FAIL BIT(7) /* 0: Link failure detection disabled, 1: Hardware scans for link failure in PHY */ 1178862bf1eSJeff Kirsher 1188862bf1eSJeff Kirsher #define METH_MAC_IPG 0x1ffff00 1198862bf1eSJeff Kirsher 1208862bf1eSJeff Kirsher #define METH_DEFAULT_IPG ((17<<15) | (11<<22) | (21<<8)) 1218862bf1eSJeff Kirsher /* 0x172e5c00 */ /* 23, 23, 23 */ /*0x54A9500 *//*21,21,21*/ 1228862bf1eSJeff Kirsher /* Bits 8 through 14 are used to determine Inter-Packet Gap between "Back to Back" packets */ 1238862bf1eSJeff Kirsher /* The gap depends on the clock speed of the link, 80ns per increment for 100baseT, 800ns */ 1248862bf1eSJeff Kirsher /* per increment for 10BaseT */ 1258862bf1eSJeff Kirsher 1268862bf1eSJeff Kirsher /* Bits 15 through 21 are used to determine IPGR1 */ 1278862bf1eSJeff Kirsher 1288862bf1eSJeff Kirsher /* Bits 22 through 28 are used to determine IPGR2 */ 1298862bf1eSJeff Kirsher 1308862bf1eSJeff Kirsher #define METH_REV_SHIFT 29 /* Bits 29 through 31 are used to determine the revision */ 1318862bf1eSJeff Kirsher /* 000: Initial revision */ 1328862bf1eSJeff Kirsher /* 001: First revision, Improved TX concatenation */ 1338862bf1eSJeff Kirsher 1348862bf1eSJeff Kirsher 1358862bf1eSJeff Kirsher /* DMA control bits */ 1368862bf1eSJeff Kirsher #define METH_RX_OFFSET_SHIFT 12 /* Bits 12:14 of DMA control register indicate starting offset of packet data for RX operation */ 1378862bf1eSJeff Kirsher #define METH_RX_DEPTH_SHIFT 4 /* Bits 8:4 define RX fifo depth -- when # of RX fifo entries != depth, interrupt is generted */ 1388862bf1eSJeff Kirsher 1398862bf1eSJeff Kirsher #define METH_DMA_TX_EN BIT(1) /* enable TX DMA */ 1408862bf1eSJeff Kirsher #define METH_DMA_TX_INT_EN BIT(0) /* enable TX Buffer Empty interrupt */ 1418862bf1eSJeff Kirsher #define METH_DMA_RX_EN BIT(15) /* Enable RX */ 1428862bf1eSJeff Kirsher #define METH_DMA_RX_INT_EN BIT(9) /* Enable interrupt on RX packet */ 1438862bf1eSJeff Kirsher 1448862bf1eSJeff Kirsher /* RX FIFO MCL Info bits */ 1458862bf1eSJeff Kirsher #define METH_RX_FIFO_WPTR(x) (((x)>>16)&0xf) 1468862bf1eSJeff Kirsher #define METH_RX_FIFO_RPTR(x) (((x)>>8)&0xf) 1478862bf1eSJeff Kirsher #define METH_RX_FIFO_DEPTH(x) ((x)&0x1f) 1488862bf1eSJeff Kirsher 1498862bf1eSJeff Kirsher /* RX status bits */ 1508862bf1eSJeff Kirsher 1518862bf1eSJeff Kirsher #define METH_RX_ST_VALID BIT(63) 1528862bf1eSJeff Kirsher #define METH_RX_ST_RCV_CODE_VIOLATION BIT(16) 1538862bf1eSJeff Kirsher #define METH_RX_ST_DRBL_NBL BIT(17) 1548862bf1eSJeff Kirsher #define METH_RX_ST_CRC_ERR BIT(18) 1558862bf1eSJeff Kirsher #define METH_RX_ST_MCAST_PKT BIT(19) 1568862bf1eSJeff Kirsher #define METH_RX_ST_BCAST_PKT BIT(20) 1578862bf1eSJeff Kirsher #define METH_RX_ST_INV_PREAMBLE_CTX BIT(21) 1588862bf1eSJeff Kirsher #define METH_RX_ST_LONG_EVT_SEEN BIT(22) 1598862bf1eSJeff Kirsher #define METH_RX_ST_BAD_PACKET BIT(23) 1608862bf1eSJeff Kirsher #define METH_RX_ST_CARRIER_EVT_SEEN BIT(24) 1618862bf1eSJeff Kirsher #define METH_RX_ST_MCAST_FILTER_MATCH BIT(25) 1628862bf1eSJeff Kirsher #define METH_RX_ST_PHYS_ADDR_MATCH BIT(26) 1638862bf1eSJeff Kirsher 1648862bf1eSJeff Kirsher #define METH_RX_STATUS_ERRORS \ 1658862bf1eSJeff Kirsher ( \ 1668862bf1eSJeff Kirsher METH_RX_ST_RCV_CODE_VIOLATION| \ 1678862bf1eSJeff Kirsher METH_RX_ST_CRC_ERR| \ 1688862bf1eSJeff Kirsher METH_RX_ST_INV_PREAMBLE_CTX| \ 1698862bf1eSJeff Kirsher METH_RX_ST_LONG_EVT_SEEN| \ 1708862bf1eSJeff Kirsher METH_RX_ST_BAD_PACKET| \ 1718862bf1eSJeff Kirsher METH_RX_ST_CARRIER_EVT_SEEN \ 1728862bf1eSJeff Kirsher ) 1738862bf1eSJeff Kirsher /* Bits in METH_INT */ 1748862bf1eSJeff Kirsher /* Write _1_ to corresponding bit to clear */ 1758862bf1eSJeff Kirsher #define METH_INT_TX_EMPTY BIT(0) /* 0: No interrupt pending, 1: The TX ring buffer is empty */ 1768862bf1eSJeff Kirsher #define METH_INT_TX_PKT BIT(1) /* 0: No interrupt pending */ 1778862bf1eSJeff Kirsher /* 1: A TX message had the INT request bit set, the packet has been sent. */ 1788862bf1eSJeff Kirsher #define METH_INT_TX_LINK_FAIL BIT(2) /* 0: No interrupt pending, 1: PHY has reported a link failure */ 1798862bf1eSJeff Kirsher #define METH_INT_MEM_ERROR BIT(3) /* 0: No interrupt pending */ 1808862bf1eSJeff Kirsher /* 1: A memory error occurred during DMA, DMA stopped, Fatal */ 1818862bf1eSJeff Kirsher #define METH_INT_TX_ABORT BIT(4) /* 0: No interrupt pending, 1: The TX aborted operation, DMA stopped, FATAL */ 1828862bf1eSJeff Kirsher #define METH_INT_RX_THRESHOLD BIT(5) /* 0: No interrupt pending, 1: Selected receive threshold condition Valid */ 1838862bf1eSJeff Kirsher #define METH_INT_RX_UNDERFLOW BIT(6) /* 0: No interrupt pending, 1: FIFO was empty, packet could not be queued */ 1848862bf1eSJeff Kirsher #define METH_INT_RX_OVERFLOW BIT(7) /* 0: No interrupt pending, 1: DMA FIFO Overflow, DMA stopped, FATAL */ 1858862bf1eSJeff Kirsher 1868862bf1eSJeff Kirsher /*#define METH_INT_RX_RPTR_MASK 0x0001F00*/ /* Bits 8 through 12 alias of RX read-pointer */ 1878862bf1eSJeff Kirsher #define METH_INT_RX_RPTR_MASK 0x0000F00 /* Bits 8 through 11 alias of RX read-pointer - so, is Rx FIFO 16 or 32 entry?*/ 1888862bf1eSJeff Kirsher 1898862bf1eSJeff Kirsher /* Bits 13 through 15 are always 0. */ 1908862bf1eSJeff Kirsher 1918862bf1eSJeff Kirsher #define METH_INT_TX_RPTR_MASK 0x1FF0000 /* Bits 16 through 24 alias of TX read-pointer */ 1928862bf1eSJeff Kirsher 1938862bf1eSJeff Kirsher #define METH_INT_RX_SEQ_MASK 0x2E000000 /* Bits 25 through 29 are the starting seq number for the message at the */ 1948862bf1eSJeff Kirsher 1958862bf1eSJeff Kirsher /* top of the queue */ 1968862bf1eSJeff Kirsher 1978862bf1eSJeff Kirsher #define METH_INT_ERROR (METH_INT_TX_LINK_FAIL| \ 1988862bf1eSJeff Kirsher METH_INT_MEM_ERROR| \ 1998862bf1eSJeff Kirsher METH_INT_TX_ABORT| \ 2008862bf1eSJeff Kirsher METH_INT_RX_OVERFLOW| \ 2018862bf1eSJeff Kirsher METH_INT_RX_UNDERFLOW) 2028862bf1eSJeff Kirsher 2038862bf1eSJeff Kirsher #define METH_INT_MCAST_HASH BIT(30) /* If RX DMA is enabled the hash select logic output is latched here */ 2048862bf1eSJeff Kirsher 2058862bf1eSJeff Kirsher /* TX status bits */ 2068862bf1eSJeff Kirsher #define METH_TX_ST_DONE BIT(63) /* TX complete */ 2078862bf1eSJeff Kirsher #define METH_TX_ST_SUCCESS BIT(23) /* Packet was transmitted successfully */ 2088862bf1eSJeff Kirsher #define METH_TX_ST_TOOLONG BIT(24) /* TX abort due to excessive length */ 2098862bf1eSJeff Kirsher #define METH_TX_ST_UNDERRUN BIT(25) /* TX abort due to underrun (?) */ 2108862bf1eSJeff Kirsher #define METH_TX_ST_EXCCOLL BIT(26) /* TX abort due to excess collisions */ 2118862bf1eSJeff Kirsher #define METH_TX_ST_DEFER BIT(27) /* TX abort due to excess deferals */ 2128862bf1eSJeff Kirsher #define METH_TX_ST_LATECOLL BIT(28) /* TX abort due to late collision */ 2138862bf1eSJeff Kirsher 2148862bf1eSJeff Kirsher 2158862bf1eSJeff Kirsher /* Tx command header bits */ 2168862bf1eSJeff Kirsher #define METH_TX_CMD_INT_EN BIT(24) /* Generate TX interrupt when packet is sent */ 2178862bf1eSJeff Kirsher 2188862bf1eSJeff Kirsher /* Phy MDIO interface busy flag */ 2198862bf1eSJeff Kirsher #define MDIO_BUSY BIT(16) 2208862bf1eSJeff Kirsher #define MDIO_DATA_MASK 0xFFFF 2218862bf1eSJeff Kirsher /* PHY defines */ 2228862bf1eSJeff Kirsher #define PHY_QS6612X 0x0181441 /* Quality TX */ 2238862bf1eSJeff Kirsher #define PHY_ICS1889 0x0015F41 /* ICS FX */ 2248862bf1eSJeff Kirsher #define PHY_ICS1890 0x0015F42 /* ICS TX */ 2258862bf1eSJeff Kirsher #define PHY_DP83840 0x20005C0 /* National TX */ 2268862bf1eSJeff Kirsher 2278862bf1eSJeff Kirsher #define ADVANCE_RX_PTR(x) x=(x+1)&(RX_RING_ENTRIES-1) 228