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/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dclk-palmas-clk32kg-clocks.txt5 This binding uses the common clock binding ./clock-bindings.txt.
8 - compatible : "ti,palmas-clk32kg" for clk32kg clock
9 "ti,palmas-clk32kgaudio" for clk32kgaudio clock
10 - #clock-cells : shall be set to 0.
13 - ti,external-sleep-control: The external enable input pins controlled the
14 enable/disable of clocks. The external enable input pins ENABLE1,
15 ENABLE2 and NSLEEP. The valid values for the external pins are:
20 via register access and these pins do not have any control.
21 The macros of external control pins for DTS is defined at
22 dt-bindings/mfd/palmas.h
[all …]
H A Dpistachio-clock.txt5 general control, and top general control) which are instantiated individually
6 from the device-tree.
8 External clocks:
9 ----------------
11 There are three external inputs to the clock controllers which should be
12 defined with the following clock-output-names:
13 - "xtal": External 52Mhz oscillator (required)
14 - "audio_clk_in": Alternate audio reference clock (optional)
15 - "enet_clk_in": Alternate ethernet PHY clock (optional)
18 ----------------------
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H A Dbaikal,bt1-ccu-div.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-div.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 Clock Control Unit Dividers
11 - Serge Semin <fancer.lancer@gmail.com>
14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
16 connected with an external fixed rate oscillator, which signal is transformed
18 IP-blocks or to groups of blocks (clock domains). The transformation is done
19 by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The
[all …]
/openbmc/linux/drivers/pinctrl/samsung/
H A Dpinctrl-samsung.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
25 * enum pincfg_type - possible pin configuration types supported.
46 * packed together into a 16-bits. The upper 8-bits represent the configuration
47 * type and the lower 8-bits hold the value of the configuration type.
65 * enum eint_type - possible external interrupt types.
66 * @EINT_TYPE_NONE: bank does not support external interrupts
67 * @EINT_TYPE_GPIO: bank supportes external gpio interrupts
68 * @EINT_TYPE_WKUP: bank supportes external wakeup interrupts
69 * @EINT_TYPE_WKUP_MUX: bank supports multiplexed external wakeup interrupts
[all …]
/openbmc/linux/arch/m68k/include/asm/
H A DMC68328.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68328.h: '328 control registers
8 * Based on include/asm-m68knommu/MC68332.h
26 * 0xFFFFF0xx -- System Control
31 * System Control Register (SCR)
36 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
39 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
42 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
52 * 0xFFFFF1xx -- Chip-Select logic
58 * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
[all …]
H A DMC68EZ328.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68EZ328.h: 'EZ328 control registers
8 * Based on include/asm-m68knommu/MC68332.h
27 * 0xFFFFF0xx -- System Control
32 * System Control Register (SCR)
37 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
40 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
43 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
53 * 0xFFFFF1xx -- Chip-Select logic
84 #define CSA_EN 0x0001 /* Chip-Select Enable */
[all …]
H A Dm5272sim.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m5272sim.h -- ColdFire 5272 System Integration Module support.
67 #define MCFSIM_DCCR0 (MCF_MBAR + 0x57) /* DRAM 0 Control */
70 #define MCFSIM_DCCR1 (MCF_MBAR + 0x63) /* DRAM 1 Control */
75 #define MCFSIM_PACNT (MCF_MBAR + 0x80) /* Port A Control (r/w) */
78 #define MCFSIM_PBCNT (MCF_MBAR + 0x88) /* Port B Control (r/w) */
83 #define MCFSIM_PDCNT (MCF_MBAR + 0x98) /* Port D Control (r/w) */
100 #define MCF_IRQ_EINT1 65 /* External Interrupt 1 */
101 #define MCF_IRQ_EINT2 66 /* External Interrupt 2 */
102 #define MCF_IRQ_EINT3 67 /* External Interrupt 3 */
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/openbmc/linux/Documentation/devicetree/bindings/regulator/
H A Dlp872x.txt4 - compatible: "ti,lp8720" or "ti,lp8725"
5 - reg: I2C slave address. 0x7d = LP8720, 0x7a = LP8725
8 - ti,general-config: the value of LP872X_GENERAL_CFG register (u8)
10 bit[2]: BUCK output voltage control by external DVS pin or register
11 1 = external pin, 0 = bit7 of register 08h
12 bit[1]: sleep control by external DVS pin or register
13 1 = external pin, 0 = bit6 of register 08h
18 bit[4]: BUCK2 enable control. 1 = enable, 0 = disable
20 bit[2]: BUCK1 output voltage control by external DVS pin or register
22 bit[1]: LDO sleep control. 1 = sleep mode, 0 = normal
[all …]
H A Das3722-regulator.txt5 --------------------
7 regulator node. The AS3722 is having 7 DCDC step-down regulators as
8 sd[0-6], 10 LDOs as ldo[0-7], ldo[9-11]. The input supply of these
10 vsup-sd2-supply: Input supply for SD2.
11 vsup-sd3-supply: Input supply for SD3.
12 vsup-sd4-supply: Input supply for SD4.
13 vsup-sd5-supply: Input supply for SD5.
14 vin-ldo0-supply: Input supply for LDO0.
15 vin-ldo1-6-supply: Input supply for LDO1 and LDO6.
16 vin-ldo2-5-7-supply: Input supply for LDO2, LDO5 and LDO7.
[all …]
/openbmc/qemu/hw/sh4/
H A Dsh7750_regs.h2 * SH-7750 memory-mapped registers
6 * Document Number ADE-602-124C, Rev. 4.0, 4/21/00, Hitachi Ltd.
8 * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia
42 * All register has 2 addresses: in 0xff000000 - 0xffffffff (P4 address) and
43 * in 0x1f000000 - 0x1fffffff (area 7 address)
55 /* Page Table Entry High register - PTEH */
64 /* Page Table Entry Low register - PTEL */
70 #define SH7750_PTEL_V 0x00000100 /* Validity (0-entry is invalid) */
73 #define SH7750_PTEL_SZ_1KB 0x00000000 /* 1-kbyte page */
74 #define SH7750_PTEL_SZ_4KB 0x00000010 /* 4-kbyte page */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Das3722.txt4 -------------------
5 - compatible: Must be "ams,as3722".
6 - reg: I2C device address.
7 - interrupt-controller: AS3722 has internal interrupt controller which takes the
8 interrupt request from internal sub-blocks like RTC, regulators, GPIOs as well
9 as external input.
10 - #interrupt-cells: Should be set to 2 for IRQ number and flags.
12 of AS3722 are defined at dt-bindings/mfd/as3722.h
14 interrupts.txt, using dt-bindings/irq.
17 --------------------
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H A Dstericsson,ab8500.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsson Analog Baseband AB8500 and AB8505
10 - Linus Walleij <linus.walleij@linaro.org>
13 the AB8500 "Analog Baseband" is the mixed-signals integrated circuit
14 handling power management (regulators), analog-to-digital conversion
15 (ADC), battery charging, fuel gauging of the battery, battery-backed
16 RTC, PWM, USB PHY and some GPIO lines in the ST-Ericsson U8500 platforms
21 USB charging handling has changed, and it has an embedded USB-to-serial
[all …]
/openbmc/linux/drivers/memory/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
42 Used to configure the EBI (external bus interface) when the device-
43 tree is used. This bus supports NANDs, external ethernet controller,
64 controller and specifically control the Self Refresh Power Down
68 bool "Baikal-T1 CM2 L2-RAM Cache Control Block"
72 Baikal-T1 CPU is based on the MIPS P5600 Warrior IP-core. The CPU
73 resides Coherency Manager v2 with embedded 1MB L2-cache. It's
75 tags and way-select latencies of RAM access. This driver provides a
76 dt properties-based and sysfs interface for it.
84 SoCs. AEMIF stands for Asynchronous External Memory Interface and
[all …]
/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dti-phy.txt3 OMAP CONTROL PHY
6 - compatible: Should be one of
7 "ti,control-phy-otghs" - if it has otghs_control mailbox register as on OMAP4.
8 "ti,control-phy-usb2" - if it has Power down bit in control_dev_conf register
10 "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control
12 "ti,control-phy-pcie" - for pcie to support external clock for pcie and to
15 "ti,control-phy-usb2-dra7" - if it has power down register like USB2 PHY on
17 "ti,control-phy-usb2-am437" - if it has power down register like USB2 PHY on
19 - reg : register ranges as listed in the reg-names property
20 - reg-names: "otghs_control" for control-phy-otghs
[all …]
/openbmc/linux/arch/powerpc/include/asm/
H A Dipic.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * IPIC external definitions and structure.
36 #define IPIC_SICNR 0x28 /* System Internal Interrupt Control Register */
37 #define IPIC_SEPNR 0x2C /* System External Interrupt Pending Register */
40 #define IPIC_SEMSR 0x38 /* System External Interrupt Mask Register */
41 #define IPIC_SECNR 0x3C /* System External Interrupt Control Register */
44 #define IPIC_SERCR 0x48 /* System Error Control Register */
47 #define IPIC_SEFCR 0x58 /* System External Interrupt Force Register */
/openbmc/u-boot/include/usb/
H A Dulpi.h1 /* SPDX-License-Identifier: GPL-2.0 */
40 * @ulpi_vp - structure containing ULPI viewport data
48 * @speed - ULPI_FC_HIGH_SPEED, ULPI_FC_FULL_SPEED (default),
56 * @ext_power - external VBUS supply is used (default is false)
57 * @ext_indicator - external VBUS over-current indicator is used
65 * @external - external VBUS over-current indicator is used
66 * @passthru - disables ANDing of internal VBUS comparator
67 * with external VBUS input
68 * @complement - inverts the external VBUS input
70 int ulpi_set_vbus_indicator(struct ulpi_viewport *ulpi_vp, int external,
[all …]
/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Dmsm-hsusb.txt6 - compatible: Should contain "qcom,ehci-host"
7 - regs: offset and length of the register set in the memory map
8 - usb-phy: phandle for the PHY device
13 compatible = "qcom,ehci-host";
15 usb-phy = <&usb_otg>;
21 - compatible: Should contain:
22 "qcom,usb-otg-ci" for chipsets with ChipIdea 45nm PHY
23 "qcom,usb-otg-snps" for chipsets with Synopsys 28nm PHY
25 - regs: Offset and length of the register set in the memory map
26 - interrupts: interrupt-specifier for the OTG interrupt.
[all …]
/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Driscv,cpu-intc.txt1 RISC-V Hart-Level Interrupt Controller (HLIC)
2 ---------------------------------------------
4 RISC-V cores include Control Status Registers (CSRs) which are local to each
5 CPU core (HART in RISC-V terminology) and can be read or written by software.
6 Some of these CSRs are used to control local interrupts connected to the core.
10 The RISC-V supervisor ISA manual specifies three interrupt sources that are
11 attached to every HLIC: software interrupts, the timer interrupt, and external
13 timer interrupt comes from an architecturally mandated real-time timer that is
14 controlled via Supervisor Binary Interface (SBI) calls and CSR reads. External
16 via the platform-level interrupt controller (PLIC).
[all …]
/openbmc/linux/Documentation/networking/dsa/
H A Dbcm_sf2.rst8 - xDSL gateways such as BCM63138
9 - streaming/multimedia Set Top Box such as BCM7445
10 - Cable Modem/residential gateways such as BCM7145/BCM3390
13 ports, offering a range of built-in and customizable interfaces:
15 - single integrated Gigabit PHY
16 - quad integrated Gigabit PHY
17 - quad external Gigabit PHY w/ MDIO multiplexer
18 - integrated MoCA PHY
19 - several external MII/RevMII/GMII/RGMII interfaces
21 The switch also supports specific congestion control features which allow MoCA
[all …]
/openbmc/u-boot/arch/powerpc/include/asm/
H A Dimmap_85xx.h1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Copyright 2007-2012 Freescale Semiconductor, Inc.
47 /* Local-Access Registers & ECM Registers */
123 u8 res[4096 - 1 * sizeof(struct fsl_i2c_base)];
139 u8 ulcr1; /* UART1 Line Control */
140 u8 umcr1; /* UART1 Modem Control */
153 u8 ulcr2; /* UART2 Line Control */
154 u8 umcr2; /* UART2 Modem Control */
282 u32 l2cewar0; /* L2 cache external write addr 0 */
284 u32 l2cewcr0; /* L2 cache external write control 0 */
[all …]
/openbmc/linux/drivers/usb/serial/
H A Dkeyspan_usa26msg.h1 /* SPDX-License-Identifier: BSD-3-Clause */
5 Copyright (C) 1998-2000 InnoSys Incorporated. All Rights Reserved
6 This file is available under a BSD-style copyright
19 Copyright (C) 1998-2000 InnoSys Incorporated. All Rights Reserved
21 This file is available under a BSD-style copyright
44 USB OUT (host -> USAxx, transmit) messages contain a
52 USB IN (USAxx -> host, receive) messages begin with a status
100 1999apr14 add resetDataToggle to control message
102 2000jun01 add extended BSD-style copyright text
120 there are three types of "commands" sent in the control message:
[all …]
/openbmc/linux/arch/mips/include/asm/sgi/
H A Dhpc3.h40 u32 _unused0[0x1000/4 - 2]; /* padding */
41 volatile u32 pbdma_ctrl; /* pbus dma channel control register has
54 #define HPC3_PDMACTRL_HW 0x0000ff00 /* DMA High-water mark */
58 u32 _unused1[0x1000/4 - 1]; /* padding */
61 /* The HPC3 SCSI registers, this does not include external ones. */
65 u32 _unused0[0x1000/4 - 2]; /* padding */
71 volatile u32 ctrl; /* control register */
78 #define HPC3_SCTRL_CRESET 0x40 /* Resets dma channel and external controller */
89 #define HPC3_SDCFG_HW 0x01000 /* Enable 16-bit halfword DMA accesses to scsi */
92 #define HPC3_SDCFG_POLL 0x08000 /* hd_dreq polarity control */
[all …]
/openbmc/u-boot/doc/
H A DREADME.nokia_rx511 Board: Nokia RX-51 aka N900
3 This board definition results in a u-boot.bin which can be chainloaded
9 onenand as such. This u-boot is intended to be flashed to the N900 like
11 appended to u-boot.bin at 0x40000. NOLO will load the entire image into
12 (random) memory and execute u-boot, which saves hw revision, boot reason
14 uImage or boot.scr from a fat, ext2/ext3 or ext4 filesystem in external
20 NOLO so u-boot must kick watchdog to prevent reboot device (but not very
25 When U-Boot is starting it enable IBE bit in Auxiliary Control Register,
26 which is needed for Thumb-2 ISA support. It is workaround for errata 430973.
31 * 1. try boot from external SD card
[all …]
/openbmc/linux/drivers/regulator/
H A Dtps65910-regulator.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * tps65910.c -- TI tps65910
351 return -EINVAL; in tps65910_get_ctrl_register()
385 return -EINVAL; in tps65911_get_ctrl_register()
395 reg = pmic->get_ctrl_reg(id); in tps65910_set_mode()
411 return -EINVAL; in tps65910_set_mode()
420 reg = pmic->get_ctrl_reg(id); in tps65910_get_mode()
499 return srvsel - 3; in tps65910_get_voltage_dcdc_sel()
507 return opvsel - 3; in tps65910_get_voltage_dcdc_sel()
509 return -EINVAL; in tps65910_get_voltage_dcdc_sel()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/powerpc/nintendo/
H A Dwii.txt11 - model : Should be "nintendo,wii"
12 - compatible : Should be "nintendo,wii"
16 This node represents the multi-function "Hollywood" chip, which packages
21 - compatible : Should be "nintendo,hollywood"
25 Represents the interface between the graphics processor and a external
30 - compatible : should be "nintendo,hollywood-vi","nintendo,flipper-vi"
31 - reg : should contain the VI registers location and length
32 - interrupts : should contain the VI interrupt
36 Represents the data and control interface between the main processor
41 - compatible : should be "nintendo,hollywood-pi","nintendo,flipper-pi"
[all …]

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