include/asm/MC68EZ328.h

1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68EZ328.h: 'EZ328 control registers
8  * Based on include/asm-m68knommu/MC68332.h
27  * 0xFFFFF0xx -- System Control
32  * System Control Register (SCR)
37 #define SCR_WDTH8	0x01	/* 8-Bit Width Select */
40 #define SCR_BETEN	0x10	/* Bus-Error Time-Out Enable */
43 #define SCR_BETO	0x80	/* Bus-Error TimeOut */
53  * 0xFFFFF1xx -- Chip-Select logic
84 #define CSA_EN		0x0001		/* Chip-Select Enable */
85 #define CSA_SIZ_MASK	0x000e		/* Chip-Select Size */
91 #define CSA_RO		0x8000		/* Read-Only */
93 #define CSB_EN		0x0001		/* Chip-Select Enable */
94 #define CSB_SIZ_MASK	0x000e		/* Chip-Select Size */
104 #define CSB_RO		0x8000		/* Read-Only */
106 #define CSC_EN		0x0001		/* Chip-Select Enable */
107 #define CSC_SIZ_MASK	0x000e		/* Chip-Select Size */
117 #define CSC_RO		0x8000		/* Read-Only */
119 #define CSD_EN		0x0001		/* Chip-Select Enable */
120 #define CSD_SIZ_MASK	0x000e		/* Chip-Select Size */
132 #define CSD_RO		0x8000		/* Read-Only */
135  * Emulation Chip-Select Register
145  * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
150  * PLL Control Register
163 /* '328-compatible definitions */
181  * Power Control Register
188 #define PCTRL_PCEN		0x80	/* Power Control Enable */
192  * 0xFFFFF3xx -- Interrupt Controller
205  * Interrupt control Register
210 #define ICR_POL5	0x0080	/* Polarity Control for IRQ5 */
215 #define ICR_POL6	0x1000	/* Polarity Control for IRQ6 */
216 #define ICR_POL3	0x2000	/* Polarity Control for IRQ3 */
217 #define ICR_POL2	0x4000	/* Polarity Control for IRQ2 */
218 #define ICR_POL1	0x8000	/* Polarity Control for IRQ1 */
236 #define PWM_IRQ_NUM	7	/* Pulse-Width Modulator int. */
237 #define	INT0_IRQ_NUM	8	/* External INT0 */
238 #define	INT1_IRQ_NUM	9	/* External INT1 */
239 #define	INT2_IRQ_NUM	10	/* External INT2 */
240 #define	INT3_IRQ_NUM	11	/* External INT3 */
249 /* '328-compatible definitions */
262 #define IMR_MPWM	(1 << PWM_IRQ_NUM)	/* Mask Pulse-Width Modulator int. */
263 #define	IMR_MINT0	(1 << INT0_IRQ_NUM)	/* Mask External INT0 */
264 #define	IMR_MINT1	(1 << INT1_IRQ_NUM)	/* Mask External INT1 */
265 #define	IMR_MINT2	(1 << INT2_IRQ_NUM)	/* Mask External INT2 */
266 #define	IMR_MINT3	(1 << INT3_IRQ_NUM)	/* Mask External INT3 */
275 /* '328-compatible definitions */
291 #define ISR_PWM		(1 << PWM_IRQ_NUM)	/* Pulse-Width Modulator interrupt */
292 #define	ISR_INT0	(1 << INT0_IRQ_NUM)	/* External INT0 */
293 #define	ISR_INT1	(1 << INT1_IRQ_NUM)	/* External INT1 */
294 #define	ISR_INT2	(1 << INT2_IRQ_NUM)	/* External INT2 */
295 #define	ISR_INT3	(1 << INT3_IRQ_NUM)	/* External INT3 */
304 /* '328-compatible definitions */
320 #define IPR_PWM		(1 << PWM_IRQ_NUM)	/* Pulse-Width Modulator interrupt */
321 #define	IPR_INT0	(1 << INT0_IRQ_NUM)	/* External INT0 */
322 #define	IPR_INT1	(1 << INT1_IRQ_NUM)	/* External INT1 */
323 #define	IPR_INT2	(1 << INT2_IRQ_NUM)	/* External INT2 */
324 #define	IPR_INT3	(1 << INT3_IRQ_NUM)	/* External INT3 */
333 /* '328-compatible definitions */
339  * 0xFFFFF4xx -- Parallel Ports
348 #define PAPUEN_ADDR	0xfffff402		/* Port A Pull-Up enable reg */
361 #define PBPUEN_ADDR	0xfffff40a		/* Port B Pull-Up enable reg */
385 #define PCPDEN_ADDR	0xfffff412		/* Port C Pull-Down enb. reg */
409 #define PDPUEN_ADDR	0xfffff41a		/* Port D Pull-Up enable reg */
441 #define PEPUEN_ADDR	0xfffff422		/* Port E Pull-Up enable reg */
465 #define PFPUEN_ADDR	0xfffff42a		/* Port F Pull-Up enable reg */
489 #define PGPUEN_ADDR	0xfffff432		/* Port G Pull-Up enable reg */
508  * 0xFFFFF5xx -- Pulse-Width Modulator (PWM)
513  * PWM Control Register
530 /* '328-compatible definitions */
553  * 0xFFFFF6xx -- General-Purpose Timer
558  * Timer Control register
575 #define TCTL_FRR		0x0010	/* Free-Run Mode */
577 /* '328-compatible definitions */
587 /* '328-compatible definitions */
597 /* '328-compatible definitions */
607 /* '328-compatible definitions */
617 /* '328-compatible definitions */
630 /* '328-compatible definitions */
636  * 0xFFFFF8xx -- Serial Peripheral Interface Master (SPIM)
647  * SPIM Control/Status Register
663 /* '328-compatible definitions */
669  * 0xFFFFF9xx -- UART
674  * UART Status/Control Register
683 #define USTCNT_RXHE	0x0010	/* Receiver Half-Full Interrupt Enable */
687 #define USTCNT_8_7	0x0100	/* Eight or seven-bit transmission */
696 /* '328-compatible definitions */
710  * UART Baud Control Register
715 #define UBAUD_PRESCALER_MASK	0x003f	/* Actual divisor is 65 - PRESCALER */
739 #define URX_FIFO_HALF	 0x4000 /* FIFO is Half-Full */
762 /* '328-compatible definitions */
775 #define UMISC_IRDA_EN	 0x0020	/* Infra-Red Enable */
777 #define UMISC_RTSCONT	 0x0080	/* Choose RTS control */
786  * UART Non-integer Prescaler Register
795 #define NIPR_PRE_SEL		0x8000	/* Non-integer prescaler select */
798 /* generalization of uart control registers to support multiple ports: */
825  * 0xFFFFFAxx -- LCD Controller
835 #define LSSA_SSA_MASK	0x1ffffffe	/* Bits 0 and 29-31 are reserved */
849 #define LXMAX_XM_MASK	0x02f0		/* Bits 0-3 and 10-15 are reserved */
857 #define LYMAX_YM_MASK	0x01ff		/* Bits 9-15 are reserved */
865 #define LCXP_CC_MASK	0xc000		/* Cursor Control */
892  * LCD Blink Control Register
907 #define LPICF_GS_MASK	 0x03	 /* Gray-Scale Mode */
928  * LACD (LCD Alternate Crystal Direction) Rate Control Register
934 #define LACDRC_ACD_MASK	 0x0f	/* Alternate Crystal Direction Control */
947  * LCD Clocking Control Register
952 #define LCKCON_DWS_MASK	 0x0f	/* Display Wait-State */
957 /* '328-compatible definitions */
977  * LCD Frame Rate Control Modulation Register
999  * PWM Contrast Control Register
1006 #define PWMR_CCPEN	0x0100	/* Contrast Control Enable */
1014  * 0xFFFFFBxx -- Real-Time Clock (RTC)
1057  * RTC Control Register
1065 /* '328-compatible definitions */
1076 #define RTCISR_MIN	0x0002	/* 1-minute interrupt has occurred */
1078 #define RTCISR_DAY	0x0008	/* 24-hour rollover interrupt has occurred */
1080 #define RTCISR_HR	0x0020	/* 1-hour interrupt has occurred */
1097 #define RTCIENR_MIN	0x0002	/* 1-minute interrupt enable */
1099 #define RTCIENR_DAY	0x0008	/* 24-hour rollover interrupt enable */
1101 #define RTCIENR_HR	0x0020	/* 1-hour interrupt enable */
1140  * 0xFFFFFCxx -- DRAM Controller
1169  * DRAM Control Register
1176 #define DRAMC_LPR	   0x0004	/* Low-Power Refresh Enable */
1180 #define DRAMC_WS_MASK	   0x00c0	/* Wait-states */
1198  * 0xFFFFFDxx -- In-Circuit Emulation (ICE)
1215  * ICE Module Control Compare Register
1224  * ICE Module Control Mask Register
1233  * ICE Module Control Register
1251 #define ICEMSR_BRKIRQ	0x0002	/* A-Line Vector Fetch Detected */