1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 249148020SSam Ravnborg /****************************************************************************/ 349148020SSam Ravnborg 449148020SSam Ravnborg /* 549148020SSam Ravnborg * m5272sim.h -- ColdFire 5272 System Integration Module support. 649148020SSam Ravnborg * 749148020SSam Ravnborg * (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com) 849148020SSam Ravnborg * (C) Copyright 2000, Lineo Inc. (www.lineo.com) 949148020SSam Ravnborg */ 1049148020SSam Ravnborg 1149148020SSam Ravnborg /****************************************************************************/ 1249148020SSam Ravnborg #ifndef m5272sim_h 1349148020SSam Ravnborg #define m5272sim_h 1449148020SSam Ravnborg /****************************************************************************/ 1549148020SSam Ravnborg 167fc82b65SGreg Ungerer #define CPU_NAME "COLDFIRE(m5272)" 17733f31b7SGreg Ungerer #define CPU_INSTR_PER_JIFFY 3 18ce3de78aSGreg Ungerer #define MCF_BUSCLK MCF_CLK 197fc82b65SGreg Ungerer 20a12cf0a8SGreg Ungerer #include <asm/m52xxacr.h> 21a12cf0a8SGreg Ungerer 2249148020SSam Ravnborg /* 2349148020SSam Ravnborg * Define the 5272 SIM register set addresses. 2449148020SSam Ravnborg */ 25d72a5abbSGreg Ungerer #define MCFSIM_SCR (MCF_MBAR + 0x04) /* SIM Config reg */ 26d72a5abbSGreg Ungerer #define MCFSIM_SPR (MCF_MBAR + 0x06) /* System Protection */ 27d72a5abbSGreg Ungerer #define MCFSIM_PMR (MCF_MBAR + 0x08) /* Power Management */ 28d72a5abbSGreg Ungerer #define MCFSIM_APMR (MCF_MBAR + 0x0e) /* Active Low Power */ 29d72a5abbSGreg Ungerer #define MCFSIM_DIR (MCF_MBAR + 0x10) /* Device Identity */ 3049148020SSam Ravnborg 31c986a3d5SGreg Ungerer #define MCFSIM_ICR1 (MCF_MBAR + 0x20) /* Intr Ctrl reg 1 */ 32c986a3d5SGreg Ungerer #define MCFSIM_ICR2 (MCF_MBAR + 0x24) /* Intr Ctrl reg 2 */ 33c986a3d5SGreg Ungerer #define MCFSIM_ICR3 (MCF_MBAR + 0x28) /* Intr Ctrl reg 3 */ 34c986a3d5SGreg Ungerer #define MCFSIM_ICR4 (MCF_MBAR + 0x2c) /* Intr Ctrl reg 4 */ 3549148020SSam Ravnborg 366a3a786dSGreg Ungerer #define MCFSIM_ISR (MCF_MBAR + 0x30) /* Intr Source */ 376a3a786dSGreg Ungerer #define MCFSIM_PITR (MCF_MBAR + 0x34) /* Intr Transition */ 386a3a786dSGreg Ungerer #define MCFSIM_PIWR (MCF_MBAR + 0x38) /* Intr Wakeup */ 396a3a786dSGreg Ungerer #define MCFSIM_PIVR (MCF_MBAR + 0x3f) /* Intr Vector */ 4049148020SSam Ravnborg 41660b73e3SGreg Ungerer #define MCFSIM_WRRR (MCF_MBAR + 0x280) /* Watchdog reference */ 42660b73e3SGreg Ungerer #define MCFSIM_WIRR (MCF_MBAR + 0x284) /* Watchdog interrupt */ 43660b73e3SGreg Ungerer #define MCFSIM_WCR (MCF_MBAR + 0x288) /* Watchdog counter */ 44660b73e3SGreg Ungerer #define MCFSIM_WER (MCF_MBAR + 0x28c) /* Watchdog event */ 4549148020SSam Ravnborg 461419ea3bSGreg Ungerer #define MCFSIM_CSBR0 (MCF_MBAR + 0x40) /* CS0 Base Address */ 471419ea3bSGreg Ungerer #define MCFSIM_CSOR0 (MCF_MBAR + 0x44) /* CS0 Option */ 481419ea3bSGreg Ungerer #define MCFSIM_CSBR1 (MCF_MBAR + 0x48) /* CS1 Base Address */ 491419ea3bSGreg Ungerer #define MCFSIM_CSOR1 (MCF_MBAR + 0x4c) /* CS1 Option */ 501419ea3bSGreg Ungerer #define MCFSIM_CSBR2 (MCF_MBAR + 0x50) /* CS2 Base Address */ 511419ea3bSGreg Ungerer #define MCFSIM_CSOR2 (MCF_MBAR + 0x54) /* CS2 Option */ 521419ea3bSGreg Ungerer #define MCFSIM_CSBR3 (MCF_MBAR + 0x58) /* CS3 Base Address */ 531419ea3bSGreg Ungerer #define MCFSIM_CSOR3 (MCF_MBAR + 0x5c) /* CS3 Option */ 541419ea3bSGreg Ungerer #define MCFSIM_CSBR4 (MCF_MBAR + 0x60) /* CS4 Base Address */ 551419ea3bSGreg Ungerer #define MCFSIM_CSOR4 (MCF_MBAR + 0x64) /* CS4 Option */ 561419ea3bSGreg Ungerer #define MCFSIM_CSBR5 (MCF_MBAR + 0x68) /* CS5 Base Address */ 571419ea3bSGreg Ungerer #define MCFSIM_CSOR5 (MCF_MBAR + 0x6c) /* CS5 Option */ 581419ea3bSGreg Ungerer #define MCFSIM_CSBR6 (MCF_MBAR + 0x70) /* CS6 Base Address */ 591419ea3bSGreg Ungerer #define MCFSIM_CSOR6 (MCF_MBAR + 0x74) /* CS6 Option */ 601419ea3bSGreg Ungerer #define MCFSIM_CSBR7 (MCF_MBAR + 0x78) /* CS7 Base Address */ 611419ea3bSGreg Ungerer #define MCFSIM_CSOR7 (MCF_MBAR + 0x7c) /* CS7 Option */ 6249148020SSam Ravnborg 63d72a5abbSGreg Ungerer #define MCFSIM_SDCR (MCF_MBAR + 0x180) /* SDRAM Config */ 64d72a5abbSGreg Ungerer #define MCFSIM_SDTR (MCF_MBAR + 0x184) /* SDRAM Timing */ 65d72a5abbSGreg Ungerer #define MCFSIM_DCAR0 (MCF_MBAR + 0x4c) /* DRAM 0 Address */ 66d72a5abbSGreg Ungerer #define MCFSIM_DCMR0 (MCF_MBAR + 0x50) /* DRAM 0 Mask */ 67d72a5abbSGreg Ungerer #define MCFSIM_DCCR0 (MCF_MBAR + 0x57) /* DRAM 0 Control */ 68d72a5abbSGreg Ungerer #define MCFSIM_DCAR1 (MCF_MBAR + 0x58) /* DRAM 1 Address */ 69d72a5abbSGreg Ungerer #define MCFSIM_DCMR1 (MCF_MBAR + 0x5c) /* DRAM 1 Mask reg */ 70d72a5abbSGreg Ungerer #define MCFSIM_DCCR1 (MCF_MBAR + 0x63) /* DRAM 1 Control */ 7149148020SSam Ravnborg 72023e0555SGreg Ungerer #define MCFUART_BASE0 (MCF_MBAR + 0x100) /* Base address UART0 */ 73023e0555SGreg Ungerer #define MCFUART_BASE1 (MCF_MBAR + 0x140) /* Base address UART1 */ 7457015421SGreg Ungerer 75316f2c48Ssfking@fdwdc.com #define MCFSIM_PACNT (MCF_MBAR + 0x80) /* Port A Control (r/w) */ 76316f2c48Ssfking@fdwdc.com #define MCFSIM_PADDR (MCF_MBAR + 0x84) /* Port A Direction (r/w) */ 77316f2c48Ssfking@fdwdc.com #define MCFSIM_PADAT (MCF_MBAR + 0x86) /* Port A Data (r/w) */ 78316f2c48Ssfking@fdwdc.com #define MCFSIM_PBCNT (MCF_MBAR + 0x88) /* Port B Control (r/w) */ 79316f2c48Ssfking@fdwdc.com #define MCFSIM_PBDDR (MCF_MBAR + 0x8c) /* Port B Direction (r/w) */ 80316f2c48Ssfking@fdwdc.com #define MCFSIM_PBDAT (MCF_MBAR + 0x8e) /* Port B Data (r/w) */ 81316f2c48Ssfking@fdwdc.com #define MCFSIM_PCDDR (MCF_MBAR + 0x94) /* Port C Direction (r/w) */ 82316f2c48Ssfking@fdwdc.com #define MCFSIM_PCDAT (MCF_MBAR + 0x96) /* Port C Data (r/w) */ 83316f2c48Ssfking@fdwdc.com #define MCFSIM_PDCNT (MCF_MBAR + 0x98) /* Port D Control (r/w) */ 8449148020SSam Ravnborg 85babc08b7SGreg Ungerer #define MCFDMA_BASE0 (MCF_MBAR + 0xe0) /* Base address DMA 0 */ 86babc08b7SGreg Ungerer 8758f0ac98SGreg Ungerer #define MCFTIMER_BASE1 (MCF_MBAR + 0x200) /* Base address TIMER1 */ 8858f0ac98SGreg Ungerer #define MCFTIMER_BASE2 (MCF_MBAR + 0x220) /* Base address TIMER2 */ 8958f0ac98SGreg Ungerer #define MCFTIMER_BASE3 (MCF_MBAR + 0x240) /* Base address TIMER4 */ 9058f0ac98SGreg Ungerer #define MCFTIMER_BASE4 (MCF_MBAR + 0x260) /* Base address TIMER3 */ 9158f0ac98SGreg Ungerer 929a11b493SGreg Ungerer #define MCFFEC_BASE0 (MCF_MBAR + 0x840) /* Base FEC ethernet */ 939a11b493SGreg Ungerer #define MCFFEC_SIZE0 0x1d0 949a11b493SGreg Ungerer 9504b75b10SGreg Ungerer /* 9604b75b10SGreg Ungerer * Define system peripheral IRQ usage. 9704b75b10SGreg Ungerer */ 989075216dSGreg Ungerer #define MCFINT_VECBASE 64 /* Base of interrupts */ 999075216dSGreg Ungerer #define MCF_IRQ_SPURIOUS 64 /* User Spurious */ 1009075216dSGreg Ungerer #define MCF_IRQ_EINT1 65 /* External Interrupt 1 */ 1019075216dSGreg Ungerer #define MCF_IRQ_EINT2 66 /* External Interrupt 2 */ 1029075216dSGreg Ungerer #define MCF_IRQ_EINT3 67 /* External Interrupt 3 */ 1039075216dSGreg Ungerer #define MCF_IRQ_EINT4 68 /* External Interrupt 4 */ 1049075216dSGreg Ungerer #define MCF_IRQ_TIMER1 69 /* Timer 1 */ 1059075216dSGreg Ungerer #define MCF_IRQ_TIMER2 70 /* Timer 2 */ 1069075216dSGreg Ungerer #define MCF_IRQ_TIMER3 71 /* Timer 3 */ 1079075216dSGreg Ungerer #define MCF_IRQ_TIMER4 72 /* Timer 4 */ 108023e0555SGreg Ungerer #define MCF_IRQ_UART0 73 /* UART 0 */ 109023e0555SGreg Ungerer #define MCF_IRQ_UART1 74 /* UART 1 */ 1109075216dSGreg Ungerer #define MCF_IRQ_PLIP 75 /* PLIC 2Khz Periodic */ 1119075216dSGreg Ungerer #define MCF_IRQ_PLIA 76 /* PLIC Asynchronous */ 1129075216dSGreg Ungerer #define MCF_IRQ_USB0 77 /* USB Endpoint 0 */ 1139075216dSGreg Ungerer #define MCF_IRQ_USB1 78 /* USB Endpoint 1 */ 1149075216dSGreg Ungerer #define MCF_IRQ_USB2 79 /* USB Endpoint 2 */ 1159075216dSGreg Ungerer #define MCF_IRQ_USB3 80 /* USB Endpoint 3 */ 1169075216dSGreg Ungerer #define MCF_IRQ_USB4 81 /* USB Endpoint 4 */ 1179075216dSGreg Ungerer #define MCF_IRQ_USB5 82 /* USB Endpoint 5 */ 1189075216dSGreg Ungerer #define MCF_IRQ_USB6 83 /* USB Endpoint 6 */ 1199075216dSGreg Ungerer #define MCF_IRQ_USB7 84 /* USB Endpoint 7 */ 1209075216dSGreg Ungerer #define MCF_IRQ_DMA 85 /* DMA Controller */ 1219a11b493SGreg Ungerer #define MCF_IRQ_FECRX0 86 /* Ethernet Receiver */ 1229a11b493SGreg Ungerer #define MCF_IRQ_FECTX0 87 /* Ethernet Transmitter */ 1239a11b493SGreg Ungerer #define MCF_IRQ_FECENTC0 88 /* Ethernet Non-Time Critical */ 1249075216dSGreg Ungerer #define MCF_IRQ_QSPI 89 /* Queued Serial Interface */ 1259075216dSGreg Ungerer #define MCF_IRQ_EINT5 90 /* External Interrupt 5 */ 1269075216dSGreg Ungerer #define MCF_IRQ_EINT6 91 /* External Interrupt 6 */ 1279075216dSGreg Ungerer #define MCF_IRQ_SWTO 92 /* Software Watchdog */ 1289075216dSGreg Ungerer #define MCFINT_VECMAX 95 /* Maxmum interrupt */ 1299075216dSGreg Ungerer 1309075216dSGreg Ungerer #define MCF_IRQ_TIMER MCF_IRQ_TIMER1 1319075216dSGreg Ungerer #define MCF_IRQ_PROFILER MCF_IRQ_TIMER2 13249148020SSam Ravnborg 133316f2c48Ssfking@fdwdc.com /* 134316f2c48Ssfking@fdwdc.com * Generic GPIO support 135316f2c48Ssfking@fdwdc.com */ 136316f2c48Ssfking@fdwdc.com #define MCFGPIO_PIN_MAX 48 137316f2c48Ssfking@fdwdc.com #define MCFGPIO_IRQ_MAX -1 138316f2c48Ssfking@fdwdc.com #define MCFGPIO_IRQ_VECBASE -1 13941e5be6aSGreg Ungerer 14049148020SSam Ravnborg /****************************************************************************/ 14149148020SSam Ravnborg #endif /* m5272sim_h */ 142