include/asm/MC68328.h

1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68328.h: '328 control registers
8  * Based on include/asm-m68knommu/MC68332.h
26  * 0xFFFFF0xx -- System Control
31  * System Control Register (SCR)
36 #define SCR_WDTH8	0x01	/* 8-Bit Width Select */
39 #define SCR_BETEN	0x10	/* Bus-Error Time-Out Enable */
42 #define SCR_BETO	0x80	/* Bus-Error TimeOut */
52  * 0xFFFFF1xx -- Chip-Select logic
58  * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
76 #define GRPBASE_GBA_MASK  0xfff0	/* Group Base Address (bits 31-20) */
91 #define GRMMASK_GMA_MASK 0xfffff0	/* Group Base Mask (bits 31-20) */
94  * Chip-Select Option Registers (group A)
108 #define CSA_RO		0x00000008	/* Read-Only */
109 #define CSA_AM_MASK	0x0000ff00	/* Address Mask (bits 23-16) */
112 #define CSA_AC_MASK	0xff000000	/* Address Compare (bits 23-16) */
116  * Chip-Select Option Registers (group B)
130 #define CSB_RO		0x00000008	/* Read-Only */
131 #define CSB_AM_MASK	0x0000ff00	/* Address Mask (bits 23-16) */
134 #define CSB_AC_MASK	0xff000000	/* Address Compare (bits 23-16) */
138  * Chip-Select Option Registers (group C)
152 #define CSC_RO		0x00000008	/* Read-Only */
153 #define CSC_AM_MASK	0x0000fff0	/* Address Mask (bits 23-12) */
156 #define CSC_AC_MASK	0xfff00000	/* Address Compare (bits 23-12) */
160  * Chip-Select Option Registers (group D)
174 #define CSD_RO		0x00000008	/* Read-Only */
175 #define CSD_AM_MASK	0x0000fff0	/* Address Mask (bits 23-12) */
178 #define CSD_AC_MASK	0xfff00000	/* Address Compare (bits 23-12) */
183  * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
188  * PLL Control Register
200 /* 'EZ328-compatible definitions */
218  * Power Control Register
225 #define PCTRL_STOP		0x40	/* Enter power-save mode immediately */
226 #define PCTRL_PCEN		0x80	/* Power Control Enable */
230  * 0xFFFFF3xx -- Interrupt Controller
243  * Interrupt control Register
252 #define ICR_POL6	0x1000	/* Polarity Control for IRQ6 */
253 #define ICR_POL3	0x2000	/* Polarity Control for IRQ3 */
254 #define ICR_POL2	0x4000	/* Polarity Control for IRQ2 */
255 #define ICR_POL1	0x8000	/* Polarity Control for IRQ1 */
273 #define PWM_IRQ_NUM	7	/* Pulse-Width Modulator int. */
274 #define	INT0_IRQ_NUM	8	/* External INT0 */
275 #define	INT1_IRQ_NUM	9	/* External INT1 */
276 #define	INT2_IRQ_NUM	10	/* External INT2 */
277 #define	INT3_IRQ_NUM	11	/* External INT3 */
278 #define	INT4_IRQ_NUM	12	/* External INT4 */
279 #define	INT5_IRQ_NUM	13	/* External INT5 */
280 #define	INT6_IRQ_NUM	14	/* External INT6 */
281 #define	INT7_IRQ_NUM	15	/* External INT7 */
291 /* '328-compatible definitions */
304 #define IMR_MPWM	(1 << PWM_IRQ_NUM)	/* Mask Pulse-Width Modulator int. */
305 #define	IMR_MINT0	(1 << INT0_IRQ_NUM)	/* Mask External INT0 */
306 #define	IMR_MINT1	(1 << INT1_IRQ_NUM)	/* Mask External INT1 */
307 #define	IMR_MINT2	(1 << INT2_IRQ_NUM)	/* Mask External INT2 */
308 #define	IMR_MINT3	(1 << INT3_IRQ_NUM)	/* Mask External INT3 */
309 #define	IMR_MINT4	(1 << INT4_IRQ_NUM)	/* Mask External INT4 */
310 #define	IMR_MINT5	(1 << INT5_IRQ_NUM)	/* Mask External INT5 */
311 #define	IMR_MINT6	(1 << INT6_IRQ_NUM)	/* Mask External INT6 */
312 #define	IMR_MINT7	(1 << INT7_IRQ_NUM)	/* Mask External INT7 */
322 /* 'EZ328-compatible definitions */
327  * Interrupt Wake-Up Enable Register
338 #define IWR_PWM		(1 << PWM_IRQ_NUM)	/* Pulse-Width Modulator int. */
339 #define	IWR_INT0	(1 << INT0_IRQ_NUM)	/* External INT0 */
340 #define	IWR_INT1	(1 << INT1_IRQ_NUM)	/* External INT1 */
341 #define	IWR_INT2	(1 << INT2_IRQ_NUM)	/* External INT2 */
342 #define	IWR_INT3	(1 << INT3_IRQ_NUM)	/* External INT3 */
343 #define	IWR_INT4	(1 << INT4_IRQ_NUM)	/* External INT4 */
344 #define	IWR_INT5	(1 << INT5_IRQ_NUM)	/* External INT5 */
345 #define	IWR_INT6	(1 << INT6_IRQ_NUM)	/* External INT6 */
346 #define	IWR_INT7	(1 << INT7_IRQ_NUM)	/* External INT7 */
368 #define ISR_PWM		(1 << PWM_IRQ_NUM)	/* Pulse-Width Modulator int. */
369 #define	ISR_INT0	(1 << INT0_IRQ_NUM)	/* External INT0 */
370 #define	ISR_INT1	(1 << INT1_IRQ_NUM)	/* External INT1 */
371 #define	ISR_INT2	(1 << INT2_IRQ_NUM)	/* External INT2 */
372 #define	ISR_INT3	(1 << INT3_IRQ_NUM)	/* External INT3 */
373 #define	ISR_INT4	(1 << INT4_IRQ_NUM)	/* External INT4 */
374 #define	ISR_INT5	(1 << INT5_IRQ_NUM)	/* External INT5 */
375 #define	ISR_INT6	(1 << INT6_IRQ_NUM)	/* External INT6 */
376 #define	ISR_INT7	(1 << INT7_IRQ_NUM)	/* External INT7 */
386 /* 'EZ328-compatible definitions */
402 #define IPR_PWM		(1 << PWM_IRQ_NUM)	/* Pulse-Width Modulator int. */
403 #define	IPR_INT0	(1 << INT0_IRQ_NUM)	/* External INT0 */
404 #define	IPR_INT1	(1 << INT1_IRQ_NUM)	/* External INT1 */
405 #define	IPR_INT2	(1 << INT2_IRQ_NUM)	/* External INT2 */
406 #define	IPR_INT3	(1 << INT3_IRQ_NUM)	/* External INT3 */
407 #define	IPR_INT4	(1 << INT4_IRQ_NUM)	/* External INT4 */
408 #define	IPR_INT5	(1 << INT5_IRQ_NUM)	/* External INT5 */
409 #define	IPR_INT6	(1 << INT6_IRQ_NUM)	/* External INT6 */
410 #define	IPR_INT7	(1 << INT7_IRQ_NUM)	/* External INT7 */
420 /* 'EZ328-compatible definitions */
426  * 0xFFFFF4xx -- Parallel Ports
442 #define PA_A(x)		PA((x) - 16)	/* This is specific to PA only! */
501 #define PDPUEN_ADDR	0xfffff41a		/* Port D Pull-Up enable reg */
530 #define PEPUEN_ADDR	0xfffff422		/* Port E Pull-Up enable reg */
553 #define PFPUEN_ADDR	0xfffff42a		/* Port F Pull-Up enable reg */
562 #define PF_A(x)		PF((x) - 24)	/* This is Port F specific only */
578 #define PGPUEN_ADDR	0xfffff432		/* Port G Pull-Up enable reg */
617 #define PKPUEN_ADDR	0xfffff442		/* Port K Pull-Up enable reg */
632 #define PMPUEN_ADDR	0xfffff43a		/* Port M Pull-Up enable reg */
644  * 0xFFFFF5xx -- Pulse-Width Modulator (PWM)
649  * PWM Control Register
663 /* 'EZ328-compatible definitions */
686  * 0xFFFFF6xx -- General-Purpose Timers
691  * Timer Unit 1 and 2 Control Registers
710 #define TCTL_FRR		0x0010	/* Free-Run Mode */
712 /* 'EZ328-compatible definitions */
724 /* 'EZ328-compatible definitions */
736 /* 'EZ328-compatible definitions */
748 /* 'EZ328-compatible definitions */
760 /* 'EZ328-compatible definitions */
775 /* 'EZ328-compatible definitions */
792  * Watchdog Control and Status Register
803  * 0xFFFFF7xx -- Serial Peripheral Interface Slave (SPIS)
816 #define SPISR_DATA_MASK	 0x00ff	/* Shifted data from the external device */
819 #define SPISR_POL	 0x0200	/* SPSCLK polarity control */
829  * 0xFFFFF8xx -- Serial Peripheral Interface Master (SPIM)
840  * SPIM Control/Status Register
856 /* 'EZ328-compatible definitions */
861  * 0xFFFFF9xx -- UART
866  * UART Status/Control Register
875 #define USTCNT_RXHALFEN		0x0010	/* Receiver Half-Full Int Enable */
879 #define USTCNT_8_7		0x0100	/* Eight or seven-bit transmission */
888 /* 'EZ328-compatible definitions */
902  * UART Baud Control Register
907 #define UBAUD_PRESCALER_MASK	0x003f	/* Actual divisor is 65 - PRESCALER */
933 #define URX_FIFO_HALF	 0x4000 /* FIFO is Half-Full */
955 /* 'EZ328-compatible definitions */
968 #define UMISC_IRDA_EN	 0x0020	/* Infra-Red Enable */
970 #define UMISC_RTSCONT	 0x0080	/* Choose RTS control */
976 /* generalization of uart control registers to support multiple ports: */
1003  * 0xFFFFFAxx -- LCD Controller
1027 #define LXMAX_XM_MASK	0x02ff		/* Bits 0-3 are reserved */
1035 #define LYMAX_YM_MASK	0x02ff		/* Bits 10-15 are reserved */
1043 #define LCXP_CC_MASK	0xc000		/* Cursor Control */
1070  * LCD Blink Control Register
1085 #define LPICF_GS_MASK	 0x01	 /* Gray-Scale Mode */
1105  * LACD (LCD Alternate Crystal Direction) Rate Control Register
1110 #define LACDRC_ACD_MASK	 0x0f	/* Alternate Crystal Direction Control */
1123  * LCD Clocking Control Register
1130 #define LCKCON_DWS_MASK	 0x3c	/* Display Wait-State */
1135 /* 'EZ328-compatible definitions */
1165  * LCD Frame Rate Control Modulation Register
1192  * 0xFFFFFBxx -- Real-Time Clock (RTC)
1223  * RTC Control Register
1231 /* 'EZ328-compatible definitions */
1242 #define RTCISR_MIN	0x0002	/* 1-minute interrupt has occurred */
1244 #define RTCISR_DAY	0x0008	/* 24-hour rollover interrupt has occurred */
1254 #define RTCIENR_MIN	0x0002	/* 1-minute interrupt enable */
1256 #define RTCIENR_DAY	0x0008	/* 24-hour rollover interrupt enable */