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/openbmc/linux/Documentation/devicetree/bindings/arm/mediatek/
H A Dmediatek,ethsys.txt1 Mediatek ethsys controller
4 The Mediatek ethsys controller provides various clocks to the system.
9 - "mediatek,mt2701-ethsys", "syscon"
10 - "mediatek,mt7622-ethsys", "syscon"
11 - "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon"
12 - "mediatek,mt7629-ethsys", "syscon"
13 - "mediatek,mt7981-ethsys", "syscon"
14 - "mediatek,mt7986-ethsys", "syscon"
18 The ethsys controller uses the common clk binding from
24 ethsys: clock-controller@1b000000 {
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dmediatek,net.yaml52 mediatek,ethsys:
395 - mediatek,ethsys
417 <&ethsys CLK_ETH_ESW_EN>,
418 <&ethsys CLK_ETH_GP0_EN>,
419 <&ethsys CLK_ETH_GP1_EN>,
420 <&ethsys CLK_ETH_GP2_EN>,
432 mediatek,ethsys = <&ethsys>;
497 clocks = <&ethsys CLK_ETH_FE_EN>,
498 <&ethsys CLK_ETH_GP2_EN>,
499 <&ethsys CLK_ETH_GP1_EN>,
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dmt7629.dtsi228 ethsys: syscon@1b000000 { label
229 compatible = "mediatek,mt7629-ethsys", "syscon";
240 <&ethsys CLK_ETH_ESW_EN>,
241 <&ethsys CLK_ETH_GP0_EN>,
242 <&ethsys CLK_ETH_GP1_EN>,
243 <&ethsys CLK_ETH_GP2_EN>,
244 <&ethsys CLK_ETH_FE_EN>,
266 resets = <&ethsys ETHSYS_FE_RST>;
268 mediatek,ethsys = <&ethsys>;
H A Dmt7623.dtsi251 ethsys: syscon@1b000000 { label
252 compatible = "mediatek,mt7623-ethsys", "syscon";
262 <&ethsys CLK_ETHSYS_ESW>,
263 <&ethsys CLK_ETHSYS_GP1>,
264 <&ethsys CLK_ETHSYS_GP2>,
268 resets = <&ethsys ETHSYS_FE_RST>,
269 <&ethsys ETHSYS_MCM_RST>;
271 mediatek,ethsys = <&ethsys>;
/openbmc/linux/arch/arm/boot/dts/mediatek/
H A Dmt7629.dtsi430 ethsys: syscon@1b000000 { label
431 compatible = "mediatek,mt7629-ethsys", "syscon";
445 <&ethsys CLK_ETH_ESW_EN>,
446 <&ethsys CLK_ETH_GP0_EN>,
447 <&ethsys CLK_ETH_GP1_EN>,
448 <&ethsys CLK_ETH_GP2_EN>,
449 <&ethsys CLK_ETH_FE_EN>,
471 mediatek,ethsys = <&ethsys>;
H A Dmt2701.dtsi720 ethsys: syscon@1b000000 { label
721 compatible = "mediatek,mt2701-ethsys", "syscon";
734 <&ethsys CLK_ETHSYS_ESW>,
735 <&ethsys CLK_ETHSYS_GP1>,
736 <&ethsys CLK_ETHSYS_GP2>,
739 resets = <&ethsys MT2701_ETHSYS_FE_RST>,
740 <&ethsys MT2701_ETHSYS_GMAC_RST>,
741 <&ethsys MT2701_ETHSYS_PPE_RST>;
744 mediatek,ethsys = <&ethsys>;
H A Dmt7623.dtsi940 ethsys: syscon@1b000000 { label
941 compatible = "mediatek,mt7623-ethsys",
942 "mediatek,mt2701-ethsys",
953 clocks = <&ethsys CLK_ETHSYS_HSDMA>;
968 <&ethsys CLK_ETHSYS_ESW>,
969 <&ethsys CLK_ETHSYS_GP1>,
970 <&ethsys CLK_ETHSYS_GP2>,
973 resets = <&ethsys MT2701_ETHSYS_FE_RST>,
974 <&ethsys MT2701_ETHSYS_GMAC_RST>,
975 <&ethsys MT2701_ETHSYS_PPE_RST>;
[all …]
H A Dmt7623a.dtsi54 resets = <&ethsys MT2701_ETHSYS_MCM_RST>;
/openbmc/linux/drivers/net/ethernet/mediatek/
H A Dmtk_eth_path.c144 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); in set_mux_gmac1_gmac2_to_sgmii_rgmii()
159 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, in set_mux_gmac1_gmac2_to_sgmii_rgmii()
173 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); in set_mux_gmac12_to_gephy_sgmii()
190 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, in set_mux_gmac12_to_gephy_sgmii()
H A Dmtk_eth_soc.c475 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, in mt7621_gmac0_rgmii_adjust()
612 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); in mtk_mac_config()
615 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); in mtk_mac_config()
626 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); in mtk_mac_config()
628 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, in mtk_mac_config()
672 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, in mtk_mac_finish()
3533 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, in ethsys_reset()
3538 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, in ethsys_reset()
3662 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0); in mtk_hw_reset()
3686 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, in mtk_hw_reset()
[all …]
/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt7986a.dtsi490 ethsys: syscon@15000000 { label
491 compatible = "mediatek,mt7986-ethsys",
531 clocks = <&ethsys CLK_ETH_FE_EN>,
532 <&ethsys CLK_ETH_GP2_EN>,
533 <&ethsys CLK_ETH_GP1_EN>,
534 <&ethsys CLK_ETH_WOCPU1_EN>,
535 <&ethsys CLK_ETH_WOCPU0_EN>,
558 mediatek,ethsys = <&ethsys>;
H A Dmt7622.dtsi925 ethsys: clock-controller@1b000000 { label
926 compatible = "mediatek,mt7622-ethsys",
937 clocks = <&ethsys CLK_ETH_HSDMA_EN>;
971 <&ethsys CLK_ETH_ESW_EN>,
972 <&ethsys CLK_ETH_GP0_EN>,
973 <&ethsys CLK_ETH_GP1_EN>,
974 <&ethsys CLK_ETH_GP2_EN>,
986 mediatek,ethsys = <&ethsys>;
/openbmc/linux/drivers/clk/mediatek/
H A DKconfig54 bool "Clock driver for MediaTek MT2701 ethsys"
57 This driver supports MediaTek MT2701 ethsys clocks.
349 tristate "Clock driver for MediaTek MT7622 ETHSYS"
379 bool "Clock driver for MediaTek MT7629 ETHSYS"
402 tristate "Clock driver for MediaTek MT7981 ETHSYS"
419 tristate "Clock driver for MediaTek MT7986 ETHSYS"
H A Dclk-mt2701-eth.c49 { .compatible = "mediatek,mt2701-ethsys", .data = &eth_desc },
H A Dclk-mt7622-eth.c74 { .compatible = "mediatek,mt7622-ethsys", .data = &eth_desc },
H A Dclk-mt7986-eth.c82 { .compatible = "mediatek,mt7986-ethsys", .data = &eth_desc },
/openbmc/u-boot/include/dt-bindings/reset/
H A Dmtk-reset.h9 /* ETHSYS */
/openbmc/linux/Documentation/devicetree/bindings/crypto/
H A Dmediatek-crypto.txt22 clocks = <&ethsys CLK_ETHSYS_CRYPTO>;
/openbmc/linux/include/dt-bindings/reset/
H A Dmt7986-resets.h46 /* ETHSYS Subsystem resets */
H A Dmt2701-resets.h75 /* ETHSYS resets */
H A Dmt7622-reset.h76 /* ETHSYS Subsystem resets */
/openbmc/linux/Documentation/devicetree/bindings/dma/
H A Dmtk-hsdma.txt27 clocks = <&ethsys CLK_ETHSYS_HSDMA>;
/openbmc/u-boot/drivers/clk/mediatek/
H A Dclk-mt7629.c494 /* ethsys */
613 debug("Warning: failed to bind ethsys reset controller\n"); in mt7629_ethsys_bind()
645 { .compatible = "mediatek,mt7629-ethsys", },
708 .name = "mt7629-clock-ethsys",
H A Dclk-mt7623.c694 /* ethsys */
793 debug("Warning: failed to bind ethsys reset controller\n"); in mt7623_ethsys_bind()
820 { .compatible = "mediatek,mt7623-ethsys" },
878 .name = "mt7623-clock-ethsys",
/openbmc/linux/include/dt-bindings/clock/
H A Dmt7986-clk.h161 /* ETHSYS */

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