11802d0beSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 27f4fbf79SSean Wang /* 37f4fbf79SSean Wang * Copyright (c) 2017 MediaTek Inc. 47f4fbf79SSean Wang * Author: Sean Wang <sean.wang@mediatek.com> 57f4fbf79SSean Wang */ 67f4fbf79SSean Wang 77f4fbf79SSean Wang #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7622 87f4fbf79SSean Wang #define _DT_BINDINGS_RESET_CONTROLLER_MT7622 97f4fbf79SSean Wang 107f4fbf79SSean Wang /* INFRACFG resets */ 117f4fbf79SSean Wang #define MT7622_INFRA_EMI_REG_RST 0 127f4fbf79SSean Wang #define MT7622_INFRA_DRAMC0_A0_RST 1 137f4fbf79SSean Wang #define MT7622_INFRA_APCIRQ_EINT_RST 3 147f4fbf79SSean Wang #define MT7622_INFRA_APXGPT_RST 4 157f4fbf79SSean Wang #define MT7622_INFRA_SCPSYS_RST 5 167f4fbf79SSean Wang #define MT7622_INFRA_PMIC_WRAP_RST 7 177f4fbf79SSean Wang #define MT7622_INFRA_IRRX_RST 9 187f4fbf79SSean Wang #define MT7622_INFRA_EMI_RST 16 197f4fbf79SSean Wang #define MT7622_INFRA_WED0_RST 17 207f4fbf79SSean Wang #define MT7622_INFRA_DRAMC_RST 18 217f4fbf79SSean Wang #define MT7622_INFRA_CCI_INTF_RST 19 227f4fbf79SSean Wang #define MT7622_INFRA_TRNG_RST 21 237f4fbf79SSean Wang #define MT7622_INFRA_SYSIRQ_RST 22 247f4fbf79SSean Wang #define MT7622_INFRA_WED1_RST 25 257f4fbf79SSean Wang 267f4fbf79SSean Wang /* PERICFG Subsystem resets */ 277f4fbf79SSean Wang #define MT7622_PERI_UART0_SW_RST 0 287f4fbf79SSean Wang #define MT7622_PERI_UART1_SW_RST 1 297f4fbf79SSean Wang #define MT7622_PERI_UART2_SW_RST 2 307f4fbf79SSean Wang #define MT7622_PERI_UART3_SW_RST 3 317f4fbf79SSean Wang #define MT7622_PERI_UART4_SW_RST 4 327f4fbf79SSean Wang #define MT7622_PERI_BTIF_SW_RST 6 337f4fbf79SSean Wang #define MT7622_PERI_PWM_SW_RST 8 347f4fbf79SSean Wang #define MT7622_PERI_AUXADC_SW_RST 10 357f4fbf79SSean Wang #define MT7622_PERI_DMA_SW_RST 11 367f4fbf79SSean Wang #define MT7622_PERI_IRTX_SW_RST 13 377f4fbf79SSean Wang #define MT7622_PERI_NFI_SW_RST 14 387f4fbf79SSean Wang #define MT7622_PERI_THERM_SW_RST 16 397f4fbf79SSean Wang #define MT7622_PERI_MSDC0_SW_RST 19 407f4fbf79SSean Wang #define MT7622_PERI_MSDC1_SW_RST 20 417f4fbf79SSean Wang #define MT7622_PERI_I2C0_SW_RST 22 427f4fbf79SSean Wang #define MT7622_PERI_I2C1_SW_RST 23 437f4fbf79SSean Wang #define MT7622_PERI_I2C2_SW_RST 24 447f4fbf79SSean Wang #define MT7622_PERI_SPI0_SW_RST 33 457f4fbf79SSean Wang #define MT7622_PERI_SPI1_SW_RST 34 467f4fbf79SSean Wang #define MT7622_PERI_FLASHIF_SW_RST 36 477f4fbf79SSean Wang 487f4fbf79SSean Wang /* TOPRGU resets */ 497f4fbf79SSean Wang #define MT7622_TOPRGU_INFRA_RST 0 507f4fbf79SSean Wang #define MT7622_TOPRGU_ETHDMA_RST 1 517f4fbf79SSean Wang #define MT7622_TOPRGU_DDRPHY_RST 6 527f4fbf79SSean Wang #define MT7622_TOPRGU_INFRA_AO_RST 8 537f4fbf79SSean Wang #define MT7622_TOPRGU_CONN_RST 9 547f4fbf79SSean Wang #define MT7622_TOPRGU_APMIXED_RST 10 557f4fbf79SSean Wang #define MT7622_TOPRGU_CONN_MCU_RST 12 567f4fbf79SSean Wang 577f4fbf79SSean Wang /* PCIe/SATA Subsystem resets */ 587f4fbf79SSean Wang #define MT7622_SATA_PHY_REG_RST 12 597f4fbf79SSean Wang #define MT7622_SATA_PHY_SW_RST 13 607f4fbf79SSean Wang #define MT7622_SATA_AXI_BUS_RST 15 617f4fbf79SSean Wang #define MT7622_PCIE1_CORE_RST 19 627f4fbf79SSean Wang #define MT7622_PCIE1_MMIO_RST 20 637f4fbf79SSean Wang #define MT7622_PCIE1_HRST 21 647f4fbf79SSean Wang #define MT7622_PCIE1_USER_RST 22 657f4fbf79SSean Wang #define MT7622_PCIE1_PIPE_RST 23 667f4fbf79SSean Wang #define MT7622_PCIE0_CORE_RST 27 677f4fbf79SSean Wang #define MT7622_PCIE0_MMIO_RST 28 687f4fbf79SSean Wang #define MT7622_PCIE0_HRST 29 697f4fbf79SSean Wang #define MT7622_PCIE0_USER_RST 30 707f4fbf79SSean Wang #define MT7622_PCIE0_PIPE_RST 31 717f4fbf79SSean Wang 727f4fbf79SSean Wang /* SSUSB Subsystem resets */ 737f4fbf79SSean Wang #define MT7622_SSUSB_PHY_PWR_RST 3 747f4fbf79SSean Wang #define MT7622_SSUSB_MAC_PWR_RST 4 757f4fbf79SSean Wang 767f4fbf79SSean Wang /* ETHSYS Subsystem resets */ 777f4fbf79SSean Wang #define MT7622_ETHSYS_SYS_RST 0 787f4fbf79SSean Wang #define MT7622_ETHSYS_MCM_RST 2 797f4fbf79SSean Wang #define MT7622_ETHSYS_HSDMA_RST 5 807f4fbf79SSean Wang #define MT7622_ETHSYS_FE_RST 6 817f4fbf79SSean Wang #define MT7622_ETHSYS_GMAC_RST 23 827f4fbf79SSean Wang #define MT7622_ETHSYS_EPHY_RST 24 837f4fbf79SSean Wang #define MT7622_ETHSYS_CRYPTO_RST 29 847f4fbf79SSean Wang #define MT7622_ETHSYS_PPE_RST 31 857f4fbf79SSean Wang 867f4fbf79SSean Wang #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7622 */ 87