1*5794dda1SSam Shih /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ 2*5794dda1SSam Shih /* 3*5794dda1SSam Shih * Copyright (c) 2022 MediaTek Inc. 4*5794dda1SSam Shih * Author: Sam Shih <sam.shih@mediatek.com> 5*5794dda1SSam Shih */ 6*5794dda1SSam Shih 7*5794dda1SSam Shih #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7986 8*5794dda1SSam Shih #define _DT_BINDINGS_RESET_CONTROLLER_MT7986 9*5794dda1SSam Shih 10*5794dda1SSam Shih /* INFRACFG resets */ 11*5794dda1SSam Shih #define MT7986_INFRACFG_PEXTP_MAC_SW_RST 6 12*5794dda1SSam Shih #define MT7986_INFRACFG_SSUSB_SW_RST 7 13*5794dda1SSam Shih #define MT7986_INFRACFG_EIP97_SW_RST 8 14*5794dda1SSam Shih #define MT7986_INFRACFG_AUDIO_SW_RST 13 15*5794dda1SSam Shih #define MT7986_INFRACFG_CQ_DMA_SW_RST 14 16*5794dda1SSam Shih 17*5794dda1SSam Shih #define MT7986_INFRACFG_TRNG_SW_RST 17 18*5794dda1SSam Shih #define MT7986_INFRACFG_AP_DMA_SW_RST 32 19*5794dda1SSam Shih #define MT7986_INFRACFG_I2C_SW_RST 33 20*5794dda1SSam Shih #define MT7986_INFRACFG_NFI_SW_RST 34 21*5794dda1SSam Shih #define MT7986_INFRACFG_SPI0_SW_RST 35 22*5794dda1SSam Shih #define MT7986_INFRACFG_SPI1_SW_RST 36 23*5794dda1SSam Shih #define MT7986_INFRACFG_UART0_SW_RST 37 24*5794dda1SSam Shih #define MT7986_INFRACFG_UART1_SW_RST 38 25*5794dda1SSam Shih #define MT7986_INFRACFG_UART2_SW_RST 39 26*5794dda1SSam Shih #define MT7986_INFRACFG_AUXADC_SW_RST 43 27*5794dda1SSam Shih 28*5794dda1SSam Shih #define MT7986_INFRACFG_APXGPT_SW_RST 66 29*5794dda1SSam Shih #define MT7986_INFRACFG_PWM_SW_RST 68 30*5794dda1SSam Shih 31*5794dda1SSam Shih #define MT7986_INFRACFG_SW_RST_NUM 69 32*5794dda1SSam Shih 33*5794dda1SSam Shih /* TOPRGU resets */ 34*5794dda1SSam Shih #define MT7986_TOPRGU_APMIXEDSYS_SW_RST 0 35*5794dda1SSam Shih #define MT7986_TOPRGU_SGMII0_SW_RST 1 36*5794dda1SSam Shih #define MT7986_TOPRGU_SGMII1_SW_RST 2 37*5794dda1SSam Shih #define MT7986_TOPRGU_INFRA_SW_RST 3 38*5794dda1SSam Shih #define MT7986_TOPRGU_U2PHY_SW_RST 5 39*5794dda1SSam Shih #define MT7986_TOPRGU_PCIE_SW_RST 6 40*5794dda1SSam Shih #define MT7986_TOPRGU_SSUSB_SW_RST 7 41*5794dda1SSam Shih #define MT7986_TOPRGU_ETHDMA_SW_RST 20 42*5794dda1SSam Shih #define MT7986_TOPRGU_CONSYS_SW_RST 23 43*5794dda1SSam Shih 44*5794dda1SSam Shih #define MT7986_TOPRGU_SW_RST_NUM 24 45*5794dda1SSam Shih 46*5794dda1SSam Shih /* ETHSYS Subsystem resets */ 47*5794dda1SSam Shih #define MT7986_ETHSYS_FE_SW_RST 6 48*5794dda1SSam Shih #define MT7986_ETHSYS_PMTR_SW_RST 8 49*5794dda1SSam Shih #define MT7986_ETHSYS_GMAC_SW_RST 23 50*5794dda1SSam Shih #define MT7986_ETHSYS_PPE0_SW_RST 30 51*5794dda1SSam Shih #define MT7986_ETHSYS_PPE1_SW_RST 31 52*5794dda1SSam Shih 53*5794dda1SSam Shih #define MT7986_ETHSYS_SW_RST_NUM 32 54*5794dda1SSam Shih 55*5794dda1SSam Shih #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7986 */ 56