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/openbmc/u-boot/board/technexion/tao3530/
H A Dtao3530.c1 // SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch/gpio.h>
15 #include <asm/gpio.h>
16 #include <asm/mach-types.h>
19 #include <asm/ehci-omap.h>
32 puts("Error: GPIO 65 not available\n"); in tao3530_revision()
35 MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)); in tao3530_revision()
39 puts("Error: GPIO 1 not available\n"); in tao3530_revision()
42 MUX_VAL(CP(SYS_CLKREQ), (IEN | PTU | EN | M4)); in tao3530_revision()
46 puts("Error: GPIO 65 not available for input\n"); in tao3530_revision()
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dmeson-gxbb-odroidc2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "meson-gxbb.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
14 compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb";
15 model = "Hardkernel ODROID-C2";
23 stdout-path = "serial0:115200n8";
31 usb_otg_pwr: regulator-usb-pwrs {
32 compatible = "regulator-fixed";
34 regulator-name = "USB_OTG_PWR";
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H A Drk3288-veyron-speedy.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
9 #include "rk3288-veyron-chromebook.dtsi"
10 #include "cros-ec-sbs.dtsi"
11 #include "rk3288-veyron-speedy-u-boot.dtsi"
15 compatible = "google,veyron-speedy-rev9", "google,veyron-speedy-rev8",
16 "google,veyron-speedy-rev7", "google,veyron-speedy-rev6",
17 "google,veyron-speedy-rev5", "google,veyron-speedy-rev4",
18 "google,veyron-speedy-rev3", "google,veyron-speedy-rev2",
19 "google,veyron-speedy", "google,veyron", "rockchip,rk3288";
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H A Drk3399-gru-chromebook.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Google Gru-Chromebook shared properties
8 #include "rk3399-gru.dtsi"
11 pp900_ap: pp900-ap {
12 compatible = "regulator-fixed";
13 regulator-name = "pp900_ap";
16 regulator-always-on;
17 regulator-boot-on;
18 regulator-min-microvolt = <900000>;
19 regulator-max-microvolt = <900000>;
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H A Drk3288-veyron-jerry.dts1 // SPDX-License-Identifier: GPL-2.0
8 /dts-v1/;
9 #include "rk3288-veyron-chromebook.dtsi"
10 #include "cros-ec-sbs.dtsi"
14 compatible = "google,veyron-jerry-rev7", "google,veyron-jerry-rev6",
15 "google,veyron-jerry-rev5", "google,veyron-jerry-rev4",
16 "google,veyron-jerry-rev3", "google,veyron-jerry",
20 stdout-path = &uart2;
23 panel_regulator: panel-regulator {
24 compatible = "regulator-fixed";
[all …]
H A Drk3399-evb.dts1 // SPDX-License-Identifier: GPL-2.0+
6 /dts-v1/;
7 #include <dt-bindings/pwm/pwm.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
10 #include "rk3399-sdram-lpddr3-4GB-1600.dtsi"
14 compatible = "rockchip,rk3399-evb", "rockchip,rk3399",
15 "google,rk3399evb-rev2";
18 stdout-path = &uart2;
19 u-boot,spl-boot-order = \
23 vdd_center: vdd-center {
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H A Drk3288-veyron-minnie.dts6 * This file is dual-licensed: you can use it either under the terms
45 /dts-v1/;
46 #include "rk3288-veyron-chromebook.dtsi"
50 compatible = "google,veyron-minnie-rev4", "google,veyron-minnie-rev3",
51 "google,veyron-minnie-rev2", "google,veyron-minnie-rev1",
52 "google,veyron-minnie-rev0", "google,veyron-minnie",
55 backlight_regulator: backlight-regulator {
56 compatible = "regulator-fixed";
57 enable-active-high;
58 gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>;
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H A Dmeson-gxbb-nanopi-k2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "meson-gxbb.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
12 compatible = "friendlyarm,nanopi-k2", "amlogic,meson-gxbb";
20 stdout-path = "serial0:115200n8";
29 compatible = "gpio-leds";
32 label = "nanopi-k2:blue:stat";
34 default-state = "on";
35 panic-indicator;
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H A Dtegra20-ventana.dts1 /dts-v1/;
3 #include <dt-bindings/input/input.h>
11 stdout-path = &uartd;
38 display-timings {
41 clock-frequency = <70600000>;
44 hback-porch = <58>;
45 hfront-porch = <58>;
46 hsync-len = <58>;
47 vback-porch = <4>;
48 vfront-porch = <4>;
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H A Dtegra20-harmony.dts1 /dts-v1/;
3 #include <dt-bindings/input/input.h>
11 stdout-path = &uartd;
38 display-timings {
41 clock-frequency = <42430000>;
44 hback-porch = <138>;
45 hfront-porch = <34>;
46 hsync-len = <136>;
47 vback-porch = <21>;
48 vfront-porch = <4>;
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H A Drk3288-veyron-chromebook.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/rockchip,rk808.h>
9 #include <dt-bindings/input/input.h>
10 #include "rk3288-veyron.dtsi"
19 gpio_keys: gpio-keys {
20 pinctrl-0 = <&pwr_key_h &ap_lid_int_l>;
25 linux,input-type = <5>; /* EV_SW */
26 debounce-interval = <1>;
27 gpio-key,wakeup;
31 gpio-charger {
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/openbmc/openbmc/meta-facebook/meta-yosemite4/recipes-phosphor/gpio/phosphor-gpio-monitor/
H A Den-i3c-hub-scan-fru@.service2 Description=slot-en-i3c-hub-scan-fru:%i
6 ExecStart=/usr/libexec/phosphor-gpio-monitor/en-i3c-hub-scan-fru %i
7 SyslogIdentifier=slot-en-i3c-hub-scan-fru %i
/openbmc/openbmc/meta-facebook/meta-yosemite4/recipes-phosphor/gpio/
H A Dphosphor-gpio-monitor_%.bbappend3 inherit obmc-phosphor-systemd systemd
5 SRC_URI += "file://yosemite4-phosphor-multi-gpio-monitor.json \
6 file://configure-nic-mctp-endpoint \
7 file://setup-nic-endpoint-slot@.service \
8 file://remove-nic-endpoint-slot@.service \
9 file://set-button-sled.service \
10 file://probe-slot-device@.service \
11 file://probe-slot-device \
12 file://reconfig-net-interface@.service \
13 file://reconfig-net-interface \
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/openbmc/u-boot/board/compulab/cm_t35/
H A Dcm_t35.c1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2011 - 2013 CompuLab, Ltd. <www.compulab.co.il>
10 * Richard Woodruff <r-woodruff2@ti.com>
32 #include <asm/mach-types.h>
33 #include <asm/ehci-omap.h>
34 #include <asm/gpio.h>
43 "CM-T3x board",
50 * Description: If we use SPL then there is no x-loader nor config header
55 timings->mr = MICRON_V_MR_165; in get_board_mem_timings()
56 timings->mcfg = MICRON_V_MCFG_200(256 << 20); /* raswidth 14 needed */ in get_board_mem_timings()
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/openbmc/qemu/hw/arm/
H A Db-l475e-iot01a.c2 * B-L475E-IOT01A Discovery Kit machine
3 * (B-L475E-IOT01A IoT Node)
5 * Copyright (c) 2023-2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
6 * Copyright (c) 2023-2024 Inès Varhol <ines.varhol@telecom-paris.fr>
8 * SPDX-License-Identifier: GPL-2.0-or-later
11 * See the COPYING file in the top-level directory.
21 * Discovery kit for IoT node, multi-channel communication with STM32L4.
22 * https://www.st.com/en/evaluation-tools/b-l475e-iot01a.html#documentation
28 #include "hw/qdev-properties.h"
29 #include "qemu/error-report.h"
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/openbmc/qemu/include/hw/gpio/
H A Dstm32l4x5_gpio.h2 * STM32L4x5 GPIO (General Purpose Input/Ouput)
4 * Copyright (c) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
5 * Copyright (c) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
7 * SPDX-License-Identifier: GPL-2.0-or-later
10 * See the COPYING file in the top-level directory.
15 * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
16 * https://www.st.com/en/microcontrollers-microprocessors/stm32l4x5/documentation.html
25 #define TYPE_STM32L4X5_GPIO "stm32l4x5-gpio"
36 /* GPIO registers */
48 /* GPIO registers reset values */
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/openbmc/u-boot/board/teejet/mt_ventoux/
H A Dmt_ventoux.h1 /* SPDX-License-Identifier: GPL-2.0+ */
30 * IEN - Input Enable
31 * IDIS - Input Disable
32 * PTD - Pull type Down
33 * PTU - Pull type Up
34 * DIS - Pull type selection is inactive
35 * EN - Pull type selection is active
36 * M0 - Mode 0
78 MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0)) \
79 MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0)) \
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/openbmc/u-boot/drivers/gpio/
H A Ds5p_gpio.c1 // SPDX-License-Identifier: GPL-2.0+
13 #include <asm/gpio.h>
14 #include <dm/device-internal.h>
21 #define CON_SFR(gpio, cfg) ((cfg) << ((gpio) << 2)) argument
22 #define CON_SFR_UNSHIFT(val, gpio) ((val) >> ((gpio) << 2)) argument
24 #define DAT_MASK(gpio) (0x1 << (gpio)) argument
25 #define DAT_SET(gpio) (0x1 << (gpio)) argument
27 #define PULL_MASK(gpio) (0x3 << ((gpio) << 1)) argument
28 #define PULL_MODE(gpio, pull) ((pull) << ((gpio) << 1)) argument
30 #define DRV_MASK(gpio) (0x3 << ((gpio) << 1)) argument
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/openbmc/u-boot/doc/device-tree-bindings/net/
H A Dsnps,dwc-qos-ethernet.txt10 - compatible: One of:
11 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
12 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
13 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
15 - "snps,dwc-qos-ethernet-4.10"
17 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
19 - reg: Address and length of the register set for the device
20 - clocks: Phandle and clock specifiers for each entry in clock-names, in the
21 same order. See ../clock/clock-bindings.txt.
22 - clock-names: May contain any/all of the following depending on the IP
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/openbmc/u-boot/board/keymile/kmp204x/
H A Dqrio.c1 // SPDX-License-Identifier: GPL-2.0+
12 /* QRIO GPIO register offsets */
82 /* set to output -> GPIO drives low */ in qrio_set_opendrain_gpio()
85 /* set to input -> GPIO floating */ in qrio_set_opendrain_gpio()
110 void qrio_prst(u8 bit, bool en, bool wden) in qrio_prst() argument
119 if (en) in qrio_prst()
H A Dkmp204x.h1 /* SPDX-License-Identifier: GPL-2.0+ */
7 /* QRIO GPIO ports */
21 void qrio_prst(u8 bit, bool en, bool wden);
/openbmc/u-boot/board/compulab/cm_t3517/
H A Dmux.c1 // SPDX-License-Identifier: GPL-2.0+
53 MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); in set_muxconf_regs()
57 MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); in set_muxconf_regs()
58 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); in set_muxconf_regs()
59 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); in set_muxconf_regs()
60 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); in set_muxconf_regs()
61 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); in set_muxconf_regs()
62 MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); in set_muxconf_regs()
63 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); in set_muxconf_regs()
64 MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); in set_muxconf_regs()
[all …]
/openbmc/u-boot/board/logicpd/zoom1/
H A Dzoom1.h1 /* SPDX-License-Identifier: GPL-2.0+ */
27 * IEN - Input Enable
28 * IDIS - Input Disable
29 * PTD - Pull type Down
30 * PTU - Pull type Up
31 * DIS - Pull type selection is inactive
32 * EN - Pull type selection is active
33 * M0 - Mode 0
102 MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
103 MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
[all …]
/openbmc/qemu/include/hw/misc/
H A Dxlnx-versal-pmc-iou-slcr.h34 * https://www.xilinx.com/support/documentation/architecture-manuals/am011-versal-acap-trm.pdf
37 * https://docs.xilinx.com/r/en-US/am012-versal-register-reference/PMC_IOP_SLCR-Module
44 * + Named GPIO output "sd-emmc-sel[0]": Enables 0: SD mode or 1: eMMC mode on
46 * + Named GPIO output "sd-emmc-sel[1]": Enables 0: SD mode or 1: eMMC mode on
48 * + Named GPIO output "qspi-ospi-mux-sel": Selects 0: QSPI linear region or 1:
50 * + Named GPIO output "ospi-mux-sel": Selects 0: OSPI Indirect access mode or
60 #define TYPE_XILINX_VERSAL_PMC_IOU_SLCR "xlnx.versal-pmc-iou-slcr"
/openbmc/qemu/include/hw/arm/
H A Dstm32l4x5_soc.h4 * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
5 * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
7 * SPDX-License-Identifier: GPL-2.0-or-later
10 * See the COPYING file in the top-level directory.
20 * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
21 * https://www.st.com/en/microcontrollers-microprocessors/stm32l4x5/documentation.html
29 #include "hw/or-irq.h"
33 #include "hw/gpio/stm32l4x5_gpio.h"
37 #define TYPE_STM32L4X5_SOC "stm32l4x5-soc"
38 #define TYPE_STM32L4X5XC_SOC "stm32l4x5xc-soc"
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