Lines Matching +full:en +full:- +full:gpio
1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2011 - 2013 CompuLab, Ltd. <www.compulab.co.il>
10 * Richard Woodruff <r-woodruff2@ti.com>
32 #include <asm/mach-types.h>
33 #include <asm/ehci-omap.h>
34 #include <asm/gpio.h>
43 "CM-T3x board",
50 * Description: If we use SPL then there is no x-loader nor config header
55 timings->mr = MICRON_V_MR_165; in get_board_mem_timings()
56 timings->mcfg = MICRON_V_MCFG_200(256 << 20); /* raswidth 14 needed */ in get_board_mem_timings()
57 timings->ctrla = MICRON_V_ACTIMA_165; in get_board_mem_timings()
58 timings->ctrlb = MICRON_V_ACTIMB_165; in get_board_mem_timings()
59 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; in get_board_mem_timings()
88 gd->bd->bi_arch_number = MACH_TYPE_CM_T35; in board_init()
90 gd->bd->bi_arch_number = MACH_TYPE_CM_T3730; in board_init()
93 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); in board_init()
165 MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); /*SDRC_CKE0*/ in cm_t3x_set_common_muxconf()
169 MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); /*GPMC_A1*/ in cm_t3x_set_common_muxconf()
170 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); /*GPMC_A2*/ in cm_t3x_set_common_muxconf()
171 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); /*GPMC_A3*/ in cm_t3x_set_common_muxconf()
172 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); /*GPMC_A4*/ in cm_t3x_set_common_muxconf()
173 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); /*GPMC_A5*/ in cm_t3x_set_common_muxconf()
174 MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); /*GPMC_A6*/ in cm_t3x_set_common_muxconf()
175 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); /*GPMC_A7*/ in cm_t3x_set_common_muxconf()
176 MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); /*GPMC_A8*/ in cm_t3x_set_common_muxconf()
177 MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); /*GPMC_A9*/ in cm_t3x_set_common_muxconf()
178 MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)); /*GPMC_A10*/ in cm_t3x_set_common_muxconf()
179 MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); /*GPMC_D0*/ in cm_t3x_set_common_muxconf()
180 MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)); /*GPMC_D1*/ in cm_t3x_set_common_muxconf()
181 MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)); /*GPMC_D2*/ in cm_t3x_set_common_muxconf()
182 MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)); /*GPMC_D3*/ in cm_t3x_set_common_muxconf()
183 MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)); /*GPMC_D4*/ in cm_t3x_set_common_muxconf()
184 MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)); /*GPMC_D5*/ in cm_t3x_set_common_muxconf()
185 MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)); /*GPMC_D6*/ in cm_t3x_set_common_muxconf()
186 MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)); /*GPMC_D7*/ in cm_t3x_set_common_muxconf()
187 MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)); /*GPMC_D8*/ in cm_t3x_set_common_muxconf()
188 MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)); /*GPMC_D9*/ in cm_t3x_set_common_muxconf()
189 MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)); /*GPMC_D10*/ in cm_t3x_set_common_muxconf()
190 MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)); /*GPMC_D11*/ in cm_t3x_set_common_muxconf()
191 MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)); /*GPMC_D12*/ in cm_t3x_set_common_muxconf()
192 MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)); /*GPMC_D13*/ in cm_t3x_set_common_muxconf()
193 MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)); /*GPMC_D14*/ in cm_t3x_set_common_muxconf()
194 MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)); /*GPMC_D15*/ in cm_t3x_set_common_muxconf()
195 MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); /*GPMC_nCS0*/ in cm_t3x_set_common_muxconf()
197 /* SB-T35 Ethernet */ in cm_t3x_set_common_muxconf()
198 MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)); /*GPMC_nCS4*/ in cm_t3x_set_common_muxconf()
206 /* CM-T3x Ethernet */ in cm_t3x_set_common_muxconf()
212 MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)); /*nBE0_CLE*/ in cm_t3x_set_common_muxconf()
215 MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); /*WAIT0*/ in cm_t3x_set_common_muxconf()
241 MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)); /*HSUSB0_STP*/ in cm_t3x_set_common_muxconf()
254 MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT0*/ in cm_t3x_set_common_muxconf()
255 MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT1*/ in cm_t3x_set_common_muxconf()
256 MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT2*/ in cm_t3x_set_common_muxconf()
257 MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT3*/ in cm_t3x_set_common_muxconf()
258 MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT4*/ in cm_t3x_set_common_muxconf()
259 MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT5*/ in cm_t3x_set_common_muxconf()
260 MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT6*/ in cm_t3x_set_common_muxconf()
261 MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT7*/ in cm_t3x_set_common_muxconf()
262 MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DIR*/ in cm_t3x_set_common_muxconf()
263 MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_NXT*/ in cm_t3x_set_common_muxconf()
267 MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT0*/ in cm_t3x_set_common_muxconf()
268 MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT1*/ in cm_t3x_set_common_muxconf()
269 MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M3)); /*HSUSB2_DT2*/ in cm_t3x_set_common_muxconf()
270 MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M3)); /*HSUSB2_DT3*/ in cm_t3x_set_common_muxconf()
271 MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | EN | M3)); /*HSUSB2_DT4*/ in cm_t3x_set_common_muxconf()
272 MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | EN | M3)); /*HSUSB2_DT5*/ in cm_t3x_set_common_muxconf()
273 MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M3)); /*HSUSB2_DT6*/ in cm_t3x_set_common_muxconf()
274 MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M3)); /*HSUSB2_DT7*/ in cm_t3x_set_common_muxconf()
275 MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DIR*/ in cm_t3x_set_common_muxconf()
276 MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_NXT*/ in cm_t3x_set_common_muxconf()
284 MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)); /*I2C1_SCL*/ in cm_t3x_set_common_muxconf()
285 MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)); /*I2C1_SDA*/ in cm_t3x_set_common_muxconf()
287 MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)); /*I2C2_SCL*/ in cm_t3x_set_common_muxconf()
288 MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)); /*I2C2_SDA*/ in cm_t3x_set_common_muxconf()
290 MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)); /*I2C3_SCL*/ in cm_t3x_set_common_muxconf()
291 MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)); /*I2C3_SDA*/ in cm_t3x_set_common_muxconf()
296 MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)); /*SYS_nIRQ*/ in cm_t3x_set_common_muxconf()
306 MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)); /*MMC1_CLK*/ in cm_t3x_set_common_muxconf()
307 MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)); /*MMC1_CMD*/ in cm_t3x_set_common_muxconf()
308 MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)); /*MMC1_DAT0*/ in cm_t3x_set_common_muxconf()
309 MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); /*MMC1_DAT1*/ in cm_t3x_set_common_muxconf()
310 MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); /*MMC1_DAT2*/ in cm_t3x_set_common_muxconf()
311 MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); /*MMC1_DAT3*/ in cm_t3x_set_common_muxconf()
317 MUX_VAL(CP(MCBSP1_FSX), (IEN | PTU | EN | M1)); /*MCSPI4_CS0*/ in cm_t3x_set_common_muxconf()
341 MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)); /*MMC1_DAT4*/ in cm_t35_set_muxconf()
342 MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)); /*MMC1_DAT5*/ in cm_t35_set_muxconf()
343 MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)); /*MMC1_DAT6*/ in cm_t35_set_muxconf()
344 MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)); /*MMC1_DAT7*/ in cm_t35_set_muxconf()
383 return -1; in board_mmc_getcd()
390 return omap_mmc_init(0, 0, 0, -1, SB_T35_WP_GPIO); in board_mmc_init()
404 * Description: reset the Ethernet controller via TPS65930 GPIO
406 static int cm_t3x_reset_net_chip(int gpio) in cm_t3x_reset_net_chip() argument
411 /* Send a pulse on the GPIO pin */ in cm_t3x_reset_net_chip()
424 static inline int cm_t3x_reset_net_chip(int gpio) { return 0; } in cm_t3x_reset_net_chip() argument
430 * Description: prepare MAC address for on-board Ethernet.
446 return -1; in handle_mac_address()
453 * Description: initialize module and base-board Ethernet chips
465 cm_t3x_reset_net_chip, -EINVAL); in board_eth_init()
469 rc1 = cl_omap3_smc911x_init(1, 4, SB_T35_SMC911X_BASE, NULL, -EINVAL); in board_eth_init()
491 cl_usb_hub_init(SB_T35_USB_HUB_RESET_GPIO, "sb-t35 hub rst"); in ehci_hcd_init()