xref: /openbmc/qemu/include/hw/gpio/stm32l4x5_gpio.h (revision 1c38129d)
1 /*
2  * STM32L4x5 GPIO (General Purpose Input/Ouput)
3  *
4  * Copyright (c) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
5  * Copyright (c) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * This work is licensed under the terms of the GNU GPL, version 2 or later.
10  * See the COPYING file in the top-level directory.
11  */
12 
13 /*
14  * The reference used is the STMicroElectronics RM0351 Reference manual
15  * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
16  * https://www.st.com/en/microcontrollers-microprocessors/stm32l4x5/documentation.html
17  */
18 
19 #ifndef HW_STM32L4X5_GPIO_H
20 #define HW_STM32L4X5_GPIO_H
21 
22 #include "hw/sysbus.h"
23 #include "qom/object.h"
24 
25 #define TYPE_STM32L4X5_GPIO "stm32l4x5-gpio"
26 OBJECT_DECLARE_SIMPLE_TYPE(Stm32l4x5GpioState, STM32L4X5_GPIO)
27 
28 #define NUM_GPIOS 8
29 #define GPIO_NUM_PINS 16
30 
31 struct Stm32l4x5GpioState {
32     SysBusDevice parent_obj;
33 
34     MemoryRegion mmio;
35 
36     /* GPIO registers */
37     uint32_t moder;
38     uint32_t otyper;
39     uint32_t ospeedr;
40     uint32_t pupdr;
41     uint32_t idr;
42     uint32_t odr;
43     uint32_t lckr;
44     uint32_t afrl;
45     uint32_t afrh;
46     uint32_t ascr;
47 
48     /* GPIO registers reset values */
49     uint32_t moder_reset;
50     uint32_t ospeedr_reset;
51     uint32_t pupdr_reset;
52 
53     /*
54      * External driving of pins.
55      * The pins can be set externally through the device
56      * anonymous input GPIOs lines under certain conditions.
57      * The pin must not be in push-pull output mode,
58      * and can't be set high in open-drain mode.
59      * Pins driven externally and configured to
60      * output mode will in general be "disconnected"
61      * (see `get_gpio_pinmask_to_disconnect()`)
62      */
63     uint16_t disconnected_pins;
64     uint16_t pins_connected_high;
65 
66     char *name;
67     Clock *clk;
68     qemu_irq pin[GPIO_NUM_PINS];
69 };
70 
71 #endif
72