1*8e2e601cSMarty E. Plummer// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*8e2e601cSMarty E. Plummer/* 3*8e2e601cSMarty E. Plummer * Google Veyron Speedy Rev 1+ board device tree source 4*8e2e601cSMarty E. Plummer * 5*8e2e601cSMarty E. Plummer * Copyright 2015 Google, Inc 6*8e2e601cSMarty E. Plummer */ 7*8e2e601cSMarty E. Plummer 8*8e2e601cSMarty E. Plummer/dts-v1/; 9*8e2e601cSMarty E. Plummer#include "rk3288-veyron-chromebook.dtsi" 10*8e2e601cSMarty E. Plummer#include "cros-ec-sbs.dtsi" 11*8e2e601cSMarty E. Plummer#include "rk3288-veyron-speedy-u-boot.dtsi" 12*8e2e601cSMarty E. Plummer 13*8e2e601cSMarty E. Plummer/ { 14*8e2e601cSMarty E. Plummer model = "Google Speedy"; 15*8e2e601cSMarty E. Plummer compatible = "google,veyron-speedy-rev9", "google,veyron-speedy-rev8", 16*8e2e601cSMarty E. Plummer "google,veyron-speedy-rev7", "google,veyron-speedy-rev6", 17*8e2e601cSMarty E. Plummer "google,veyron-speedy-rev5", "google,veyron-speedy-rev4", 18*8e2e601cSMarty E. Plummer "google,veyron-speedy-rev3", "google,veyron-speedy-rev2", 19*8e2e601cSMarty E. Plummer "google,veyron-speedy", "google,veyron", "rockchip,rk3288"; 20*8e2e601cSMarty E. Plummer 21*8e2e601cSMarty E. Plummer panel_regulator: panel-regulator { 22*8e2e601cSMarty E. Plummer compatible = "regulator-fixed"; 23*8e2e601cSMarty E. Plummer enable-active-high; 24*8e2e601cSMarty E. Plummer gpio = <&gpio7 RK_PB6 GPIO_ACTIVE_HIGH>; 25*8e2e601cSMarty E. Plummer pinctrl-names = "default"; 26*8e2e601cSMarty E. Plummer pinctrl-0 = <&lcd_enable_h>; 27*8e2e601cSMarty E. Plummer regulator-name = "panel_regulator"; 28*8e2e601cSMarty E. Plummer startup-delay-us = <100000>; 29*8e2e601cSMarty E. Plummer vin-supply = <&vcc33_sys>; 30*8e2e601cSMarty E. Plummer }; 31*8e2e601cSMarty E. Plummer 32*8e2e601cSMarty E. Plummer vcc18_lcd: vcc18-lcd { 33*8e2e601cSMarty E. Plummer compatible = "regulator-fixed"; 34*8e2e601cSMarty E. Plummer enable-active-high; 35*8e2e601cSMarty E. Plummer gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>; 36*8e2e601cSMarty E. Plummer pinctrl-names = "default"; 37*8e2e601cSMarty E. Plummer pinctrl-0 = <&avdd_1v8_disp_en>; 38*8e2e601cSMarty E. Plummer regulator-name = "vcc18_lcd"; 39*8e2e601cSMarty E. Plummer regulator-always-on; 40*8e2e601cSMarty E. Plummer regulator-boot-on; 41*8e2e601cSMarty E. Plummer vin-supply = <&vcc18_wl>; 42*8e2e601cSMarty E. Plummer }; 43*8e2e601cSMarty E. Plummer 44*8e2e601cSMarty E. Plummer backlight_regulator: backlight-regulator { 45*8e2e601cSMarty E. Plummer compatible = "regulator-fixed"; 46*8e2e601cSMarty E. Plummer enable-active-high; 47*8e2e601cSMarty E. Plummer gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>; 48*8e2e601cSMarty E. Plummer pinctrl-names = "default"; 49*8e2e601cSMarty E. Plummer pinctrl-0 = <&bl_pwr_en>; 50*8e2e601cSMarty E. Plummer regulator-name = "backlight_regulator"; 51*8e2e601cSMarty E. Plummer vin-supply = <&vcc33_sys>; 52*8e2e601cSMarty E. Plummer startup-delay-us = <15000>; 53*8e2e601cSMarty E. Plummer }; 54*8e2e601cSMarty E. Plummer}; 55*8e2e601cSMarty E. Plummer 56*8e2e601cSMarty E. Plummer&backlight { 57*8e2e601cSMarty E. Plummer power-supply = <&backlight_regulator>; 58*8e2e601cSMarty E. Plummer}; 59*8e2e601cSMarty E. Plummer 60*8e2e601cSMarty E. Plummer&cpu_alert0 { 61*8e2e601cSMarty E. Plummer temperature = <65000>; 62*8e2e601cSMarty E. Plummer}; 63*8e2e601cSMarty E. Plummer 64*8e2e601cSMarty E. Plummer&cpu_alert1 { 65*8e2e601cSMarty E. Plummer temperature = <70000>; 66*8e2e601cSMarty E. Plummer}; 67*8e2e601cSMarty E. Plummer 68*8e2e601cSMarty E. Plummer&edp { 69*8e2e601cSMarty E. Plummer /delete-property/pinctrl-names; 70*8e2e601cSMarty E. Plummer /delete-property/pinctrl-0; 71*8e2e601cSMarty E. Plummer 72*8e2e601cSMarty E. Plummer force-hpd; 73*8e2e601cSMarty E. Plummer}; 74*8e2e601cSMarty E. Plummer 75*8e2e601cSMarty E. Plummer&panel { 76*8e2e601cSMarty E. Plummer power-supply = <&panel_regulator>; 77*8e2e601cSMarty E. Plummer}; 78*8e2e601cSMarty E. Plummer 79*8e2e601cSMarty E. Plummer&rk808 { 80*8e2e601cSMarty E. Plummer pinctrl-names = "default"; 81*8e2e601cSMarty E. Plummer pinctrl-0 = <&pmic_int_l>; 82*8e2e601cSMarty E. Plummer}; 83*8e2e601cSMarty E. Plummer 84*8e2e601cSMarty E. Plummer&sdmmc { 85*8e2e601cSMarty E. Plummer disable-wp; 86*8e2e601cSMarty E. Plummer pinctrl-names = "default"; 87*8e2e601cSMarty E. Plummer pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio 88*8e2e601cSMarty E. Plummer &sdmmc_bus4>; 89*8e2e601cSMarty E. Plummer}; 90*8e2e601cSMarty E. Plummer 91*8e2e601cSMarty E. Plummer&vcc_5v { 92*8e2e601cSMarty E. Plummer enable-active-high; 93*8e2e601cSMarty E. Plummer gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>; 94*8e2e601cSMarty E. Plummer pinctrl-names = "default"; 95*8e2e601cSMarty E. Plummer pinctrl-0 = <&drv_5v>; 96*8e2e601cSMarty E. Plummer}; 97*8e2e601cSMarty E. Plummer 98*8e2e601cSMarty E. Plummer&vcc50_hdmi { 99*8e2e601cSMarty E. Plummer enable-active-high; 100*8e2e601cSMarty E. Plummer gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>; 101*8e2e601cSMarty E. Plummer pinctrl-names = "default"; 102*8e2e601cSMarty E. Plummer pinctrl-0 = <&vcc50_hdmi_en>; 103*8e2e601cSMarty E. Plummer}; 104*8e2e601cSMarty E. Plummer 105*8e2e601cSMarty E. Plummer&pinctrl { 106*8e2e601cSMarty E. Plummer backlight { 107*8e2e601cSMarty E. Plummer bl_pwr_en: bl_pwr_en { 108*8e2e601cSMarty E. Plummer rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>; 109*8e2e601cSMarty E. Plummer }; 110*8e2e601cSMarty E. Plummer }; 111*8e2e601cSMarty E. Plummer 112*8e2e601cSMarty E. Plummer buck-5v { 113*8e2e601cSMarty E. Plummer drv_5v: drv-5v { 114*8e2e601cSMarty E. Plummer rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>; 115*8e2e601cSMarty E. Plummer }; 116*8e2e601cSMarty E. Plummer }; 117*8e2e601cSMarty E. Plummer 118*8e2e601cSMarty E. Plummer hdmi { 119*8e2e601cSMarty E. Plummer vcc50_hdmi_en: vcc50-hdmi-en { 120*8e2e601cSMarty E. Plummer rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>; 121*8e2e601cSMarty E. Plummer }; 122*8e2e601cSMarty E. Plummer }; 123*8e2e601cSMarty E. Plummer 124*8e2e601cSMarty E. Plummer lcd { 125*8e2e601cSMarty E. Plummer lcd_enable_h: lcd-en { 126*8e2e601cSMarty E. Plummer rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>; 127*8e2e601cSMarty E. Plummer }; 128*8e2e601cSMarty E. Plummer 129*8e2e601cSMarty E. Plummer avdd_1v8_disp_en: avdd-1v8-disp-en { 130*8e2e601cSMarty E. Plummer rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>; 131*8e2e601cSMarty E. Plummer }; 132*8e2e601cSMarty E. Plummer }; 133*8e2e601cSMarty E. Plummer 134*8e2e601cSMarty E. Plummer pmic { 135*8e2e601cSMarty E. Plummer dvs_1: dvs-1 { 136*8e2e601cSMarty E. Plummer rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>; 137*8e2e601cSMarty E. Plummer }; 138*8e2e601cSMarty E. Plummer 139*8e2e601cSMarty E. Plummer dvs_2: dvs-2 { 140*8e2e601cSMarty E. Plummer rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>; 141*8e2e601cSMarty E. Plummer }; 142*8e2e601cSMarty E. Plummer }; 143*8e2e601cSMarty E. Plummer}; 144