Lines Matching +full:en +full:- +full:gpio
1 // SPDX-License-Identifier: GPL-2.0+
13 #include <asm/gpio.h>
14 #include <dm/device-internal.h>
21 #define CON_SFR(gpio, cfg) ((cfg) << ((gpio) << 2)) argument
22 #define CON_SFR_UNSHIFT(val, gpio) ((val) >> ((gpio) << 2)) argument
24 #define DAT_MASK(gpio) (0x1 << (gpio)) argument
25 #define DAT_SET(gpio) (0x1 << (gpio)) argument
27 #define PULL_MASK(gpio) (0x3 << ((gpio) << 1)) argument
28 #define PULL_MODE(gpio, pull) ((pull) << ((gpio) << 1)) argument
30 #define DRV_MASK(gpio) (0x3 << ((gpio) << 1)) argument
31 #define DRV_SET(gpio, mode) ((mode) << ((gpio) << 1)) argument
32 #define RATE_MASK(gpio) (0x1 << (gpio + 16)) argument
33 #define RATE_SET(gpio) (0x1 << (gpio + 16)) argument
41 /* Information about each bank at run-time */
46 static struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned int gpio) in s5p_gpio_get_bank() argument
58 if (gpio < data->max_gpio) { in s5p_gpio_get_bank()
60 bank = (struct s5p_gpio_bank *)data->reg_addr; in s5p_gpio_get_bank()
61 bank += (gpio - upto) / GPIO_PER_BANK; in s5p_gpio_get_bank()
62 debug("gpio=%d, bank=%p\n", gpio, bank); in s5p_gpio_get_bank()
66 upto = data->max_gpio; in s5p_gpio_get_bank()
73 static void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg) in s5p_gpio_cfg_pin() argument
77 value = readl(&bank->con); in s5p_gpio_cfg_pin()
78 value &= ~CON_MASK(gpio); in s5p_gpio_cfg_pin()
79 value |= CON_SFR(gpio, cfg); in s5p_gpio_cfg_pin()
80 writel(value, &bank->con); in s5p_gpio_cfg_pin()
83 static void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en) in s5p_gpio_set_value() argument
87 value = readl(&bank->dat); in s5p_gpio_set_value()
88 value &= ~DAT_MASK(gpio); in s5p_gpio_set_value()
89 if (en) in s5p_gpio_set_value()
90 value |= DAT_SET(gpio); in s5p_gpio_set_value()
91 writel(value, &bank->dat); in s5p_gpio_set_value()
95 /* Common GPIO API - SPL does not support driver model yet */
96 int gpio_set_value(unsigned gpio, int value) in gpio_set_value() argument
98 s5p_gpio_set_value(s5p_gpio_get_bank(gpio), in gpio_set_value()
99 s5p_gpio_get_pin(gpio), value); in gpio_set_value()
104 static int s5p_gpio_get_cfg_pin(struct s5p_gpio_bank *bank, int gpio) in s5p_gpio_get_cfg_pin() argument
108 value = readl(&bank->con); in s5p_gpio_get_cfg_pin()
109 value &= CON_MASK(gpio); in s5p_gpio_get_cfg_pin()
110 return CON_SFR_UNSHIFT(value, gpio); in s5p_gpio_get_cfg_pin()
113 static unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio) in s5p_gpio_get_value() argument
117 value = readl(&bank->dat); in s5p_gpio_get_value()
118 return !!(value & DAT_MASK(gpio)); in s5p_gpio_get_value()
122 static void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode) in s5p_gpio_set_pull() argument
126 value = readl(&bank->pull); in s5p_gpio_set_pull()
127 value &= ~PULL_MASK(gpio); in s5p_gpio_set_pull()
132 value |= PULL_MODE(gpio, mode); in s5p_gpio_set_pull()
138 writel(value, &bank->pull); in s5p_gpio_set_pull()
141 static void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode) in s5p_gpio_set_drv() argument
145 value = readl(&bank->drv); in s5p_gpio_set_drv()
146 value &= ~DRV_MASK(gpio); in s5p_gpio_set_drv()
153 value |= DRV_SET(gpio, mode); in s5p_gpio_set_drv()
159 writel(value, &bank->drv); in s5p_gpio_set_drv()
162 static void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode) in s5p_gpio_set_rate() argument
166 value = readl(&bank->drv); in s5p_gpio_set_rate()
167 value &= ~RATE_MASK(gpio); in s5p_gpio_set_rate()
172 value |= RATE_SET(gpio); in s5p_gpio_set_rate()
178 writel(value, &bank->drv); in s5p_gpio_set_rate()
181 int s5p_gpio_get_pin(unsigned gpio) in s5p_gpio_get_pin() argument
183 return S5P_GPIO_GET_PIN(gpio); in s5p_gpio_get_pin()
188 /* set GPIO pin 'gpio' as an input */
193 /* Configure GPIO direction as input. */ in exynos_gpio_direction_input()
194 s5p_gpio_cfg_pin(state->bank, offset, S5P_GPIO_INPUT); in exynos_gpio_direction_input()
199 /* set GPIO pin 'gpio' as an output, with polarity 'value' */
205 /* Configure GPIO output value. */ in exynos_gpio_direction_output()
206 s5p_gpio_set_value(state->bank, offset, value); in exynos_gpio_direction_output()
208 /* Configure GPIO direction as output. */ in exynos_gpio_direction_output()
209 s5p_gpio_cfg_pin(state->bank, offset, S5P_GPIO_OUTPUT); in exynos_gpio_direction_output()
214 /* read GPIO IN value of pin 'gpio' */
219 return s5p_gpio_get_value(state->bank, offset); in exynos_gpio_get_value()
222 /* write GPIO OUT value to pin 'gpio' */
228 s5p_gpio_set_value(state->bank, offset, value); in exynos_gpio_set_value()
235 * There is no common GPIO API for pull, drv, pin, rate (yet). These
238 void gpio_set_pull(int gpio, int mode) in gpio_set_pull() argument
240 s5p_gpio_set_pull(s5p_gpio_get_bank(gpio), in gpio_set_pull()
241 s5p_gpio_get_pin(gpio), mode); in gpio_set_pull()
244 void gpio_set_drv(int gpio, int mode) in gpio_set_drv() argument
246 s5p_gpio_set_drv(s5p_gpio_get_bank(gpio), in gpio_set_drv()
247 s5p_gpio_get_pin(gpio), mode); in gpio_set_drv()
250 void gpio_cfg_pin(int gpio, int cfg) in gpio_cfg_pin() argument
252 s5p_gpio_cfg_pin(s5p_gpio_get_bank(gpio), in gpio_cfg_pin()
253 s5p_gpio_get_pin(gpio), cfg); in gpio_cfg_pin()
256 void gpio_set_rate(int gpio, int mode) in gpio_set_rate() argument
258 s5p_gpio_set_rate(s5p_gpio_get_bank(gpio), in gpio_set_rate()
259 s5p_gpio_get_pin(gpio), mode); in gpio_set_rate()
268 cfg = s5p_gpio_get_cfg_pin(state->bank, offset); in exynos_gpio_get_function()
288 struct exynos_bank_info *priv = dev->priv; in gpio_exynos_probe()
289 struct exynos_gpio_platdata *plat = dev->platdata; in gpio_exynos_probe()
295 priv->bank = plat->bank; in gpio_exynos_probe()
297 uc_priv->gpio_count = GPIO_PER_BANK; in gpio_exynos_probe()
298 uc_priv->bank_name = plat->bank_name; in gpio_exynos_probe()
304 * We have a top-level GPIO device with no actual GPIOs. It has a child
305 * device for each Exynos GPIO bank.
309 struct exynos_gpio_platdata *plat = parent->platdata; in gpio_exynos_bind()
311 const void *blob = gd->fdt_blob; in gpio_exynos_bind()
327 if (!fdtdec_get_bool(blob, node, "gpio-controller")) in gpio_exynos_bind()
331 return -ENOMEM; in gpio_exynos_bind()
333 plat->bank_name = fdt_get_name(blob, node, NULL); in gpio_exynos_bind()
334 ret = device_bind(parent, parent->driver, in gpio_exynos_bind()
335 plat->bank_name, plat, -1, &dev); in gpio_exynos_bind()
345 plat->bank = bank; in gpio_exynos_bind()
347 debug("dev at %p: %s\n", bank, plat->bank_name); in gpio_exynos_bind()
354 { .compatible = "samsung,s5pc100-pinctrl" },
355 { .compatible = "samsung,s5pc110-pinctrl" },
356 { .compatible = "samsung,exynos4210-pinctrl" },
357 { .compatible = "samsung,exynos4x12-pinctrl" },
358 { .compatible = "samsung,exynos5250-pinctrl" },
359 { .compatible = "samsung,exynos5420-pinctrl" },