Home
last modified time | relevance | path

Searched full:driving (Results 1 – 25 of 96) sorted by relevance

1234

/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_axp_mc_static.h42 {0x000014C0, 0x192434e9}, /* DRAM address and Control Driving Strenght */
43 {0x000014C4, 0x092434e9}, /* DRAM Data and DQS Driving Strenght */
100 {0x000014C0, 0x192434e9}, /* DRAM address and Control Driving Strenght */
101 {0x000014C4, 0x092434e9}, /* DRAM Data and DQS Driving Strenght */
152 {0x000014C0, 0x192424C8}, /* DRAM address and Control Driving Strenght */
153 {0x000014C4, 0xEFB24C8}, /* DRAM Data and DQS Driving Strenght */
209 {0x000014C0, 0x192424C8}, /* DRAM address and Control Driving Strenght */
210 {0x000014C4, 0xEFB24C8}, /* DRAM Data and DQS Driving Strenght */
258 {0x000014C0, 0x192424C8}, /* DRAM address and Control Driving Strenght */
259 {0x000014C4, 0xEFB24C8}, /* DRAM Data and DQS Driving Strenght */
/openbmc/u-boot/drivers/usb/gadget/
H A Dbcm_udc_otg_phy.c20 /* set Phy to driving mode */ in otg_phy_init()
50 /* set Phy to non-driving (reset) mode */ in otg_phy_off()
/openbmc/u-boot/board/cssi/MCR3000/
H A Dnand.c30 /* Driving NCE pin */ in nand_hwcontrol()
36 /* Driving CLE and ALE pin */ in nand_hwcontrol()
/openbmc/phosphor-dbus-interfaces/yaml/xyz/openbmc_project/Debug/Pid/
H A DZone.interface.yaml10 This means the name of the thermal/Power PID config that is driving
/openbmc/openbmc/meta-raspberrypi/.github/workflows/docker-images/yocto-builder/
H A DREADME.md10 privides multiple scripts for driving different operations.
/openbmc/u-boot/drivers/video/
H A Danx9804.h9 * interface for driving eDP TFT displays.
H A Dssd2828.h9 * interface for driving a MIPI compatible TFT display.
12 * responsible for driving parallel LCD hardware in front of the video pipeline.
/openbmc/u-boot/doc/device-tree-bindings/usb/
H A Dmarvell.xhci-usb.txt15 - clocks: phandle to system controller clock driving this unit
/openbmc/u-boot/drivers/pinctrl/mediatek/
H A Dpinctrl-mtk-common.h51 /* Group the pins by the driving current */
120 * @drv_n: the index with the driving group
/openbmc/qemu/python/qemu/machine/
H A D__init__.py4 This library provides a few high-level classes for driving QEMU from a
/openbmc/u-boot/include/andestech/
H A Dandes_pcu.h31 unsigned int dcsrcr0; /* 0x20 - Driving Capability
33 unsigned int dcsrcr1; /* 0x24 - Driving Capability
35 unsigned int dcsrcr2; /* 0x28 - Driving Capability
141 * Driving Capability and Slew Rate Control Register 0 (rw)
150 * Driving Capability and Slew Rate Control Register 1 (rw)
155 * Driving Capability and Slew Rate Control Register 2 (rw)
/openbmc/u-boot/board/gdsys/common/
H A Ddp501.c109 i2c_reg_write(addr + 2, 0x00, 0x18); /* driving strength */ in dp501_powerup()
110 i2c_reg_write(addr + 2, 0x03, 0x06); /* driving strength */ in dp501_powerup()
/openbmc/u-boot/board/maxbcm/
H A Dmaxbcm.c46 {0x000014C0, 0x192424C9}, /* DRAM addr and Ctrl Driving Strenght*/
47 {0x000014C4, 0xAAA24C9}, /* DRAM Data and DQS Driving Strenght */
/openbmc/qemu/include/hw/display/
H A Ddm163.h3 * driving columns of associated 8x8 RGB matrix.
/openbmc/u-boot/drivers/adc/
H A DKconfig4 This enables ADC API for drivers, which allows driving ADC features
/openbmc/qemu/include/hw/gpio/
H A Dstm32l4x5_gpio.h54 * External driving of pins.
/openbmc/openbmc/meta-asrock/meta-e3c256d4i/recipes-x86/chassis/x86-power-control/
H A Dpower-config-host0.json20 // (normally the NMI button input) instead as an output and driving
/openbmc/u-boot/board/Synology/ds414/
H A Dds414.c74 {0x000014C0, 0x192424C9}, /* DRAM address and Control Driving Strenght */
75 {0x000014C4, 0x0AAA24C9}, /* DRAM Data and DQS Driving Strenght */
/openbmc/u-boot/drivers/spi/
H A Dmscc_bb_spi.c78 /* Keep driving the CLK to its current value while in mscc_bb_spi_cs_deactivate()
87 /* Stop driving the clock, but keep CS with nCS == 1 */ in mscc_bb_spi_cs_deactivate()
/openbmc/u-boot/drivers/reset/
H A DKconfig12 although driving such reset isgnals using GPIOs may be more
/openbmc/u-boot/board/buffalo/lsxl/
H A Dkwbimage-lschl.cfg201 # bit20-16: 0, Pad N channel driving strength for ODT
202 # bit25-21: 0, Pad P channel driving strength for ODT
H A Dkwbimage-lsxhl.cfg201 # bit20-16: 0, Pad N channel driving strength for ODT
202 # bit25-21: 0, Pad P channel driving strength for ODT
/openbmc/u-boot/board/d-link/dns325/
H A Dkwbimage.cfg181 # bit20-16: 0, Pad N channel driving strength for ODT
182 # bit25-21: 0, Pad P channel driving strength for ODT
/openbmc/witherspoon-pfault-analysis/power-sequencer/
H A Druntime_monitor.hpp25 * driving power to a faulted component.
/openbmc/u-boot/doc/device-tree-bindings/gpio/
H A Dgpio-pcf857x.txt7 (a) as output and driving the signal low/high, or (b) as input and reporting a

1234