1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 2854cbd29SJiandong Zheng /* 3854cbd29SJiandong Zheng * Copyright 2015 Broadcom Corporation. 4854cbd29SJiandong Zheng */ 5854cbd29SJiandong Zheng 6854cbd29SJiandong Zheng #include <config.h> 7854cbd29SJiandong Zheng #include <common.h> 8854cbd29SJiandong Zheng #include <asm/io.h> 9854cbd29SJiandong Zheng #include <asm/arch/sysmap.h> 10cf125473SSteve Rae #include <asm/kona-common/clk.h> 11854cbd29SJiandong Zheng 12f4d9bd06SMarek Vasut #include "dwc2_udc_otg_priv.h" 13854cbd29SJiandong Zheng #include "bcm_udc_otg.h" 14854cbd29SJiandong Zheng otg_phy_init(struct dwc2_udc * dev)15b4d5cf0bSMarek Vasutvoid otg_phy_init(struct dwc2_udc *dev) 16854cbd29SJiandong Zheng { 17cf125473SSteve Rae /* turn on the USB OTG clocks */ 18cf125473SSteve Rae clk_usb_otg_enable((void *)HSOTG_BASE_ADDR); 19cf125473SSteve Rae 20854cbd29SJiandong Zheng /* set Phy to driving mode */ 21854cbd29SJiandong Zheng wfld_clear(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET, 22854cbd29SJiandong Zheng HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK); 23854cbd29SJiandong Zheng 24854cbd29SJiandong Zheng udelay(100); 25854cbd29SJiandong Zheng 26854cbd29SJiandong Zheng /* clear Soft Disconnect */ 27854cbd29SJiandong Zheng wfld_clear(HSOTG_BASE_ADDR + HSOTG_DCTL_OFFSET, 28854cbd29SJiandong Zheng HSOTG_DCTL_SFTDISCON_MASK); 29854cbd29SJiandong Zheng 30854cbd29SJiandong Zheng /* invoke Reset (active low) */ 31854cbd29SJiandong Zheng wfld_clear(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET, 32854cbd29SJiandong Zheng HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK); 33854cbd29SJiandong Zheng 34854cbd29SJiandong Zheng /* Reset needs to be asserted for 2ms */ 35854cbd29SJiandong Zheng udelay(2000); 36854cbd29SJiandong Zheng 37854cbd29SJiandong Zheng /* release Reset */ 38854cbd29SJiandong Zheng wfld_set(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET, 39854cbd29SJiandong Zheng HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK, 40854cbd29SJiandong Zheng HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK); 41854cbd29SJiandong Zheng } 42854cbd29SJiandong Zheng otg_phy_off(struct dwc2_udc * dev)43b4d5cf0bSMarek Vasutvoid otg_phy_off(struct dwc2_udc *dev) 44854cbd29SJiandong Zheng { 45854cbd29SJiandong Zheng /* Soft Disconnect */ 46854cbd29SJiandong Zheng wfld_set(HSOTG_BASE_ADDR + HSOTG_DCTL_OFFSET, 47854cbd29SJiandong Zheng HSOTG_DCTL_SFTDISCON_MASK, 48854cbd29SJiandong Zheng HSOTG_DCTL_SFTDISCON_MASK); 49854cbd29SJiandong Zheng 50854cbd29SJiandong Zheng /* set Phy to non-driving (reset) mode */ 51854cbd29SJiandong Zheng wfld_set(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET, 52854cbd29SJiandong Zheng HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK, 53854cbd29SJiandong Zheng HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK); 54854cbd29SJiandong Zheng } 55