/openbmc/linux/Documentation/devicetree/bindings/dma/ |
H A D | mediatek,uart-dma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/dma/mediatek,uart-dma.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Long Cheng <long.cheng@mediatek.com> 13 The MediaTek UART APDMA controller provides DMA capabilities 17 - $ref: dma-controller.yaml# 22 - items: 23 - enum: 24 - mediatek,mt2712-uart-dma [all …]
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H A D | stericsson,dma40.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/dma/stericsson,dma40.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: ST-Ericsson DMA40 DMA Engine 10 - Linus Walleij <linus.walleij@linaro.org> 13 - $ref: dma-controller.yaml# 16 "#dma-cells": 32 10: Multi-Channel Display Engine MCDE RX 55 33: SPI controller 2 [all …]
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/openbmc/linux/drivers/ata/ |
H A D | pata_pdc202xx_old.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * pata_pdc202xx_old.c - Promise PDC202xx PATA for new ATA layer 29 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in pdc2026x_cable_detect() 33 if (cis & (1 << (10 + ap->port_no))) in pdc2026x_cable_detect() 41 iowrite8(tf->command, ap->ioaddr.command_addr); in pdc202xx_exec_command() 47 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in pdc202xx_irq_check() 51 if (ap->port_no) { in pdc202xx_irq_check() 67 * pdc202xx_configure_piomode - set chip PIO timing 79 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in pdc202xx_configure_piomode() 80 int port = 0x60 + 8 * ap->port_no + 4 * adev->devno; in pdc202xx_configure_piomode() [all …]
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H A D | pata_optidma.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * pata_optidma.c - Opti DMA PATA for new ATA layer 6 * The Opti DMA controllers are related to the older PIO PCI controllers 11 * This driver should support Viper-N+, FireStar, FireStar Plus. 13 * These devices support virtual DMA for read (aka the CS5520). Later 15 * so you have to get this right. We don't support the virtual DMA 18 * Bits that are worth knowing 20 * 0x1F5 bit 0 tells you if the PCI/VLB clock is 33 or 25Mhz 21 * Virtual DMA registers *move* between rev 0x02 and rev 0x10 45 static int pci_clock; /* 0 = 33 1 = 25 */ [all …]
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H A D | pata_sc1200.c | 1 // SPDX-License-Identifier: GPL-2.0-only 6 * TODO: Needs custom DMA cleanup code 10 * linux/drivers/ide/pci/sc1200.c Version 0.91 28-Jan-2003 12 * Copyright (C) 2000-2002 Mark Lord <mlord@pobox.com> 37 * sc1200_clock - PCI clock 40 * in use. We return 0 for 33MHz 1 for 48MHz and 2 for 66Mhz 51 return 0; /* 33 MHz mode */ in sc1200_clock() 54 0/3 is 33Mhz 1 is 48 2 is 66 */ in sc1200_clock() 65 * sc1200_set_piomode - PIO setup 75 /* format0, 33Mhz */ in sc1200_set_piomode() [all …]
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H A D | pata_cypress.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * pata_cypress.c - Cypress PATA for new ATA layer 46 MODULE_PARM_DESC(enable_dma, "Enable bus master DMA operations"); 49 * cy82c693_set_piomode - set initial PIO mode data 58 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in cy82c693_set_piomode() 60 const unsigned long T = 1000000 / 33; in cy82c693_set_piomode() 64 if (ata_timing_compute(adev, adev->pio_mode, &t, T, 1) < 0) { in cy82c693_set_piomode() 69 time_16 = clamp_val(t.recover - 1, 0, 15) | in cy82c693_set_piomode() 70 (clamp_val(t.active - 1, 0, 15) << 4); in cy82c693_set_piomode() 71 time_8 = clamp_val(t.act8b - 1, 0, 15) | in cy82c693_set_piomode() [all …]
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H A D | pata_artop.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * pata_artop.c - ARTOP ATA controller driver 9 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org> 11 * driver by Thibaut VARENE <varenet@parisc-linux.org> 34 * The ARTOP has 33 Mhz and "over clocked" timing tables. Until we 43 * artop62x0_pre_reset - probe begin 57 struct ata_port *ap = link->ap; in artop62x0_pre_reset() 58 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in artop62x0_pre_reset() 60 /* Odd numbered device ids are the units with enable bits. */ in artop62x0_pre_reset() 61 if ((pdev->device & 1) && in artop62x0_pre_reset() [all …]
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/openbmc/linux/arch/arm/boot/dts/intel/pxa/ |
H A D | pxa27x.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 4 #include "dt-bindings/clock/pxa-clock.h" 11 pdma: dma-controller@40000000 { 12 compatible = "marvell,pdma-1.0"; 15 #dma-cells = <2>; 17 #dma-channels = <32>; 18 dma-channels = <32>; 19 #dma-requests = <75>; 20 dma-requests = <75>; 24 pxairq: interrupt-controller@40d00000 { [all …]
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/openbmc/linux/arch/arm/boot/dts/ti/davinci/ |
H A D | da850.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later 6 #include <dt-bindings/interrupt-controller/irq.h> 9 #address-cells = <1>; 10 #size-cells = <1>; 20 #address-cells = <1>; 21 #size-cells = <0>; 24 compatible = "arm,arm926ej-s"; 28 operating-points-v2 = <&opp_table>; 32 opp_table: opp-table { 33 compatible = "operating-points-v2"; [all …]
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/openbmc/linux/arch/sparc/kernel/ |
H A D | pci_sabre.c | 1 // SPDX-License-Identifier: GPL-2.0 33 #define SABRE_UEAFSR_PDRD 0x4000000000000000UL /* Primary PCI DMA Read */ 34 #define SABRE_UEAFSR_PDWR 0x2000000000000000UL /* Primary PCI DMA Write */ 35 #define SABRE_UEAFSR_SDRD 0x0800000000000000UL /* Secondary PCI DMA Read */ 36 #define SABRE_UEAFSR_SDWR 0x0400000000000000UL /* Secondary PCI DMA Write */ 37 #define SABRE_UEAFSR_SDTE 0x0200000000000000UL /* Secondary DMA Translation Error */ 38 #define SABRE_UEAFSR_PDTE 0x0100000000000000UL /* Primary DMA Translation Error */ 40 #define SABRE_UEAFSR_OFF 0x00000000e0000000UL /* Offset (AFAR bits [5:3] */ 44 #define SABRE_CEAFSR_PDRD 0x4000000000000000UL /* Primary PCI DMA Read */ 45 #define SABRE_CEAFSR_PDWR 0x2000000000000000UL /* Primary PCI DMA Write */ [all …]
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/openbmc/u-boot/arch/arm/dts/ |
H A D | da850.dtsi | 10 #include <dt-bindings/interrupt-controller/irq.h> 13 #address-cells = <1>; 14 #size-cells = <1>; 24 #address-cells = <1>; 25 #size-cells = <1>; 27 intc: interrupt-controller@fffee000 { 28 compatible = "ti,cp-intc"; 29 interrupt-controller; 30 #interrupt-cells = <1>; 31 ti,intc-size = <101>; [all …]
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/openbmc/linux/arch/powerpc/include/asm/nohash/32/ |
H A D | pte-85xx.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 11 32 33 34 35 36 ... 50 51 52 53 54 55 56 57 58 59 60 61 62 63 14 - PRESENT *must* be in the bottom two bits because swap PTEs use 15 the top 30 bits. 19 /* Definitions for FSL Book-E Cores */ 52 * We define 2 sets of base prot bits, one for basic pages (ie, 55 * the processor might need it for DMA coherency.
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/openbmc/linux/include/uapi/linux/ |
H A D | virtio_config.h | 49 * Virtio feature bits VIRTIO_TRANSPORT_F_START through 52 * rest are per-device feature bits. 70 * If clear - device has the platform DMA (e.g. IOMMU) bypass quirk feature. 71 * If set - use platform DMA tools to access the memory. 76 #define VIRTIO_F_ACCESS_PLATFORM 33
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/openbmc/linux/drivers/iommu/ |
H A D | io-pgtable-arm-v7s.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * CPU-agnostic ARM page table allocator. 5 * ARMv7 Short-descriptor format, supporting 6 * - Basic memory attributes 7 * - Simplified access permissions (AP[2:1] model) 8 * - Backwards-compatible TEX remap 9 * - Large pages/supersections (if indicated by the caller) 12 * - Legacy access permissions (AP[2:0] model) 15 * - PXN 16 * - Domains [all …]
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/openbmc/linux/Documentation/devicetree/bindings/display/imx/ |
H A D | fsl,imx-lcdc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/display/imx/fsl,imx-lcdc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Sascha Hauer <s.hauer@pengutronix.de> 11 - Pengutronix Kernel Team <kernel@pengutronix.de> 16 - enum: 17 - fsl,imx1-fb 18 - fsl,imx21-fb 19 - items: [all …]
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/openbmc/qemu/include/standard-headers/linux/ |
H A D | virtio_config.h | 32 #include "standard-headers/linux/types.h" 49 * Virtio feature bits VIRTIO_TRANSPORT_F_START through 52 * rest are per-device feature bits. 70 * If clear - device has the platform DMA (e.g. IOMMU) bypass quirk feature. 71 * If set - use platform DMA tools to access the memory. 76 #define VIRTIO_F_ACCESS_PLATFORM 33
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/openbmc/linux/arch/arm64/boot/dts/socionext/ |
H A D | uniphier-pxs3.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/gpio/uniphier-gpio.h> 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 11 #include <dt-bindings/thermal/thermal.h> 14 compatible = "socionext,uniphier-pxs3"; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 interrupt-parent = <&gic>; 20 #address-cells = <2>; [all …]
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H A D | uniphier-ld11.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/gpio/uniphier-gpio.h> 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 13 compatible = "socionext,uniphier-ld11"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <0>; [all …]
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H A D | uniphier-ld20.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT 5 // Copyright (C) 2015-2016 Socionext Inc. 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/gpio/uniphier-gpio.h> 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 11 #include <dt-bindings/thermal/thermal.h> 14 compatible = "socionext,uniphier-ld20"; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 interrupt-parent = <&gic>; [all …]
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/openbmc/u-boot/board/micronas/vct/ |
H A D | scc.c | 1 // SPDX-License-Identifier: GPL-2.0+ 35 /** Issue#7674 (new) - DP/DVP buffer assignment */ 48 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 89 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 100 * followed by the list of data path values in bits. 179 {"ewa", "ewarp_rw", SRMD, SCC15_BASE, 15, 11, 1, 1, 0, 0, 0, -1, 0, 0, 187 {"dvp", "dvp_vbi_rd", STRM_D, SCC19_BASE, 19, 31, 1, 0, 0, 1, 0, -1, 0, 189 {"tsi", "tsio_wr", STRM_P, SCC20_BASE, 20, 5, 0, 8, 2, 1, 1, -1, 0, 0, 191 {"tsi", "tsio_rd", STRM_P, SCC21_BASE, 21, 32, 4, 0, 2, 1, 1, -1, 0, 0, 193 {"tsd", "tsd_wr", SRMD, SCC22_BASE, 22, 6, 0, 64, 0, 0, 1, -1, 0, 0, [all …]
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/openbmc/linux/drivers/net/ethernet/sun/ |
H A D | cassini.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */ 22 * PCI: 33/66MHz clock 29 /* cassini register map: 2M memory mapped in 32-bit memory space accessible as 30 * 32-bit words. there is no i/o port access. REG_ addresses are 45 * DEFAULT: 0x0, SIZE: 5 bits 62 /* top level interrupts [0-9] are auto-cleared to 0 when the status 63 * register is read. second level interrupts [13 - 18] are cleared at 64 * the source. tx completion register 3 is replicated in [19 - 31] 65 * DEFAULT: 0x00000000, SIZE: 29 bits 104 len of non-reassembly pkt [all …]
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/openbmc/linux/drivers/pci/controller/ |
H A D | pci-ftpci100.c | 1 // SPDX-License-Identifier: GPL-2.0 7 * Based on the out-of-tree OpenWRT patch for Cortina Gemini: 54 /* Bits 31..28 gives INTD..INTA status */ 58 /* Bits 25..22 masks INTD..INTA */ 74 /* Bits 7..4 reserved */ 75 /* Bits 3..0 TRDYW */ 80 * Bit 19..16 (4 bits) defines the size per below 98 * The DMA base is set to 0x0 for all memory segments, it reflects the 106 * struct faraday_pci_variant - encodes IP block differences 165 return -EINVAL; in faraday_res_to_memcfg() [all …]
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/openbmc/u-boot/board/armadeus/apf27/ |
H A D | apf27.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */ 3 * Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige@armadeus.org> 47 #define CONFIG_PERIF2_FREQ 33 /* 33.25 MHz CSPI and SDHC */ 48 #define CONFIG_PERIF3_FREQ 33 /* 33.25 MHz LCD */ 49 #define CONFIG_PERIF4_FREQ 33 /* 33.25 MHz CSI */ 66 #if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */ 69 * column address bits 72 * row address bits 90 #define ACFG_SDRAM_RAS_DELAY 42 /* ns ACTIVE-to-PRECHARGE delay */ 91 #define ACFG_SDRAM_RRD_DELAY 12 /* ns ACTIVE-to-ACTIVE delay */ [all …]
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/openbmc/linux/arch/arm64/include/asm/ |
H A D | cache.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 19 /* Ctypen, bits[3(n - 1) + 2 : 3(n - 1)], for n = 1 to 7 */ 20 #define CLIDR_CTYPE_SHIFT(level) (3 * (level - 1)) 25 /* Ttypen, bits [2(n - 1) + 34 : 2(n - 1) + 33], for n = 1 to 7 */ 26 #define CLIDR_TTYPE_SHIFT(level) (2 * ((level) - 1) + CLIDR_EL1_Ttypen_SHIFT) 29 * Memory returned by kmalloc() may be used for DMA, so we must make 41 #include <linux/kasan-enabled.h> 44 #include <asm/mte-def.h> 65 * Whilst the D-side always behaves as PIPT on AArch64, aliasing is 66 * permitted in the I-cache. [all …]
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/openbmc/linux/arch/mips/include/asm/octeon/ |
H A D | cvmx-address.h | 7 * Copyright (c) 2003-2009 Cavium Networks 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 60 /* decode within DMA space */ 76 /* send out a single-tick command on the NCB bus */ 84 * Octeon-I HW never interprets this X (<39:36> reserved 87 * - 0x0 XXX0 0000 0000 to DRAM Cached 88 * - 0x0 XXX0 0FFF FFFF 90 * - 0x0 XXX0 1000 0000 to Boot Bus Uncached (Converted to 0x1 00X0 1000 0000 91 * - 0x0 XXX0 1FFF FFFF + EJTAG to 0x1 00X0 1FFF FFFF) [all …]
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