1af866496SDavid Daney /***********************license start*************** 2af866496SDavid Daney * Author: Cavium Networks 3af866496SDavid Daney * 4af866496SDavid Daney * Contact: support@caviumnetworks.com 5af866496SDavid Daney * This file is part of the OCTEON SDK 6af866496SDavid Daney * 7af866496SDavid Daney * Copyright (c) 2003-2009 Cavium Networks 8af866496SDavid Daney * 9af866496SDavid Daney * This file is free software; you can redistribute it and/or modify 10af866496SDavid Daney * it under the terms of the GNU General Public License, Version 2, as 11af866496SDavid Daney * published by the Free Software Foundation. 12af866496SDavid Daney * 13af866496SDavid Daney * This file is distributed in the hope that it will be useful, but 14af866496SDavid Daney * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15af866496SDavid Daney * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16af866496SDavid Daney * NONINFRINGEMENT. See the GNU General Public License for more 17af866496SDavid Daney * details. 18af866496SDavid Daney * 19af866496SDavid Daney * You should have received a copy of the GNU General Public License 20af866496SDavid Daney * along with this file; if not, write to the Free Software 21af866496SDavid Daney * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 22af866496SDavid Daney * or visit http://www.gnu.org/licenses/. 23af866496SDavid Daney * 24af866496SDavid Daney * This file may also be available under a different license from Cavium. 25af866496SDavid Daney * Contact Cavium Networks for more information 26af866496SDavid Daney ***********************license end**************************************/ 27af866496SDavid Daney 28af866496SDavid Daney /** 29af866496SDavid Daney * Typedefs and defines for working with Octeon physical addresses. 30af866496SDavid Daney * 31af866496SDavid Daney */ 32af866496SDavid Daney #ifndef __CVMX_ADDRESS_H__ 33af866496SDavid Daney #define __CVMX_ADDRESS_H__ 34af866496SDavid Daney 35af866496SDavid Daney #if 0 36af866496SDavid Daney typedef enum { 37af866496SDavid Daney CVMX_MIPS_SPACE_XKSEG = 3LL, 38af866496SDavid Daney CVMX_MIPS_SPACE_XKPHYS = 2LL, 39af866496SDavid Daney CVMX_MIPS_SPACE_XSSEG = 1LL, 40af866496SDavid Daney CVMX_MIPS_SPACE_XUSEG = 0LL 41af866496SDavid Daney } cvmx_mips_space_t; 42af866496SDavid Daney #endif 43af866496SDavid Daney 44af866496SDavid Daney typedef enum { 45af866496SDavid Daney CVMX_MIPS_XKSEG_SPACE_KSEG0 = 0LL, 46af866496SDavid Daney CVMX_MIPS_XKSEG_SPACE_KSEG1 = 1LL, 47af866496SDavid Daney CVMX_MIPS_XKSEG_SPACE_SSEG = 2LL, 48af866496SDavid Daney CVMX_MIPS_XKSEG_SPACE_KSEG3 = 3LL 49af866496SDavid Daney } cvmx_mips_xkseg_space_t; 50af866496SDavid Daney 51af866496SDavid Daney /* decodes <14:13> of a kseg3 window address */ 52af866496SDavid Daney typedef enum { 53af866496SDavid Daney CVMX_ADD_WIN_SCR = 0L, 54af866496SDavid Daney /* see cvmx_add_win_dma_dec_t for further decode */ 55af866496SDavid Daney CVMX_ADD_WIN_DMA = 1L, 56af866496SDavid Daney CVMX_ADD_WIN_UNUSED = 2L, 57af866496SDavid Daney CVMX_ADD_WIN_UNUSED2 = 3L 58af866496SDavid Daney } cvmx_add_win_dec_t; 59af866496SDavid Daney 60af866496SDavid Daney /* decode within DMA space */ 61af866496SDavid Daney typedef enum { 62af866496SDavid Daney /* 63af866496SDavid Daney * Add store data to the write buffer entry, allocating it if 64af866496SDavid Daney * necessary. 65af866496SDavid Daney */ 66af866496SDavid Daney CVMX_ADD_WIN_DMA_ADD = 0L, 67af866496SDavid Daney /* send out the write buffer entry to DRAM */ 68af866496SDavid Daney CVMX_ADD_WIN_DMA_SENDMEM = 1L, 69af866496SDavid Daney /* store data must be normal DRAM memory space address in this case */ 70af866496SDavid Daney /* send out the write buffer entry as an IOBDMA command */ 71af866496SDavid Daney CVMX_ADD_WIN_DMA_SENDDMA = 2L, 72af866496SDavid Daney /* see CVMX_ADD_WIN_DMA_SEND_DEC for data contents */ 73af866496SDavid Daney /* send out the write buffer entry as an IO write */ 74af866496SDavid Daney CVMX_ADD_WIN_DMA_SENDIO = 3L, 75af866496SDavid Daney /* store data must be normal IO space address in this case */ 76af866496SDavid Daney /* send out a single-tick command on the NCB bus */ 77af866496SDavid Daney CVMX_ADD_WIN_DMA_SENDSINGLE = 4L, 78af866496SDavid Daney /* no write buffer data needed/used */ 79af866496SDavid Daney } cvmx_add_win_dma_dec_t; 80af866496SDavid Daney 81af866496SDavid Daney /* 82af866496SDavid Daney * Physical Address Decode 83af866496SDavid Daney * 84af866496SDavid Daney * Octeon-I HW never interprets this X (<39:36> reserved 85af866496SDavid Daney * for future expansion), software should set to 0. 86af866496SDavid Daney * 87af866496SDavid Daney * - 0x0 XXX0 0000 0000 to DRAM Cached 88af866496SDavid Daney * - 0x0 XXX0 0FFF FFFF 89af866496SDavid Daney * 90af866496SDavid Daney * - 0x0 XXX0 1000 0000 to Boot Bus Uncached (Converted to 0x1 00X0 1000 0000 91af866496SDavid Daney * - 0x0 XXX0 1FFF FFFF + EJTAG to 0x1 00X0 1FFF FFFF) 92af866496SDavid Daney * 93af866496SDavid Daney * - 0x0 XXX0 2000 0000 to DRAM Cached 94af866496SDavid Daney * - 0x0 XXXF FFFF FFFF 95af866496SDavid Daney * 96af866496SDavid Daney * - 0x1 00X0 0000 0000 to Boot Bus Uncached 97af866496SDavid Daney * - 0x1 00XF FFFF FFFF 98af866496SDavid Daney * 99af866496SDavid Daney * - 0x1 01X0 0000 0000 to Other NCB Uncached 100af866496SDavid Daney * - 0x1 FFXF FFFF FFFF devices 101af866496SDavid Daney * 102af866496SDavid Daney * Decode of all Octeon addresses 103af866496SDavid Daney */ 104af866496SDavid Daney typedef union { 105af866496SDavid Daney 106af866496SDavid Daney uint64_t u64; 10711db04c8SPaul Martin #ifdef __BIG_ENDIAN_BITFIELD 108af866496SDavid Daney /* mapped or unmapped virtual address */ 109af866496SDavid Daney struct { 110af866496SDavid Daney uint64_t R:2; 111af866496SDavid Daney uint64_t offset:62; 112af866496SDavid Daney } sva; 113af866496SDavid Daney 114af866496SDavid Daney /* mapped USEG virtual addresses (typically) */ 115af866496SDavid Daney struct { 116af866496SDavid Daney uint64_t zeroes:33; 117af866496SDavid Daney uint64_t offset:31; 118af866496SDavid Daney } suseg; 119af866496SDavid Daney 120af866496SDavid Daney /* mapped or unmapped virtual address */ 121af866496SDavid Daney struct { 122af866496SDavid Daney uint64_t ones:33; 123af866496SDavid Daney uint64_t sp:2; 124af866496SDavid Daney uint64_t offset:29; 125af866496SDavid Daney } sxkseg; 126af866496SDavid Daney 127af866496SDavid Daney /* 128af866496SDavid Daney * physical address accessed through xkphys unmapped virtual 129af866496SDavid Daney * address. 130af866496SDavid Daney */ 131af866496SDavid Daney struct { 132af866496SDavid Daney uint64_t R:2; /* CVMX_MIPS_SPACE_XKPHYS in this case */ 133af866496SDavid Daney uint64_t cca:3; /* ignored by octeon */ 134af866496SDavid Daney uint64_t mbz:10; 135af866496SDavid Daney uint64_t pa:49; /* physical address */ 136af866496SDavid Daney } sxkphys; 137af866496SDavid Daney 138af866496SDavid Daney /* physical address */ 139af866496SDavid Daney struct { 140af866496SDavid Daney uint64_t mbz:15; 141af866496SDavid Daney /* if set, the address is uncached and resides on MCB bus */ 142af866496SDavid Daney uint64_t is_io:1; 143af866496SDavid Daney /* 144af866496SDavid Daney * the hardware ignores this field when is_io==0, else 145af866496SDavid Daney * device ID. 146af866496SDavid Daney */ 147af866496SDavid Daney uint64_t did:8; 148af866496SDavid Daney /* the hardware ignores <39:36> in Octeon I */ 149af866496SDavid Daney uint64_t unaddr:4; 150af866496SDavid Daney uint64_t offset:36; 151af866496SDavid Daney } sphys; 152af866496SDavid Daney 153af866496SDavid Daney /* physical mem address */ 154af866496SDavid Daney struct { 155*daffdec4SBhaskar Chowdhury /* technically, <47:40> are dont-cares */ 156af866496SDavid Daney uint64_t zeroes:24; 157af866496SDavid Daney /* the hardware ignores <39:36> in Octeon I */ 158af866496SDavid Daney uint64_t unaddr:4; 159af866496SDavid Daney uint64_t offset:36; 160af866496SDavid Daney } smem; 161af866496SDavid Daney 162af866496SDavid Daney /* physical IO address */ 163af866496SDavid Daney struct { 164af866496SDavid Daney uint64_t mem_region:2; 165af866496SDavid Daney uint64_t mbz:13; 166af866496SDavid Daney /* 1 in this case */ 167af866496SDavid Daney uint64_t is_io:1; 168af866496SDavid Daney /* 169af866496SDavid Daney * The hardware ignores this field when is_io==0, else 170af866496SDavid Daney * device ID. 171af866496SDavid Daney */ 172af866496SDavid Daney uint64_t did:8; 173af866496SDavid Daney /* the hardware ignores <39:36> in Octeon I */ 174af866496SDavid Daney uint64_t unaddr:4; 175af866496SDavid Daney uint64_t offset:36; 176af866496SDavid Daney } sio; 177af866496SDavid Daney 178af866496SDavid Daney /* 179af866496SDavid Daney * Scratchpad virtual address - accessed through a window at 180af866496SDavid Daney * the end of kseg3 181af866496SDavid Daney */ 182af866496SDavid Daney struct { 183af866496SDavid Daney uint64_t ones:49; 184af866496SDavid Daney /* CVMX_ADD_WIN_SCR (0) in this case */ 185af866496SDavid Daney cvmx_add_win_dec_t csrdec:2; 186af866496SDavid Daney uint64_t addr:13; 187af866496SDavid Daney } sscr; 188af866496SDavid Daney 189af866496SDavid Daney /* there should only be stores to IOBDMA space, no loads */ 190af866496SDavid Daney /* 191af866496SDavid Daney * IOBDMA virtual address - accessed through a window at the 192af866496SDavid Daney * end of kseg3 193af866496SDavid Daney */ 194af866496SDavid Daney struct { 195af866496SDavid Daney uint64_t ones:49; 196af866496SDavid Daney uint64_t csrdec:2; /* CVMX_ADD_WIN_DMA (1) in this case */ 197af866496SDavid Daney uint64_t unused2:3; 198af866496SDavid Daney uint64_t type:3; 199af866496SDavid Daney uint64_t addr:7; 200af866496SDavid Daney } sdma; 201af866496SDavid Daney 202af866496SDavid Daney struct { 203af866496SDavid Daney uint64_t didspace:24; 204af866496SDavid Daney uint64_t unused:40; 205af866496SDavid Daney } sfilldidspace; 20611db04c8SPaul Martin #else 20711db04c8SPaul Martin struct { 20811db04c8SPaul Martin uint64_t offset:62; 20911db04c8SPaul Martin uint64_t R:2; 21011db04c8SPaul Martin } sva; 21111db04c8SPaul Martin 21211db04c8SPaul Martin struct { 21311db04c8SPaul Martin uint64_t offset:31; 21411db04c8SPaul Martin uint64_t zeroes:33; 21511db04c8SPaul Martin } suseg; 21611db04c8SPaul Martin 21711db04c8SPaul Martin struct { 21811db04c8SPaul Martin uint64_t offset:29; 21911db04c8SPaul Martin uint64_t sp:2; 22011db04c8SPaul Martin uint64_t ones:33; 22111db04c8SPaul Martin } sxkseg; 22211db04c8SPaul Martin 22311db04c8SPaul Martin struct { 22411db04c8SPaul Martin uint64_t pa:49; 22511db04c8SPaul Martin uint64_t mbz:10; 22611db04c8SPaul Martin uint64_t cca:3; 22711db04c8SPaul Martin uint64_t R:2; 22811db04c8SPaul Martin } sxkphys; 22911db04c8SPaul Martin 23011db04c8SPaul Martin struct { 23111db04c8SPaul Martin uint64_t offset:36; 23211db04c8SPaul Martin uint64_t unaddr:4; 23311db04c8SPaul Martin uint64_t did:8; 23411db04c8SPaul Martin uint64_t is_io:1; 23511db04c8SPaul Martin uint64_t mbz:15; 23611db04c8SPaul Martin } sphys; 23711db04c8SPaul Martin 23811db04c8SPaul Martin struct { 23911db04c8SPaul Martin uint64_t offset:36; 24011db04c8SPaul Martin uint64_t unaddr:4; 24111db04c8SPaul Martin uint64_t zeroes:24; 24211db04c8SPaul Martin } smem; 24311db04c8SPaul Martin 24411db04c8SPaul Martin struct { 24511db04c8SPaul Martin uint64_t offset:36; 24611db04c8SPaul Martin uint64_t unaddr:4; 24711db04c8SPaul Martin uint64_t did:8; 24811db04c8SPaul Martin uint64_t is_io:1; 24911db04c8SPaul Martin uint64_t mbz:13; 25011db04c8SPaul Martin uint64_t mem_region:2; 25111db04c8SPaul Martin } sio; 25211db04c8SPaul Martin 25311db04c8SPaul Martin struct { 25411db04c8SPaul Martin uint64_t addr:13; 25511db04c8SPaul Martin cvmx_add_win_dec_t csrdec:2; 25611db04c8SPaul Martin uint64_t ones:49; 25711db04c8SPaul Martin } sscr; 25811db04c8SPaul Martin 25911db04c8SPaul Martin struct { 26011db04c8SPaul Martin uint64_t addr:7; 26111db04c8SPaul Martin uint64_t type:3; 26211db04c8SPaul Martin uint64_t unused2:3; 26311db04c8SPaul Martin uint64_t csrdec:2; 26411db04c8SPaul Martin uint64_t ones:49; 26511db04c8SPaul Martin } sdma; 26611db04c8SPaul Martin 26711db04c8SPaul Martin struct { 26811db04c8SPaul Martin uint64_t unused:40; 26911db04c8SPaul Martin uint64_t didspace:24; 27011db04c8SPaul Martin } sfilldidspace; 27111db04c8SPaul Martin #endif 272af866496SDavid Daney 273af866496SDavid Daney } cvmx_addr_t; 274af866496SDavid Daney 275af866496SDavid Daney /* These macros for used by 32 bit applications */ 276af866496SDavid Daney 277af866496SDavid Daney #define CVMX_MIPS32_SPACE_KSEG0 1l 278af866496SDavid Daney #define CVMX_ADD_SEG32(segment, add) \ 279af866496SDavid Daney (((int32_t)segment << 31) | (int32_t)(add)) 280af866496SDavid Daney 281af866496SDavid Daney /* 282af866496SDavid Daney * Currently all IOs are performed using XKPHYS addressing. Linux uses 283af866496SDavid Daney * the CvmMemCtl register to enable XKPHYS addressing to IO space from 284af866496SDavid Daney * user mode. Future OSes may need to change the upper bits of IO 285af866496SDavid Daney * addresses. The following define controls the upper two bits for all 286af866496SDavid Daney * IO addresses generated by the simple executive library. 287af866496SDavid Daney */ 288af866496SDavid Daney #define CVMX_IO_SEG CVMX_MIPS_SPACE_XKPHYS 289af866496SDavid Daney 290af866496SDavid Daney /* These macros simplify the process of creating common IO addresses */ 291af866496SDavid Daney #define CVMX_ADD_SEG(segment, add) ((((uint64_t)segment) << 62) | (add)) 292af866496SDavid Daney #ifndef CVMX_ADD_IO_SEG 293af866496SDavid Daney #define CVMX_ADD_IO_SEG(add) CVMX_ADD_SEG(CVMX_IO_SEG, (add)) 294af866496SDavid Daney #endif 295af866496SDavid Daney #define CVMX_ADDR_DIDSPACE(did) (((CVMX_IO_SEG) << 22) | ((1ULL) << 8) | (did)) 296af866496SDavid Daney #define CVMX_ADDR_DID(did) (CVMX_ADDR_DIDSPACE(did) << 40) 297af866496SDavid Daney #define CVMX_FULL_DID(did, subdid) (((did) << 3) | (subdid)) 298af866496SDavid Daney 299af866496SDavid Daney /* from include/ncb_rsl_id.v */ 300af866496SDavid Daney #define CVMX_OCT_DID_MIS 0ULL /* misc stuff */ 301af866496SDavid Daney #define CVMX_OCT_DID_GMX0 1ULL 302af866496SDavid Daney #define CVMX_OCT_DID_GMX1 2ULL 303af866496SDavid Daney #define CVMX_OCT_DID_PCI 3ULL 304af866496SDavid Daney #define CVMX_OCT_DID_KEY 4ULL 305af866496SDavid Daney #define CVMX_OCT_DID_FPA 5ULL 306af866496SDavid Daney #define CVMX_OCT_DID_DFA 6ULL 307af866496SDavid Daney #define CVMX_OCT_DID_ZIP 7ULL 308af866496SDavid Daney #define CVMX_OCT_DID_RNG 8ULL 309af866496SDavid Daney #define CVMX_OCT_DID_IPD 9ULL 310af866496SDavid Daney #define CVMX_OCT_DID_PKT 10ULL 311af866496SDavid Daney #define CVMX_OCT_DID_TIM 11ULL 312af866496SDavid Daney #define CVMX_OCT_DID_TAG 12ULL 313af866496SDavid Daney /* the rest are not on the IO bus */ 314af866496SDavid Daney #define CVMX_OCT_DID_L2C 16ULL 315af866496SDavid Daney #define CVMX_OCT_DID_LMC 17ULL 316af866496SDavid Daney #define CVMX_OCT_DID_SPX0 18ULL 317af866496SDavid Daney #define CVMX_OCT_DID_SPX1 19ULL 318af866496SDavid Daney #define CVMX_OCT_DID_PIP 20ULL 319af866496SDavid Daney #define CVMX_OCT_DID_ASX0 22ULL 320af866496SDavid Daney #define CVMX_OCT_DID_ASX1 23ULL 321af866496SDavid Daney #define CVMX_OCT_DID_IOB 30ULL 322af866496SDavid Daney 323af866496SDavid Daney #define CVMX_OCT_DID_PKT_SEND CVMX_FULL_DID(CVMX_OCT_DID_PKT, 2ULL) 324af866496SDavid Daney #define CVMX_OCT_DID_TAG_SWTAG CVMX_FULL_DID(CVMX_OCT_DID_TAG, 0ULL) 325af866496SDavid Daney #define CVMX_OCT_DID_TAG_TAG1 CVMX_FULL_DID(CVMX_OCT_DID_TAG, 1ULL) 326af866496SDavid Daney #define CVMX_OCT_DID_TAG_TAG2 CVMX_FULL_DID(CVMX_OCT_DID_TAG, 2ULL) 327af866496SDavid Daney #define CVMX_OCT_DID_TAG_TAG3 CVMX_FULL_DID(CVMX_OCT_DID_TAG, 3ULL) 328af866496SDavid Daney #define CVMX_OCT_DID_TAG_NULL_RD CVMX_FULL_DID(CVMX_OCT_DID_TAG, 4ULL) 329af866496SDavid Daney #define CVMX_OCT_DID_TAG_CSR CVMX_FULL_DID(CVMX_OCT_DID_TAG, 7ULL) 330af866496SDavid Daney #define CVMX_OCT_DID_FAU_FAI CVMX_FULL_DID(CVMX_OCT_DID_IOB, 0ULL) 331af866496SDavid Daney #define CVMX_OCT_DID_TIM_CSR CVMX_FULL_DID(CVMX_OCT_DID_TIM, 0ULL) 332af866496SDavid Daney #define CVMX_OCT_DID_KEY_RW CVMX_FULL_DID(CVMX_OCT_DID_KEY, 0ULL) 333af866496SDavid Daney #define CVMX_OCT_DID_PCI_6 CVMX_FULL_DID(CVMX_OCT_DID_PCI, 6ULL) 334af866496SDavid Daney #define CVMX_OCT_DID_MIS_BOO CVMX_FULL_DID(CVMX_OCT_DID_MIS, 0ULL) 335af866496SDavid Daney #define CVMX_OCT_DID_PCI_RML CVMX_FULL_DID(CVMX_OCT_DID_PCI, 0ULL) 336af866496SDavid Daney #define CVMX_OCT_DID_IPD_CSR CVMX_FULL_DID(CVMX_OCT_DID_IPD, 7ULL) 337af866496SDavid Daney #define CVMX_OCT_DID_DFA_CSR CVMX_FULL_DID(CVMX_OCT_DID_DFA, 7ULL) 338af866496SDavid Daney #define CVMX_OCT_DID_MIS_CSR CVMX_FULL_DID(CVMX_OCT_DID_MIS, 7ULL) 339af866496SDavid Daney #define CVMX_OCT_DID_ZIP_CSR CVMX_FULL_DID(CVMX_OCT_DID_ZIP, 0ULL) 340af866496SDavid Daney 341af866496SDavid Daney #endif /* __CVMX_ADDRESS_H__ */ 342