1dfc3095cSChristophe Leroy /* SPDX-License-Identifier: GPL-2.0 */
2dfc3095cSChristophe Leroy #ifndef _ASM_POWERPC_NOHASH_32_PTE_85xx_H
3dfc3095cSChristophe Leroy #define _ASM_POWERPC_NOHASH_32_PTE_85xx_H
4dfc3095cSChristophe Leroy #ifdef __KERNEL__
5dfc3095cSChristophe Leroy 
6dfc3095cSChristophe Leroy /* PTE bit definitions for Freescale BookE SW loaded TLB MMU based
7dfc3095cSChristophe Leroy  * processors
8dfc3095cSChristophe Leroy  *
9dfc3095cSChristophe Leroy    MMU Assist Register 3:
10dfc3095cSChristophe Leroy 
11dfc3095cSChristophe Leroy    32 33 34 35 36  ... 50 51 52 53 54 55 56 57 58 59 60 61 62 63
12dfc3095cSChristophe Leroy    RPN......................  0  0 U0 U1 U2 U3 UX SX UW SW UR SR
13dfc3095cSChristophe Leroy 
14*2bba2ffbSDavid Hildenbrand    - PRESENT *must* be in the bottom two bits because swap PTEs use
15*2bba2ffbSDavid Hildenbrand      the top 30 bits.
16dfc3095cSChristophe Leroy 
17dfc3095cSChristophe Leroy */
18dfc3095cSChristophe Leroy 
19dfc3095cSChristophe Leroy /* Definitions for FSL Book-E Cores */
20dfc3095cSChristophe Leroy #define _PAGE_PRESENT	0x00001	/* S: PTE contains a translation */
21dfc3095cSChristophe Leroy #define _PAGE_USER	0x00002	/* S: User page (maps to UR) */
22dfc3095cSChristophe Leroy #define _PAGE_RW	0x00004	/* S: Write permission (SW) */
23dfc3095cSChristophe Leroy #define _PAGE_DIRTY	0x00008	/* S: Page dirty */
24dfc3095cSChristophe Leroy #define _PAGE_EXEC	0x00010	/* H: SX permission */
25dfc3095cSChristophe Leroy #define _PAGE_ACCESSED	0x00020	/* S: Page referenced */
26dfc3095cSChristophe Leroy 
27dfc3095cSChristophe Leroy #define _PAGE_ENDIAN	0x00040	/* H: E bit */
28dfc3095cSChristophe Leroy #define _PAGE_GUARDED	0x00080	/* H: G bit */
29dfc3095cSChristophe Leroy #define _PAGE_COHERENT	0x00100	/* H: M bit */
30dfc3095cSChristophe Leroy #define _PAGE_NO_CACHE	0x00200	/* H: I bit */
31dfc3095cSChristophe Leroy #define _PAGE_WRITETHRU	0x00400	/* H: W bit */
32dfc3095cSChristophe Leroy #define _PAGE_SPECIAL	0x00800 /* S: Special page */
33dfc3095cSChristophe Leroy 
34dfc3095cSChristophe Leroy #define _PAGE_KERNEL_RO		0
35dfc3095cSChristophe Leroy #define _PAGE_KERNEL_ROX	_PAGE_EXEC
36dfc3095cSChristophe Leroy #define _PAGE_KERNEL_RW		(_PAGE_DIRTY | _PAGE_RW)
37dfc3095cSChristophe Leroy #define _PAGE_KERNEL_RWX	(_PAGE_DIRTY | _PAGE_RW | _PAGE_EXEC)
38dfc3095cSChristophe Leroy 
39dfc3095cSChristophe Leroy /* No page size encoding in the linux PTE */
40dfc3095cSChristophe Leroy #define _PAGE_PSIZE		0
41dfc3095cSChristophe Leroy 
42dfc3095cSChristophe Leroy #define _PMD_PRESENT	0
43dfc3095cSChristophe Leroy #define _PMD_PRESENT_MASK (PAGE_MASK)
44dfc3095cSChristophe Leroy #define _PMD_BAD	(~PAGE_MASK)
45dfc3095cSChristophe Leroy #define _PMD_USER	0
46dfc3095cSChristophe Leroy 
47dfc3095cSChristophe Leroy #define _PTE_NONE_MASK	0
48dfc3095cSChristophe Leroy 
49dfc3095cSChristophe Leroy #define PTE_WIMGE_SHIFT (6)
50dfc3095cSChristophe Leroy 
51dfc3095cSChristophe Leroy /*
52dfc3095cSChristophe Leroy  * We define 2 sets of base prot bits, one for basic pages (ie,
53dfc3095cSChristophe Leroy  * cacheable kernel and user pages) and one for non cacheable
54dfc3095cSChristophe Leroy  * pages. We always set _PAGE_COHERENT when SMP is enabled or
55dfc3095cSChristophe Leroy  * the processor might need it for DMA coherency.
56dfc3095cSChristophe Leroy  */
57dfc3095cSChristophe Leroy #define _PAGE_BASE_NC	(_PAGE_PRESENT | _PAGE_ACCESSED)
58dfc3095cSChristophe Leroy #if defined(CONFIG_SMP) || defined(CONFIG_PPC_E500MC)
59dfc3095cSChristophe Leroy #define _PAGE_BASE	(_PAGE_BASE_NC | _PAGE_COHERENT)
60dfc3095cSChristophe Leroy #else
61dfc3095cSChristophe Leroy #define _PAGE_BASE	(_PAGE_BASE_NC)
62dfc3095cSChristophe Leroy #endif
63dfc3095cSChristophe Leroy 
64dfc3095cSChristophe Leroy /* Permission masks used to generate the __P and __S table */
65dfc3095cSChristophe Leroy #define PAGE_NONE	__pgprot(_PAGE_BASE)
66dfc3095cSChristophe Leroy #define PAGE_SHARED	__pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW)
67dfc3095cSChristophe Leroy #define PAGE_SHARED_X	__pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_EXEC)
68dfc3095cSChristophe Leroy #define PAGE_COPY	__pgprot(_PAGE_BASE | _PAGE_USER)
69dfc3095cSChristophe Leroy #define PAGE_COPY_X	__pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
70dfc3095cSChristophe Leroy #define PAGE_READONLY	__pgprot(_PAGE_BASE | _PAGE_USER)
71dfc3095cSChristophe Leroy #define PAGE_READONLY_X	__pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
72dfc3095cSChristophe Leroy 
73dfc3095cSChristophe Leroy #endif /* __KERNEL__ */
74dfc3095cSChristophe Leroy #endif /*  _ASM_POWERPC_NOHASH_32_PTE_FSL_85xx_H */
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