Home
last modified time | relevance | path

Searched +full:de +full:- +full:assertion (Results 1 – 25 of 94) sorted by relevance

1234

/openbmc/u-boot/board/d-link/dns325/
H A Dkwbimage.cfg1 # SPDX-License-Identifier: GPL-2.0+
9 # Written-by: Prafulla Wadaskar <prafulla@marvell.com>
10 # Refer doc/README.kwbimage for more details about how-to configure
22 # Configure RGMII-0 interface pad voltage to 1.8V
27 # bit13-0: 0xc30, 3120 DDR2 clks refresh rate
28 # bit23-14: 0 required
31 # bit29-26: 0 required
32 # bit31-30: 0b01 required
35 # bit3-0: 0 required
39 # bit11-7: 0 required
[all …]
/openbmc/u-boot/board/buffalo/lsxl/
H A Dkwbimage-lschl.cfg1 # SPDX-License-Identifier: GPL-2.0+
5 # Refer doc/README.kwbimage for more details about how-to configure
15 # Configure RGMII-0/1 interface pad voltage to 1.8V
28 # bit13-0: 0x618, 1560 DDR2 clks refresh rate
29 # bit23-14: 0 required
32 # bit29-26: 0 required
33 # bit31-30: 0b01 required
37 # bit3-0: 0 required
41 # bit11-7: 0 required
45 # bit17-15: 0 required
[all …]
H A Dkwbimage-lsxhl.cfg1 # SPDX-License-Identifier: GPL-2.0+
5 # Refer doc/README.kwbimage for more details about how-to configure
15 # Configure RGMII-0/1 interface pad voltage to 1.8V
28 # bit13-0: 0x618, 1560 DDR2 clks refresh rate
29 # bit23-14: 0 required
32 # bit29-26: 0 required
33 # bit31-30: 0b01 required
37 # bit3-0: 0 required
41 # bit11-7: 0 required
45 # bit17-15: 0 required
[all …]
/openbmc/u-boot/board/keymile/km_arm/
H A Dkwbimage-memphis.cfg1 # SPDX-License-Identifier: GPL-2.0+
4 # Heiko Schocher, DENX Software Engineering, hs@denx.de.
8 # Refer doc/README.kwbimage for more details about how-to configure
16 # bit 3-0: MPPSel0 2, NF_IO[2]
17 # bit 7-4: MPPSel1 2, NF_IO[3]
18 # bit 12-8: MPPSel2 2, NF_IO[4]
19 # bit 15-12: MPPSel3 2, NF_IO[5]
20 # bit 19-16: MPPSel4 1, NF_IO[6]
21 # bit 23-20: MPPSel5 1, NF_IO[7]
22 # bit 27-24: MPPSel6 1, SYSRST_O
[all …]
H A Dkwbimage_128M16_1.cfg1 # SPDX-License-Identifier: GPL-2.0+
4 # Heiko Schocher, DENX Software Engineering, hs@denx.de.
12 # Refer doc/README.kwbimage for more details about how-to configure
20 # bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2])
21 # bit 7-4: 2, MPPSel1 SPI_SI (1=NF_IO[3])
22 # bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4])
23 # bit 15-12: 2, MPPSel3 SPI_SO (1=NF_IO[5])
24 # bit 19-16: 1, MPPSel4 NF_IO[6]
25 # bit 23-20: 1, MPPSel5 NF_IO[7]
26 # bit 27-24: 1, MPPSel6 SYSRST_O
[all …]
H A Dkwbimage_256M8_1.cfg1 # SPDX-License-Identifier: GPL-2.0+
7 # Refer doc/README.kwbimage for more details about how-to configure
10 # This configuration applies to COGE5 design (ARM-part)
11 # Two 8-Bit devices are connected on the 16-Bit bus on the same
12 # chip-select. The supported devices are
13 # MT47H256M8EB-3IT:C
14 # MT47H256M8EB-25EIT:C
20 # bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2])
21 # bit 7-4: 2, MPPSel1 SPI_MOSI (1=NF_IO[3])
22 # bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4])
[all …]
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dmvebu-devbus.txt9 - compatible: Armada 370/XP SoC are supported using the
10 "marvell,mvebu-devbus" compatible string.
13 "marvell,orion-devbus" compatible string.
15 - reg: A resource specifier for the register space.
20 - #address-cells: Must be set to 1
21 - #size-cells: Must be set to 1
22 - ranges: Must be set up to reflect the memory layout with four
23 integer values for each chip-select line in use:
28 - devbus,keep-config This property can optionally be used to keep
37 - devbus,turn-off-ps: Defines the time during which the controller does not
[all …]
/openbmc/linux/arch/sparc/include/asm/
H A Dbbc.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * bbc.h: Defines for BootBus Controller found on UltraSPARC-III
12 /* Register sizes are indicated by "B" (Byte, 1-byte),
13 * "H" (Half-word, 2 bytes), "W" (Word, 4 bytes) or
29 #define BBC_ES_DACT 0x14 /* [B] E* De-Assert Change Time */
30 #define BBC_ES_DABT 0x15 /* [B] E* De-Assert Bypass Time */
38 #define BBC_I2C_0_S1 0x2e /* [B] I2C ctrlr-0 reg S1 */
39 #define BBC_I2C_0_S0 0x2f /* [B] I2C ctrlr-0 regs S0,S0',S2,S3*/
40 #define BBC_I2C_1_S1 0x30 /* [B] I2C ctrlr-1 reg S1 */
41 #define BBC_I2C_1_S0 0x31 /* [B] I2C ctrlr-1 regs S0,S0',S2,S3*/
[all …]
/openbmc/linux/Documentation/devicetree/bindings/dma/
H A Dst,stm32-dma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/st,stm32-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The STM32 DMA is a general-purpose direct memory access controller capable of
13 described in the dma.txt file, using a four-cell specifier for each
19 -bit 9: Peripheral Increment Address
22 -bit 10: Memory Increment Address
25 -bit 15: Peripheral Increment Offset Size
27 0x1: offset size is fixed to 4 (32-bit alignment)
[all …]
/openbmc/phosphor-dbus-interfaces/yaml/xyz/openbmc_project/Logging/
H A DIPMI.interface.yaml6 type followed by type-specific information. The type-specific information
8 adding the SEL record), sensor number, event direction and event-specific
12 events it requires a generator ID (0x20 for BMC), sensor D-Bus path, event
13 direction (assertion or de-assertion), and event specific data. For OEM type
19 - name: IpmiSelAdd
23 - name: Message
27 - name: Path
31 - name: SELData
35 - name: Assert
38 An indicator if the SEL event is asserting or de-asserting.
[all …]
/openbmc/linux/drivers/spi/
H A Dspi-dw-core.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/dma-mapping.h>
17 #include <linux/spi/spi-mem.h>
21 #include "spi-dw.h"
64 snprintf(name, 32, "dw_spi%d", dws->host->bus_num); in dw_spi_debugfs_init()
65 dws->debugfs = debugfs_create_dir(name, NULL); in dw_spi_debugfs_init()
67 dws->regset.regs = dw_spi_dbgfs_regs; in dw_spi_debugfs_init()
68 dws->regset.nregs = ARRAY_SIZE(dw_spi_dbgfs_regs); in dw_spi_debugfs_init()
69 dws->regset.base = dws->regs; in dw_spi_debugfs_init()
70 debugfs_create_regset32("registers", 0400, dws->debugfs, &dws->regset); in dw_spi_debugfs_init()
[all …]
/openbmc/u-boot/board/technexion/pico-imx6ul/
H A Dpico-imx6ul.c1 // SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/mx6-pins.h>
15 #include <asm/mach-imx/iomux-v3.h>
73 * According to KSZ8081MNX-RNB manual: in board_eth_init()
75 * minimum of 500μs. The strap-in pin values are read and updated in board_eth_init()
76 * at the de-assertion of reset. in board_eth_init()
82 * According to KSZ8081MNX-RNB manual: in board_eth_init()
83 * After the de-assertion of reset, wait a minimum of 100μs before in board_eth_init()
96 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, in setup_fec()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/bus/
H A Dqcom,ebi2.txt4 external memory (such as NAND or other memory-mapped peripherals) whereas
18 Also CS1 and CS2 has -A and -B signals. Why they have that is unclear to me.
24 CS0 GPIO134 0x1a800000-0x1b000000 (8MB)
25 CS1 GPIO39 (A) / GPIO123 (B) 0x1b000000-0x1b800000 (8MB)
26 CS2 GPIO40 (A) / GPIO124 (B) 0x1b800000-0x1c000000 (8MB)
27 CS3 GPIO133 0x1d000000-0x25000000 (128 MB)
28 CS4 GPIO132 0x1c800000-0x1d000000 (8MB)
29 CS5 GPIO131 0x1c000000-0x1c800000 (8MB)
31 The APQ8060 Qualcomm Application Processor User Guide, 80-N7150-14 Rev. A,
51 - compatible: should be one of:
[all …]
H A Dnvidia,tegra20-gmi.txt10 - compatible : Should contain one of the following:
11 For Tegra20 must contain "nvidia,tegra20-gmi".
12 For Tegra30 must contain "nvidia,tegra30-gmi".
13 - reg: Should contain GMI controller registers location and length.
14 - clocks: Must contain an entry for each entry in clock-names.
15 - clock-names: Must include the following entries: "gmi"
16 - resets : Must contain an entry for each entry in reset-names.
17 - reset-names : Must include the following entries: "gmi"
18 - #address-cells: The number of cells used to represent physical base
20 - #size-cells: The number of cells used to represent the size of an address
[all …]
/openbmc/linux/Documentation/translations/sp_SP/process/
H A Dkernel-enforcement-statement.rst1 .. include:: ../disclaimer-sp.rst
3 :Original: :ref:`Documentation/process/kernel-enforcement-statement.rst <process_statement_kernel>`
8 Aplicación de la licencia en el kernel Linux
12 se utiliza nuestro software y cómo se aplica la licencia de nuestro software.
13 El cumplimiento de las obligaciones de intercambio recíproco de GPL-2.0 son
14 fundamentales en el largo plazo para la sostenibilidad de nuestro software
17 Aunque existe el derecho de hacer valer un copyright distinto en las
18 contribuciones hechas a nuestra comunidad, compartimos el interés de
20 de una manera que beneficia a nuestra comunidad y no tenga un indeseado
21 impacto negativo en la salud y crecimiento de nuestro ecosistema de software.
[all …]
/openbmc/linux/drivers/gpu/drm/bridge/
H A Dtc358762.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2020 Marek Vasut <marex@denx.de>
35 #define PPI_D0S_CLRSIPOCOUNT 0x0164 /* Assertion timer for Lane 0 */
36 #define PPI_D1S_CLRSIPOCOUNT 0x0168 /* Assertion timer for Lane 1 */
40 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */
52 #define LCDCTRL_DEPOL BIT(18) /* Polarity of DE signal */
84 int ret = ctx->error; in tc358762_clear_error()
86 ctx->error = 0; in tc358762_clear_error()
92 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); in tc358762_write()
96 if (ctx->error) in tc358762_write()
[all …]
H A Dtc358764.c1 // SPDX-License-Identifier: GPL-2.0
24 #define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
32 #define PPI_D0S_CLRSIPOCOUNT 0x0164 /* Assertion timer for Lane 0 */
33 #define PPI_D1S_CLRSIPOCOUNT 0x0168 /* Assertion timer for Lane 1 */
34 #define PPI_D2S_CLRSIPOCOUNT 0x016C /* Assertion timer for Lane 2 */
35 #define PPI_D3S_CLRSIPOCOUNT 0x0170 /* Assertion timer for Lane 3 */
39 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */
51 #define VP_CTRL_DEPOL BIT(18) /* Polarity of DE signal */
121 #define SYS_RST_I2CS BIT(0) /* Reset I2C-Slave controller */
122 #define SYS_RST_I2CM BIT(1) /* Reset I2C-Master controller */
[all …]
/openbmc/dbus-sensors/src/
H A DThresholds.cpp75 if (std::visit(VariantToStringVisitor(), labelFind->second) != in parseThresholdsFromConfig()
93 (std::visit(VariantToIntVisitor(), indexFind->second) != in parseThresholdsFromConfig()
105 std::visit(VariantToDoubleVisitor(), hysteresisFind->second); in parseThresholdsFromConfig()
119 std::visit(VariantToUnsignedIntVisitor(), severityFind->second); in parseThresholdsFromConfig()
122 std::visit(VariantToStringVisitor(), directionFind->second); in parseThresholdsFromConfig()
131 double val = std::visit(VariantToDoubleVisitor(), valueFind->second); in parseThresholdsFromConfig()
147 conn->async_method_call( in persistThreshold()
165 std::visit(VariantToStringVisitor(), labelFind->second); in persistThreshold()
182 VariantToUnsignedIntVisitor(), severityFind->second); in persistThreshold()
185 std::visit(VariantToStringVisitor(), directionFind->second); in persistThreshold()
[all …]
/openbmc/linux/drivers/bus/
H A Dqcom-ebi2.c1 // SPDX-License-Identifier: GPL-2.0-only
41 * Bits 31-28: RECOVERY recovery cycles (0 = 1, 1 = 2 etc) this is the time the
42 * memory continues to drive the data bus after OE is de-asserted.
45 * Bits 27-24: WR_HOLD write hold cycles, these are extra cycles inserted after
49 * Bits 23-16: WR_DELTA initial latency for write cycles inserted for the first
51 * Bits 15-8: RD_DELTA initial latency for read cycles inserted for the first
53 * Bits 7-4: WR_WAIT number of wait cycles for every write access, 0=1 cycle
55 * Bits 3-0: RD_WAIT number of wait cycles for every read access, 0=1 cycle
74 * Bits 31-28: ?
75 * Bits 27-24: RD_HOLD: the length in cycles of the first segment of a read
[all …]
/openbmc/linux/Documentation/process/
H A Dkernel-enforcement-statement.rst4 ----------------------------------
8 reciprocal sharing obligations of GPL-2.0 is critical to the long-term
20 Notwithstanding the termination provisions of the GPL-2.0, we agree that
22 following provisions of GPL-3.0 as additional permissions under our
23 license with respect to any non-defensive assertion of rights under the
48 Finally, once a non-compliance issue is resolved, we hope the user will feel
55 - Laura Abbott
56 - Bjorn Andersson (Linaro)
57 - Andrea Arcangeli
58 - Neil Armstrong
[all …]
/openbmc/linux/Documentation/scsi/
H A Dadvansys.rst1 .. SPDX-License-Identifier: GPL-2.0
8 RISC-based, Bus-Mastering, Fast (10 Mhz) and Ultra (20 Mhz) Narrow
9 (8-bit transfer) SCSI Host Adapters for the ISA, EISA, VL, and PCI
10 buses and RISC-based, Bus-Mastering, Ultra (20 Mhz) Wide (16-bit
21 - ABP-480 - Bus-Master CardBus (16 CDB)
24 - ABP510/5150 - Bus-Master ISA (240 CDB)
25 - ABP5140 - Bus-Master ISA PnP (16 CDB)
26 - ABP5142 - Bus-Master ISA PnP with floppy (16 CDB)
27 - ABP902/3902 - Bus-Master PCI (16 CDB)
28 - ABP3905 - Bus-Master PCI (16 CDB)
[all …]
/openbmc/linux/drivers/rtc/
H A Drtc-jz4740.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
9 #include <linux/clk-provider.h>
75 return readl(rtc->base + reg); in jz4740_rtc_reg_read()
82 return readl_poll_timeout(rtc->base + JZ_REG_RTC_CTRL, ctrl, in jz4740_rtc_wait_write_ready()
95 writel(JZ_RTC_WENR_MAGIC, rtc->base + JZ_REG_RTC_WENR); in jz4780_rtc_enable_write()
97 return readl_poll_timeout(rtc->base + JZ_REG_RTC_WENR, ctrl, in jz4780_rtc_enable_write()
106 if (rtc->type >= ID_JZ4760) in jz4740_rtc_reg_write()
111 writel(val, rtc->base + reg); in jz4740_rtc_reg_write()
123 spin_lock_irqsave(&rtc->lock, flags); in jz4740_rtc_ctrl_set_bits()
[all …]
/openbmc/u-boot/drivers/pci/
H A Dpcie_imx.c1 // SPDX-License-Identifier: GPL-2.0
3 * Freescale i.MX6 PCI Express Root-Complex driver
5 * Copyright (C) 2013 Marek Vasut <marex@denx.de>
8 * pci-imx6.c: Sean Cross <xobs@kosagi.com>
9 * pcie-designware.c: Jingoo Han <jg1.han@samsung.com>
42 /* PCIe Port Logic registers (memory-mapped) */
63 /* PHY registers (not memory-mapped) */
115 return -ETIMEDOUT; in pcie_phy_poll_ack()
143 /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
200 /* wait for ack de-assertion */ in pcie_phy_write()
[all …]
/openbmc/u-boot/board/toradex/apalis_t30/
H A Dapalis_t30.c1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2014-2018
10 #include <asm/arch-tegra/ap.h>
11 #include <asm/arch-tegra/tegra.h>
17 #include "../common/tdx-common.h"
19 #include "pinmux-config-apalis_t30.h"
45 (gd->ram_size == 0x40000000) ? 1 : 2); in checkboard()
69 /* Initialize any non-default pad configs (APB_MISC_GP regs) */ in pinmux_init()
129 if (index == 2) { /* I210 Gigabit Ethernet Controller (On-module) */ in tegra_pcie_board_port_reset()
157 * Guaranteed Until 900 us After PEX_PERST# De-assertion in tegra_pcie_board_port_reset()
/openbmc/u-boot/board/toradex/apalis-tk1/
H A Dapalis-tk1.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2016-2018 Toradex, Inc.
8 #include <asm/arch-tegra/ap.h>
17 #include "../common/tdx-common.h"
18 #include "pinmux-config-apalis-tk1.h"
76 return -EINVAL; in as3722_sd_enable()
94 return -EINVAL; in as3722_ldo_enable()
98 ldo -= 8; in as3722_ldo_enable()
150 if (index == 1) { /* I210 Gigabit Ethernet Controller (On-module) */ in tegra_pcie_board_port_reset()
235 * Until 900 us After PEX_PERST# De-assertion in tegra_pcie_board_port_reset()

1234