1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
2335a1275SLinus Walleij /*
3335a1275SLinus Walleij * Qualcomm External Bus Interface 2 (EBI2) driver
4335a1275SLinus Walleij * an older version of the Qualcomm Parallel Interface Controller (QPIC)
5335a1275SLinus Walleij *
6335a1275SLinus Walleij * Copyright (C) 2016 Linaro Ltd.
7335a1275SLinus Walleij *
8335a1275SLinus Walleij * Author: Linus Walleij <linus.walleij@linaro.org>
9335a1275SLinus Walleij *
10335a1275SLinus Walleij * See the device tree bindings for this block for more details on the
11335a1275SLinus Walleij * hardware.
12335a1275SLinus Walleij */
13335a1275SLinus Walleij
14335a1275SLinus Walleij #include <linux/module.h>
15335a1275SLinus Walleij #include <linux/clk.h>
16335a1275SLinus Walleij #include <linux/err.h>
17335a1275SLinus Walleij #include <linux/io.h>
18335a1275SLinus Walleij #include <linux/of.h>
19335a1275SLinus Walleij #include <linux/of_platform.h>
20335a1275SLinus Walleij #include <linux/init.h>
21335a1275SLinus Walleij #include <linux/slab.h>
22335a1275SLinus Walleij #include <linux/platform_device.h>
23335a1275SLinus Walleij #include <linux/bitops.h>
24335a1275SLinus Walleij
25335a1275SLinus Walleij /*
26335a1275SLinus Walleij * CS0, CS1, CS4 and CS5 are two bits wide, CS2 and CS3 are one bit.
27335a1275SLinus Walleij */
28335a1275SLinus Walleij #define EBI2_CS0_ENABLE_MASK BIT(0)|BIT(1)
29335a1275SLinus Walleij #define EBI2_CS1_ENABLE_MASK BIT(2)|BIT(3)
30335a1275SLinus Walleij #define EBI2_CS2_ENABLE_MASK BIT(4)
31335a1275SLinus Walleij #define EBI2_CS3_ENABLE_MASK BIT(5)
32335a1275SLinus Walleij #define EBI2_CS4_ENABLE_MASK BIT(6)|BIT(7)
33335a1275SLinus Walleij #define EBI2_CS5_ENABLE_MASK BIT(8)|BIT(9)
34335a1275SLinus Walleij #define EBI2_CSN_MASK GENMASK(9, 0)
35335a1275SLinus Walleij
36335a1275SLinus Walleij #define EBI2_XMEM_CFG 0x0000 /* Power management etc */
37335a1275SLinus Walleij
38335a1275SLinus Walleij /*
39335a1275SLinus Walleij * SLOW CSn CFG
40335a1275SLinus Walleij *
41335a1275SLinus Walleij * Bits 31-28: RECOVERY recovery cycles (0 = 1, 1 = 2 etc) this is the time the
42335a1275SLinus Walleij * memory continues to drive the data bus after OE is de-asserted.
43335a1275SLinus Walleij * Inserted when reading one CS and switching to another CS or read
44335a1275SLinus Walleij * followed by write on the same CS. Valid values 0 thru 15.
45335a1275SLinus Walleij * Bits 27-24: WR_HOLD write hold cycles, these are extra cycles inserted after
46335a1275SLinus Walleij * every write minimum 1. The data out is driven from the time WE is
47335a1275SLinus Walleij * asserted until CS is asserted. With a hold of 1, the CS stays
48335a1275SLinus Walleij * active for 1 extra cycle etc. Valid values 0 thru 15.
49335a1275SLinus Walleij * Bits 23-16: WR_DELTA initial latency for write cycles inserted for the first
50335a1275SLinus Walleij * write to a page or burst memory
51335a1275SLinus Walleij * Bits 15-8: RD_DELTA initial latency for read cycles inserted for the first
52335a1275SLinus Walleij * read to a page or burst memory
53335a1275SLinus Walleij * Bits 7-4: WR_WAIT number of wait cycles for every write access, 0=1 cycle
54335a1275SLinus Walleij * so 1 thru 16 cycles.
55335a1275SLinus Walleij * Bits 3-0: RD_WAIT number of wait cycles for every read access, 0=1 cycle
56335a1275SLinus Walleij * so 1 thru 16 cycles.
57335a1275SLinus Walleij */
58335a1275SLinus Walleij #define EBI2_XMEM_CS0_SLOW_CFG 0x0008
59335a1275SLinus Walleij #define EBI2_XMEM_CS1_SLOW_CFG 0x000C
60335a1275SLinus Walleij #define EBI2_XMEM_CS2_SLOW_CFG 0x0010
61335a1275SLinus Walleij #define EBI2_XMEM_CS3_SLOW_CFG 0x0014
62335a1275SLinus Walleij #define EBI2_XMEM_CS4_SLOW_CFG 0x0018
63335a1275SLinus Walleij #define EBI2_XMEM_CS5_SLOW_CFG 0x001C
64335a1275SLinus Walleij
65335a1275SLinus Walleij #define EBI2_XMEM_RECOVERY_SHIFT 28
66335a1275SLinus Walleij #define EBI2_XMEM_WR_HOLD_SHIFT 24
67335a1275SLinus Walleij #define EBI2_XMEM_WR_DELTA_SHIFT 16
68335a1275SLinus Walleij #define EBI2_XMEM_RD_DELTA_SHIFT 8
69335a1275SLinus Walleij #define EBI2_XMEM_WR_WAIT_SHIFT 4
70335a1275SLinus Walleij #define EBI2_XMEM_RD_WAIT_SHIFT 0
71335a1275SLinus Walleij
72335a1275SLinus Walleij /*
73335a1275SLinus Walleij * FAST CSn CFG
74335a1275SLinus Walleij * Bits 31-28: ?
75335a1275SLinus Walleij * Bits 27-24: RD_HOLD: the length in cycles of the first segment of a read
76335a1275SLinus Walleij * transfer. For a single read trandfer this will be the time
77335a1275SLinus Walleij * from CS assertion to OE assertion.
78335a1275SLinus Walleij * Bits 18-24: ?
79335a1275SLinus Walleij * Bits 17-16: ADV_OE_RECOVERY, the number of cycles elapsed before an OE
80335a1275SLinus Walleij * assertion, with respect to the cycle where ADV is asserted.
81335a1275SLinus Walleij * 2 means 2 cycles between ADV and OE. Values 0, 1, 2 or 3.
82335a1275SLinus Walleij * Bits 5: ADDR_HOLD_ENA, The address is held for an extra cycle to meet
83335a1275SLinus Walleij * hold time requirements with ADV assertion.
84335a1275SLinus Walleij *
85335a1275SLinus Walleij * The manual mentions "write precharge cycles" and "precharge cycles".
86335a1275SLinus Walleij * We have not been able to figure out which bit fields these correspond to
87335a1275SLinus Walleij * in the hardware, or what valid values exist. The current hypothesis is that
88335a1275SLinus Walleij * this is something just used on the FAST chip selects. There is also a "byte
89335a1275SLinus Walleij * device enable" flag somewhere for 8bit memories.
90335a1275SLinus Walleij */
91335a1275SLinus Walleij #define EBI2_XMEM_CS0_FAST_CFG 0x0028
92335a1275SLinus Walleij #define EBI2_XMEM_CS1_FAST_CFG 0x002C
93335a1275SLinus Walleij #define EBI2_XMEM_CS2_FAST_CFG 0x0030
94335a1275SLinus Walleij #define EBI2_XMEM_CS3_FAST_CFG 0x0034
95335a1275SLinus Walleij #define EBI2_XMEM_CS4_FAST_CFG 0x0038
96335a1275SLinus Walleij #define EBI2_XMEM_CS5_FAST_CFG 0x003C
97335a1275SLinus Walleij
98335a1275SLinus Walleij #define EBI2_XMEM_RD_HOLD_SHIFT 24
99335a1275SLinus Walleij #define EBI2_XMEM_ADV_OE_RECOVERY_SHIFT 16
100335a1275SLinus Walleij #define EBI2_XMEM_ADDR_HOLD_ENA_SHIFT 5
101335a1275SLinus Walleij
102335a1275SLinus Walleij /**
103335a1275SLinus Walleij * struct cs_data - struct with info on a chipselect setting
104335a1275SLinus Walleij * @enable_mask: mask to enable the chipselect in the EBI2 config
105*ee704ebfSLee Jones * @slow_cfg: offset to XMEMC slow CS config
106*ee704ebfSLee Jones * @fast_cfg: offset to XMEMC fast CS config
107335a1275SLinus Walleij */
108335a1275SLinus Walleij struct cs_data {
109335a1275SLinus Walleij u32 enable_mask;
110335a1275SLinus Walleij u16 slow_cfg;
111335a1275SLinus Walleij u16 fast_cfg;
112335a1275SLinus Walleij };
113335a1275SLinus Walleij
114335a1275SLinus Walleij static const struct cs_data cs_info[] = {
115335a1275SLinus Walleij {
116335a1275SLinus Walleij /* CS0 */
117335a1275SLinus Walleij .enable_mask = EBI2_CS0_ENABLE_MASK,
118335a1275SLinus Walleij .slow_cfg = EBI2_XMEM_CS0_SLOW_CFG,
119335a1275SLinus Walleij .fast_cfg = EBI2_XMEM_CS0_FAST_CFG,
120335a1275SLinus Walleij },
121335a1275SLinus Walleij {
122335a1275SLinus Walleij /* CS1 */
123335a1275SLinus Walleij .enable_mask = EBI2_CS1_ENABLE_MASK,
124335a1275SLinus Walleij .slow_cfg = EBI2_XMEM_CS1_SLOW_CFG,
125335a1275SLinus Walleij .fast_cfg = EBI2_XMEM_CS1_FAST_CFG,
126335a1275SLinus Walleij },
127335a1275SLinus Walleij {
128335a1275SLinus Walleij /* CS2 */
129335a1275SLinus Walleij .enable_mask = EBI2_CS2_ENABLE_MASK,
130335a1275SLinus Walleij .slow_cfg = EBI2_XMEM_CS2_SLOW_CFG,
131335a1275SLinus Walleij .fast_cfg = EBI2_XMEM_CS2_FAST_CFG,
132335a1275SLinus Walleij },
133335a1275SLinus Walleij {
134335a1275SLinus Walleij /* CS3 */
135335a1275SLinus Walleij .enable_mask = EBI2_CS3_ENABLE_MASK,
136335a1275SLinus Walleij .slow_cfg = EBI2_XMEM_CS3_SLOW_CFG,
137335a1275SLinus Walleij .fast_cfg = EBI2_XMEM_CS3_FAST_CFG,
138335a1275SLinus Walleij },
139335a1275SLinus Walleij {
140335a1275SLinus Walleij /* CS4 */
141335a1275SLinus Walleij .enable_mask = EBI2_CS4_ENABLE_MASK,
142335a1275SLinus Walleij .slow_cfg = EBI2_XMEM_CS4_SLOW_CFG,
143335a1275SLinus Walleij .fast_cfg = EBI2_XMEM_CS4_FAST_CFG,
144335a1275SLinus Walleij },
145335a1275SLinus Walleij {
146335a1275SLinus Walleij /* CS5 */
147335a1275SLinus Walleij .enable_mask = EBI2_CS5_ENABLE_MASK,
148335a1275SLinus Walleij .slow_cfg = EBI2_XMEM_CS5_SLOW_CFG,
149335a1275SLinus Walleij .fast_cfg = EBI2_XMEM_CS5_FAST_CFG,
150335a1275SLinus Walleij },
151335a1275SLinus Walleij };
152335a1275SLinus Walleij
153335a1275SLinus Walleij /**
154335a1275SLinus Walleij * struct ebi2_xmem_prop - describes an XMEM config property
155335a1275SLinus Walleij * @prop: the device tree binding name
156335a1275SLinus Walleij * @max: maximum value for the property
157335a1275SLinus Walleij * @slowreg: true if this property is in the SLOW CS config register
158335a1275SLinus Walleij * else it is assumed to be in the FAST config register
159335a1275SLinus Walleij * @shift: the bit field start in the SLOW or FAST register for this
160335a1275SLinus Walleij * property
161335a1275SLinus Walleij */
162335a1275SLinus Walleij struct ebi2_xmem_prop {
163335a1275SLinus Walleij const char *prop;
164335a1275SLinus Walleij u32 max;
165335a1275SLinus Walleij bool slowreg;
166335a1275SLinus Walleij u16 shift;
167335a1275SLinus Walleij };
168335a1275SLinus Walleij
169335a1275SLinus Walleij static const struct ebi2_xmem_prop xmem_props[] = {
170335a1275SLinus Walleij {
171335a1275SLinus Walleij .prop = "qcom,xmem-recovery-cycles",
172335a1275SLinus Walleij .max = 15,
173335a1275SLinus Walleij .slowreg = true,
174335a1275SLinus Walleij .shift = EBI2_XMEM_RECOVERY_SHIFT,
175335a1275SLinus Walleij },
176335a1275SLinus Walleij {
177335a1275SLinus Walleij .prop = "qcom,xmem-write-hold-cycles",
178335a1275SLinus Walleij .max = 15,
179335a1275SLinus Walleij .slowreg = true,
180335a1275SLinus Walleij .shift = EBI2_XMEM_WR_HOLD_SHIFT,
181335a1275SLinus Walleij },
182335a1275SLinus Walleij {
183335a1275SLinus Walleij .prop = "qcom,xmem-write-delta-cycles",
184335a1275SLinus Walleij .max = 255,
185335a1275SLinus Walleij .slowreg = true,
186335a1275SLinus Walleij .shift = EBI2_XMEM_WR_DELTA_SHIFT,
187335a1275SLinus Walleij },
188335a1275SLinus Walleij {
189335a1275SLinus Walleij .prop = "qcom,xmem-read-delta-cycles",
190335a1275SLinus Walleij .max = 255,
191335a1275SLinus Walleij .slowreg = true,
192335a1275SLinus Walleij .shift = EBI2_XMEM_RD_DELTA_SHIFT,
193335a1275SLinus Walleij },
194335a1275SLinus Walleij {
195335a1275SLinus Walleij .prop = "qcom,xmem-write-wait-cycles",
196335a1275SLinus Walleij .max = 15,
197335a1275SLinus Walleij .slowreg = true,
198335a1275SLinus Walleij .shift = EBI2_XMEM_WR_WAIT_SHIFT,
199335a1275SLinus Walleij },
200335a1275SLinus Walleij {
201335a1275SLinus Walleij .prop = "qcom,xmem-read-wait-cycles",
202335a1275SLinus Walleij .max = 15,
203335a1275SLinus Walleij .slowreg = true,
204335a1275SLinus Walleij .shift = EBI2_XMEM_RD_WAIT_SHIFT,
205335a1275SLinus Walleij },
206335a1275SLinus Walleij {
207335a1275SLinus Walleij .prop = "qcom,xmem-address-hold-enable",
208335a1275SLinus Walleij .max = 1, /* boolean prop */
209335a1275SLinus Walleij .slowreg = false,
210335a1275SLinus Walleij .shift = EBI2_XMEM_ADDR_HOLD_ENA_SHIFT,
211335a1275SLinus Walleij },
212335a1275SLinus Walleij {
213335a1275SLinus Walleij .prop = "qcom,xmem-adv-to-oe-recovery-cycles",
214335a1275SLinus Walleij .max = 3,
215335a1275SLinus Walleij .slowreg = false,
216335a1275SLinus Walleij .shift = EBI2_XMEM_ADV_OE_RECOVERY_SHIFT,
217335a1275SLinus Walleij },
218335a1275SLinus Walleij {
219335a1275SLinus Walleij .prop = "qcom,xmem-read-hold-cycles",
220335a1275SLinus Walleij .max = 15,
221335a1275SLinus Walleij .slowreg = false,
222335a1275SLinus Walleij .shift = EBI2_XMEM_RD_HOLD_SHIFT,
223335a1275SLinus Walleij },
224335a1275SLinus Walleij };
225335a1275SLinus Walleij
qcom_ebi2_setup_chipselect(struct device_node * np,struct device * dev,void __iomem * ebi2_base,void __iomem * ebi2_xmem,u32 csindex)226335a1275SLinus Walleij static void qcom_ebi2_setup_chipselect(struct device_node *np,
227335a1275SLinus Walleij struct device *dev,
228335a1275SLinus Walleij void __iomem *ebi2_base,
229335a1275SLinus Walleij void __iomem *ebi2_xmem,
230335a1275SLinus Walleij u32 csindex)
231335a1275SLinus Walleij {
232335a1275SLinus Walleij const struct cs_data *csd;
233335a1275SLinus Walleij u32 slowcfg, fastcfg;
234335a1275SLinus Walleij u32 val;
235335a1275SLinus Walleij int ret;
236335a1275SLinus Walleij int i;
237335a1275SLinus Walleij
238335a1275SLinus Walleij csd = &cs_info[csindex];
239335a1275SLinus Walleij val = readl(ebi2_base);
240335a1275SLinus Walleij val |= csd->enable_mask;
241335a1275SLinus Walleij writel(val, ebi2_base);
242335a1275SLinus Walleij dev_dbg(dev, "enabled CS%u\n", csindex);
243335a1275SLinus Walleij
244335a1275SLinus Walleij /* Next set up the XMEMC */
245335a1275SLinus Walleij slowcfg = 0;
246335a1275SLinus Walleij fastcfg = 0;
247335a1275SLinus Walleij
248335a1275SLinus Walleij for (i = 0; i < ARRAY_SIZE(xmem_props); i++) {
249335a1275SLinus Walleij const struct ebi2_xmem_prop *xp = &xmem_props[i];
250335a1275SLinus Walleij
251335a1275SLinus Walleij /* All are regular u32 values */
252335a1275SLinus Walleij ret = of_property_read_u32(np, xp->prop, &val);
253335a1275SLinus Walleij if (ret) {
254335a1275SLinus Walleij dev_dbg(dev, "could not read %s for CS%d\n",
255335a1275SLinus Walleij xp->prop, csindex);
256335a1275SLinus Walleij continue;
257335a1275SLinus Walleij }
258335a1275SLinus Walleij
259335a1275SLinus Walleij /* First check boolean props */
260335a1275SLinus Walleij if (xp->max == 1 && val) {
261335a1275SLinus Walleij if (xp->slowreg)
262335a1275SLinus Walleij slowcfg |= BIT(xp->shift);
263335a1275SLinus Walleij else
264335a1275SLinus Walleij fastcfg |= BIT(xp->shift);
265335a1275SLinus Walleij dev_dbg(dev, "set %s flag\n", xp->prop);
266335a1275SLinus Walleij continue;
267335a1275SLinus Walleij }
268335a1275SLinus Walleij
269335a1275SLinus Walleij /* We're dealing with an u32 */
270335a1275SLinus Walleij if (val > xp->max) {
271335a1275SLinus Walleij dev_err(dev,
272335a1275SLinus Walleij "too high value for %s: %u, capped at %u\n",
273335a1275SLinus Walleij xp->prop, val, xp->max);
274335a1275SLinus Walleij val = xp->max;
275335a1275SLinus Walleij }
276335a1275SLinus Walleij if (xp->slowreg)
277335a1275SLinus Walleij slowcfg |= (val << xp->shift);
278335a1275SLinus Walleij else
279335a1275SLinus Walleij fastcfg |= (val << xp->shift);
280335a1275SLinus Walleij dev_dbg(dev, "set %s to %u\n", xp->prop, val);
281335a1275SLinus Walleij }
282335a1275SLinus Walleij
283335a1275SLinus Walleij dev_info(dev, "CS%u: SLOW CFG 0x%08x, FAST CFG 0x%08x\n",
284335a1275SLinus Walleij csindex, slowcfg, fastcfg);
285335a1275SLinus Walleij
286335a1275SLinus Walleij if (slowcfg)
287335a1275SLinus Walleij writel(slowcfg, ebi2_xmem + csd->slow_cfg);
288335a1275SLinus Walleij if (fastcfg)
289335a1275SLinus Walleij writel(fastcfg, ebi2_xmem + csd->fast_cfg);
290335a1275SLinus Walleij }
291335a1275SLinus Walleij
qcom_ebi2_probe(struct platform_device * pdev)292335a1275SLinus Walleij static int qcom_ebi2_probe(struct platform_device *pdev)
293335a1275SLinus Walleij {
294335a1275SLinus Walleij struct device_node *np = pdev->dev.of_node;
295335a1275SLinus Walleij struct device_node *child;
296335a1275SLinus Walleij struct device *dev = &pdev->dev;
297335a1275SLinus Walleij struct resource *res;
298335a1275SLinus Walleij void __iomem *ebi2_base;
299335a1275SLinus Walleij void __iomem *ebi2_xmem;
300335a1275SLinus Walleij struct clk *ebi2xclk;
301335a1275SLinus Walleij struct clk *ebi2clk;
302335a1275SLinus Walleij bool have_children = false;
303335a1275SLinus Walleij u32 val;
304335a1275SLinus Walleij int ret;
305335a1275SLinus Walleij
306335a1275SLinus Walleij ebi2xclk = devm_clk_get(dev, "ebi2x");
307335a1275SLinus Walleij if (IS_ERR(ebi2xclk))
308335a1275SLinus Walleij return PTR_ERR(ebi2xclk);
309335a1275SLinus Walleij
310335a1275SLinus Walleij ret = clk_prepare_enable(ebi2xclk);
311335a1275SLinus Walleij if (ret) {
312335a1275SLinus Walleij dev_err(dev, "could not enable EBI2X clk (%d)\n", ret);
313335a1275SLinus Walleij return ret;
314335a1275SLinus Walleij }
315335a1275SLinus Walleij
316335a1275SLinus Walleij ebi2clk = devm_clk_get(dev, "ebi2");
317335a1275SLinus Walleij if (IS_ERR(ebi2clk)) {
318335a1275SLinus Walleij ret = PTR_ERR(ebi2clk);
319335a1275SLinus Walleij goto err_disable_2x_clk;
320335a1275SLinus Walleij }
321335a1275SLinus Walleij
322335a1275SLinus Walleij ret = clk_prepare_enable(ebi2clk);
323335a1275SLinus Walleij if (ret) {
324335a1275SLinus Walleij dev_err(dev, "could not enable EBI2 clk\n");
325335a1275SLinus Walleij goto err_disable_2x_clk;
326335a1275SLinus Walleij }
327335a1275SLinus Walleij
328335a1275SLinus Walleij res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
329335a1275SLinus Walleij ebi2_base = devm_ioremap_resource(dev, res);
330335a1275SLinus Walleij if (IS_ERR(ebi2_base)) {
331335a1275SLinus Walleij ret = PTR_ERR(ebi2_base);
332335a1275SLinus Walleij goto err_disable_clk;
333335a1275SLinus Walleij }
334335a1275SLinus Walleij
335335a1275SLinus Walleij res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
336335a1275SLinus Walleij ebi2_xmem = devm_ioremap_resource(dev, res);
337335a1275SLinus Walleij if (IS_ERR(ebi2_xmem)) {
338335a1275SLinus Walleij ret = PTR_ERR(ebi2_xmem);
339335a1275SLinus Walleij goto err_disable_clk;
340335a1275SLinus Walleij }
341335a1275SLinus Walleij
342335a1275SLinus Walleij /* Allegedly this turns the power save mode off */
343335a1275SLinus Walleij writel(0UL, ebi2_xmem + EBI2_XMEM_CFG);
344335a1275SLinus Walleij
345335a1275SLinus Walleij /* Disable all chipselects */
346335a1275SLinus Walleij val = readl(ebi2_base);
347335a1275SLinus Walleij val &= ~EBI2_CSN_MASK;
348335a1275SLinus Walleij writel(val, ebi2_base);
349335a1275SLinus Walleij
350335a1275SLinus Walleij /* Walk over the child nodes and see what chipselects we use */
351335a1275SLinus Walleij for_each_available_child_of_node(np, child) {
352335a1275SLinus Walleij u32 csindex;
353335a1275SLinus Walleij
354335a1275SLinus Walleij /* Figure out the chipselect */
355335a1275SLinus Walleij ret = of_property_read_u32(child, "reg", &csindex);
356ac6ad7c2SPan Bian if (ret) {
357ac6ad7c2SPan Bian of_node_put(child);
358335a1275SLinus Walleij return ret;
359ac6ad7c2SPan Bian }
360335a1275SLinus Walleij
361335a1275SLinus Walleij if (csindex > 5) {
362335a1275SLinus Walleij dev_err(dev,
363335a1275SLinus Walleij "invalid chipselect %u, we only support 0-5\n",
364335a1275SLinus Walleij csindex);
365335a1275SLinus Walleij continue;
366335a1275SLinus Walleij }
367335a1275SLinus Walleij
368335a1275SLinus Walleij qcom_ebi2_setup_chipselect(child,
369335a1275SLinus Walleij dev,
370335a1275SLinus Walleij ebi2_base,
371335a1275SLinus Walleij ebi2_xmem,
372335a1275SLinus Walleij csindex);
373335a1275SLinus Walleij
374335a1275SLinus Walleij /* We have at least one child */
375335a1275SLinus Walleij have_children = true;
376335a1275SLinus Walleij }
377335a1275SLinus Walleij
378335a1275SLinus Walleij if (have_children)
379335a1275SLinus Walleij return of_platform_default_populate(np, NULL, dev);
380335a1275SLinus Walleij return 0;
381335a1275SLinus Walleij
382335a1275SLinus Walleij err_disable_clk:
383335a1275SLinus Walleij clk_disable_unprepare(ebi2clk);
384335a1275SLinus Walleij err_disable_2x_clk:
385335a1275SLinus Walleij clk_disable_unprepare(ebi2xclk);
386335a1275SLinus Walleij
387335a1275SLinus Walleij return ret;
388335a1275SLinus Walleij }
389335a1275SLinus Walleij
390335a1275SLinus Walleij static const struct of_device_id qcom_ebi2_of_match[] = {
391335a1275SLinus Walleij { .compatible = "qcom,msm8660-ebi2", },
392335a1275SLinus Walleij { .compatible = "qcom,apq8060-ebi2", },
393335a1275SLinus Walleij { }
394335a1275SLinus Walleij };
395335a1275SLinus Walleij
396335a1275SLinus Walleij static struct platform_driver qcom_ebi2_driver = {
397335a1275SLinus Walleij .probe = qcom_ebi2_probe,
398335a1275SLinus Walleij .driver = {
399335a1275SLinus Walleij .name = "qcom-ebi2",
400335a1275SLinus Walleij .of_match_table = qcom_ebi2_of_match,
401335a1275SLinus Walleij },
402335a1275SLinus Walleij };
403335a1275SLinus Walleij module_platform_driver(qcom_ebi2_driver);
404335a1275SLinus Walleij MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
405335a1275SLinus Walleij MODULE_DESCRIPTION("Qualcomm EBI2 driver");
406