| /openbmc/u-boot/board/d-link/dns325/ |
| H A D | kwbimage.cfg | 1 # SPDX-License-Identifier: GPL-2.0+
9 # Written-by: Prafulla Wadaskar <prafulla@marvell.com>
10 # Refer doc/README.kwbimage for more details about how-to configure
22 # Configure RGMII-0 interface pad voltage to 1.8V
27 # bit13-0: 0xc30, 3120 DDR2 clks refresh rate
28 # bit23-14: 0 required
31 # bit29-26: 0 required
32 # bit31-30: 0b01 required
35 # bit3-0: 0 required
39 # bit11-7: 0 required
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| /openbmc/u-boot/board/buffalo/lsxl/ |
| H A D | kwbimage-lschl.cfg | 1 # SPDX-License-Identifier: GPL-2.0+
5 # Refer doc/README.kwbimage for more details about how-to configure
15 # Configure RGMII-0/1 interface pad voltage to 1.8V
28 # bit13-0: 0x618, 1560 DDR2 clks refresh rate
29 # bit23-14: 0 required
32 # bit29-26: 0 required
33 # bit31-30: 0b01 required
37 # bit3-0: 0 required
41 # bit11-7: 0 required
45 # bit17-15: 0 required
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| H A D | kwbimage-lsxhl.cfg | 1 # SPDX-License-Identifier: GPL-2.0+
5 # Refer doc/README.kwbimage for more details about how-to configure
15 # Configure RGMII-0/1 interface pad voltage to 1.8V
28 # bit13-0: 0x618, 1560 DDR2 clks refresh rate
29 # bit23-14: 0 required
32 # bit29-26: 0 required
33 # bit31-30: 0b01 required
37 # bit3-0: 0 required
41 # bit11-7: 0 required
45 # bit17-15: 0 required
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| /openbmc/linux/include/linux/ |
| H A D | kvm_irqfd.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
16 * level triggered interrupts. The interrupt is asserted on eventfd
18 * interrupt is de-asserted and userspace is notified through the
19 * resamplefd. All resamplers on the same gsi are de-asserted
27 * RCU list modified under kvm->irqfds.resampler_lock
32 * Entry in list of kvm->irqfd.resampler_list. Use for sharing
34 * RCU list modified under kvm->irqfds.resampler_lock
40 /* Used for MSI fast-path */
46 /* Used for level IRQ fast-path */
49 /* The resampler used by this irqfd (resampler-only) */
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| /openbmc/u-boot/board/keymile/km_arm/ |
| H A D | kwbimage-memphis.cfg | 1 # SPDX-License-Identifier: GPL-2.0+
4 # Heiko Schocher, DENX Software Engineering, hs@denx.de.
8 # Refer doc/README.kwbimage for more details about how-to configure
16 # bit 3-0: MPPSel0 2, NF_IO[2]
17 # bit 7-4: MPPSel1 2, NF_IO[3]
18 # bit 12-8: MPPSel2 2, NF_IO[4]
19 # bit 15-12: MPPSel3 2, NF_IO[5]
20 # bit 19-16: MPPSel4 1, NF_IO[6]
21 # bit 23-20: MPPSel5 1, NF_IO[7]
22 # bit 27-24: MPPSel6 1, SYSRST_O
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| H A D | kwbimage_128M16_1.cfg | 1 # SPDX-License-Identifier: GPL-2.0+
4 # Heiko Schocher, DENX Software Engineering, hs@denx.de.
12 # Refer doc/README.kwbimage for more details about how-to configure
20 # bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2])
21 # bit 7-4: 2, MPPSel1 SPI_SI (1=NF_IO[3])
22 # bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4])
23 # bit 15-12: 2, MPPSel3 SPI_SO (1=NF_IO[5])
24 # bit 19-16: 1, MPPSel4 NF_IO[6]
25 # bit 23-20: 1, MPPSel5 NF_IO[7]
26 # bit 27-24: 1, MPPSel6 SYSRST_O
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| H A D | kwbimage_256M8_1.cfg | 1 # SPDX-License-Identifier: GPL-2.0+
7 # Refer doc/README.kwbimage for more details about how-to configure
10 # This configuration applies to COGE5 design (ARM-part)
11 # Two 8-Bit devices are connected on the 16-Bit bus on the same
12 # chip-select. The supported devices are
13 # MT47H256M8EB-3IT:C
14 # MT47H256M8EB-25EIT:C
20 # bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2])
21 # bit 7-4: 2, MPPSel1 SPI_MOSI (1=NF_IO[3])
22 # bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4])
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| /openbmc/linux/Documentation/devicetree/bindings/mmc/ |
| H A D | mmc-pwrseq-simple.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-pwrseq-simple.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
19 const: mmc-pwrseq-simple
21 reset-gpios:
26 contains a list of GPIO specifiers. The reset GPIOs are asserted
28 They will be de-asserted right after the power has been provided to the
33 description: Handle for the entry in clock-names.
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| /openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ |
| H A D | mvebu-devbus.txt | 9 - compatible: Armada 370/XP SoC are supported using the
10 "marvell,mvebu-devbus" compatible string.
13 "marvell,orion-devbus" compatible string.
15 - reg: A resource specifier for the register space.
20 - #address-cells: Must be set to 1
21 - #size-cells: Must be set to 1
22 - ranges: Must be set up to reflect the memory layout with four
23 integer values for each chip-select line in use:
28 - devbus,keep-config This property can optionally be used to keep
37 - devbus,turn-off-ps: Defines the time during which the controller does not
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| /openbmc/dbus-sensors/src/ |
| H A D | Thresholds.cpp | 75 if (std::visit(VariantToStringVisitor(), labelFind->second) != in parseThresholdsFromConfig()
93 (std::visit(VariantToIntVisitor(), indexFind->second) != in parseThresholdsFromConfig()
105 std::visit(VariantToDoubleVisitor(), hysteresisFind->second); in parseThresholdsFromConfig()
119 std::visit(VariantToUnsignedIntVisitor(), severityFind->second); in parseThresholdsFromConfig()
122 std::visit(VariantToStringVisitor(), directionFind->second); in parseThresholdsFromConfig()
131 double val = std::visit(VariantToDoubleVisitor(), valueFind->second); in parseThresholdsFromConfig()
147 conn->async_method_call( in persistThreshold()
165 std::visit(VariantToStringVisitor(), labelFind->second); in persistThreshold()
182 VariantToUnsignedIntVisitor(), severityFind->second); in persistThreshold()
185 std::visit(VariantToStringVisitor(), directionFind->second); in persistThreshold()
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| /openbmc/phosphor-dbus-interfaces/yaml/xyz/openbmc_project/Led/ |
| H A D | Group.interface.yaml | 4 - name: Asserted
7 Whether or not the group is currently asserted. To assert a group, set
8 to True. To de-assert a group, set to False.
11 - name: identifying
17 - xyz.openbmc_project.Inventory.Item
18 - name: fault_identifying
24 - xyz.openbmc_project.Inventory.Item
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| H A D | README.md | 68 …https://github.com/openbmc/phosphor-dbus-interfaces/blob/master/yaml/xyz/openbmc_project/Led/Group…
70 There is only one property called **asserted** defined on groups and when set to
73 are un-done.
75 - Henceforth, the term **asserted** would mean writing boolean **true** onto
76 `assert` property of the group. Term **de-assert** would mean writing
84 Using the yaml definition above, a user can just set the `asserted` property to
91 groups namely; **bmc_booted** and **power_on**. Those would be asserted post
116 …https://github.com/openbmc/phosphor-dbus-interfaces/blob/master/yaml/xyz/openbmc_project/Led/Physi…
124 the `asserted` property to `true` would result in these actions in `id_front`
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| /openbmc/linux/Documentation/devicetree/bindings/spi/ |
| H A D | spi-peripheral-props.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral-specific properties for a SPI bus.
11 be common properties like spi-max-frequency, spi-cpha, etc. or they could be
13 need to be defined in the peripheral node because they are per-peripheral and
19 - Mark Brown <broonie@kernel.org>
27 - minimum: 0
32 spi-cs-high:
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| H A D | cdns,qspi-nor-peripheral-props.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/cdns,qspi-nor-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral-specific properties for the Cadence QSPI controller.
10 See spi-peripheral-props.yaml for more info.
13 - Vaishnav Achath <vaishnav.a@ti.com>
16 # cdns,qspi-nor.yaml
17 cdns,read-delay:
22 cdns,tshsl-ns:
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| /openbmc/linux/arch/sparc/include/asm/ |
| H A D | bbc.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * bbc.h: Defines for BootBus Controller found on UltraSPARC-III
12 /* Register sizes are indicated by "B" (Byte, 1-byte),
13 * "H" (Half-word, 2 bytes), "W" (Word, 4 bytes) or
29 #define BBC_ES_DACT 0x14 /* [B] E* De-Assert Change Time */
30 #define BBC_ES_DABT 0x15 /* [B] E* De-Assert Bypass Time */
38 #define BBC_I2C_0_S1 0x2e /* [B] I2C ctrlr-0 reg S1 */
39 #define BBC_I2C_0_S0 0x2f /* [B] I2C ctrlr-0 regs S0,S0',S2,S3*/
40 #define BBC_I2C_1_S1 0x30 /* [B] I2C ctrlr-1 reg S1 */
41 #define BBC_I2C_1_S0 0x31 /* [B] I2C ctrlr-1 regs S0,S0',S2,S3*/
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| /openbmc/linux/drivers/video/backlight/ |
| H A D | lms283gf05.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * lms283gf05.c -- support for Samsung LMS283GF05 LCD
95 gpiod_set_value(gpiod, 0); /* De-asserted */ in lms283gf05_reset()
97 gpiod_set_value(gpiod, 1); /* Asserted */ in lms283gf05_reset()
99 gpiod_set_value(gpiod, 0); /* De-asserted */ in lms283gf05_reset()
127 struct spi_device *spi = st->spi; in lms283gf05_power_set()
130 if (st->reset) in lms283gf05_power_set()
131 lms283gf05_reset(st->reset); in lms283gf05_power_set()
135 if (st->reset) in lms283gf05_power_set()
136 gpiod_set_value(st->reset, 1); /* Asserted */ in lms283gf05_power_set()
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| /openbmc/linux/arch/arm/mach-omap2/ |
| H A D | prminst44xx.c | 1 // SPDX-License-Identifier: GPL-2.0-only
18 #include "prcm-common.h"
23 #include "prm-regbits-44xx.h"
34 * omap_prm_base_init - Populates the prm partitions
75 /* Read-modify-write a register in PRM. Caller must lock */
90 * omap4_prminst_is_hardreset_asserted - read the HW reset line state of
95 * Returns 1 if the (sub)module hardreset line is currently asserted,
96 * 0 if the (sub)module hardreset line is not currently asserted, or
97 * -EINVAL upon parameter error.
112 * omap4_prminst_assert_hardreset - assert the HW reset line of a submodule
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| H A D | prm2xxx_3xxx.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2010-2011 Texas Instruments, Inc.
18 #include "prm-regbits-24xx.h"
22 * omap2_prm_is_hardreset_asserted - read the HW reset line state of
29 * Returns 1 if the (sub)module hardreset line is currently asserted,
30 * 0 if the (sub)module hardreset line is not currently asserted, or
31 * -EINVAL if called while running on a non-OMAP2/3 chip.
40 * omap2_prm_assert_hardreset - assert the HW reset line of a submodule
47 * reset line to be asserted / deasserted in order to fully enable the
48 * IP. These modules may have multiple hard-reset lines that reset
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| /openbmc/linux/Documentation/devicetree/bindings/bus/ |
| H A D | nvidia,tegra20-gmi.txt | 10 - compatible : Should contain one of the following:
11 For Tegra20 must contain "nvidia,tegra20-gmi".
12 For Tegra30 must contain "nvidia,tegra30-gmi".
13 - reg: Should contain GMI controller registers location and length.
14 - clocks: Must contain an entry for each entry in clock-names.
15 - clock-names: Must include the following entries: "gmi"
16 - resets : Must contain an entry for each entry in reset-names.
17 - reset-names : Must include the following entries: "gmi"
18 - #address-cells: The number of cells used to represent physical base
20 - #size-cells: The number of cells used to represent the size of an address
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| /openbmc/linux/drivers/clk/baikal-t1/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 bool "Baikal-T1 Clocks Control Unit interface"
7 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
13 to select Baikal-T1 CCU PLLs and Dividers drivers.
18 bool "Baikal-T1 CCU PLLs support"
22 Enable this to support the PLLs embedded into the Baikal-T1 SoC
31 bool "Baikal-T1 CCU Dividers support"
36 between AXI-bus and system devices coming from CCU PLLs of Baikal-T1
42 bool "Baikal-T1 CCU Resets support"
48 AXI-bus and some subsystems reset. These are mainly the
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| /openbmc/linux/include/sound/ |
| H A D | cs4271.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
17 * line is de-asserted. That also means that clocks cannot be changed
19 * a complete re-initialization of all registers.
21 * One (undocumented) workaround is to assert and de-assert the PDN bit
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| /openbmc/u-boot/doc/device-tree-bindings/spi/ |
| H A D | spi-cadence.txt | 2 --------------------------------------------
5 - compatible : should be "cdns,qspi-nor"
6 - reg : 1.Physical base address and size of SPI registers map.
8 - clocks : Clock phandles (see clock bindings for details).
9 - cdns,fifo-depth : Size of the data FIFO in words.
10 - cdns,fifo-width : Bus width of the data FIFO in bytes.
11 - cdns,trigger-address : 32-bit indirect AHB trigger address.
12 - cdns,is-decoded-cs : Flag to indicate whether decoder is used or not.
13 - status : enable in requried dts.
16 --------------------------
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| /openbmc/phosphor-pid-control/dbus/ |
| H A D | dbuspassive.cpp | 8 * http://www.apache.org/licenses/LICENSE-2.0
58 if (info->readPath.empty()) in createDbusPassive()
64 path = info->readPath; in createDbusPassive()
72 std::string service = helper->getService(sensorintf, path); in createDbusPassive()
74 helper->getProperties(service, path, &settings); in createDbusPassive()
75 failed = helper->thresholdsAsserted(service, path); in createDbusPassive()
83 if (info->ignoreDbusMinMax) in createDbusPassive()
89 settings.unavailableAsFailed = info->unavailableAsFailed; in createDbusPassive()
147 const std::set<std::string>& failures = redundancy->getFailed(); in getFailed()
158 * power-state-not-matching, should not trigger the failSafe mode. For in getFailed()
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| /openbmc/linux/Documentation/devicetree/bindings/sound/ |
| H A D | cs4271.txt | 7 - compatible: "cirrus,cs4271"
10 Documentation/devicetree/bindings/spi/spi-bus.txt
14 - reg: the i2c address
19 - reset-gpio: a GPIO spec to define which pin is connected to the chip's
21 - cirrus,amuteb-eq-bmutec: When given, the Codec's AMUTEB=BMUTEC flag
23 - cirrus,enable-soft-reset:
25 line is de-asserted. That also means that clocks cannot be changed
27 a complete re-initialization of all registers.
29 One (undocumented) workaround is to assert and de-assert the PDN bit
36 - vd-supply: Digital power
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| /openbmc/linux/drivers/fpga/ |
| H A D | ice40-spi.c | 1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/fpga/fpga-mgr.h>
34 struct ice40_fpga_priv *priv = mgr->priv; in ice40_fpga_ops_state()
36 return gpiod_get_value(priv->cdone) ? FPGA_MGR_STATE_OPERATING : in ice40_fpga_ops_state()
44 struct ice40_fpga_priv *priv = mgr->priv; in ice40_fpga_ops_write_init()
45 struct spi_device *dev = priv->dev; in ice40_fpga_ops_write_init()
62 if ((info->flags & FPGA_MGR_PARTIAL_RECONFIG)) { in ice40_fpga_ops_write_init()
63 dev_err(&dev->dev, in ice40_fpga_ops_write_init()
65 return -ENOTSUPP; in ice40_fpga_ops_write_init()
69 spi_bus_lock(dev->master); in ice40_fpga_ops_write_init()
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