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/openbmc/qemu/include/hw/timer/
H A Dnpcm7xx_timer.h23 /* Each Timer Module (TIM) instance holds five 25 MHz timers. */
35 #define NPCM7XX_WATCHDOG_RESET_GPIO_OUT "npcm7xx-clk-watchdog-reset-gpio-out"
40 * struct NPCM7xxBaseTimer - Basic functionality that both regular timer and
53 * struct NPCM7xxTimer - Individual timer state.
54 * @ctrl: The timer module that owns this timer.
61 NPCM7xxTimerCtrlState *ctrl; member
71 * struct NPCM7xxWatchdogTimer - The watchdog timer state.
72 * @ctrl: The timer module that owns this timer.
79 NPCM7xxTimerCtrlState *ctrl; member
89 * struct NPCM7xxTimerCtrlState - Timer Module device state.
[all …]
/openbmc/phosphor-webui/app/common/components/
H A Dfile-upload.js4 const template = `<div class="file-upload">
7 class="file-upload-btn btn btn-secondary"
8 ng-if="!$ctrl.file"
15 file=$ctrl.file
16 class="file-upload-input"
17 accept="{{$ctrl.fileType}}"/>
18 <div class="file-upload-container"
19 ng-class="{
20 'file-upload-error' : $ctrl.fileStatus ==='error'}"
21 ng-if="$ctrl.file">
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H A Dalert-banner.js32 <div class="alert-banner"
33 ng-class="{
34 'alert-banner--info': $ctrl.type === 'info',
35 'alert-banner--warn': $ctrl.type === 'warn',
36 'alert-banner--error': $ctrl.type === 'error',
37 'alert-banner--success': $ctrl.type === 'success'}">
38 <status-icon
39 ng-if="$ctrl.type !== 'info'"
40 status="{{$ctrl.status}}"
41 class="status-icon">
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H A Dstatus-icon.js8 * The <status-icon> component expects a 'status' attribute
16 const template = `<icon ng-if="$ctrl.status === 'on'"
17 file="icon-on.svg"
18 aria-hidden="true"
19 class="status-icon">
21 <icon ng-if="$ctrl.status === 'off'"
22 file="icon-off.svg"
23 aria-hidden="true"
24 class="status-icon">
26 <icon ng-if="$ctrl.status === 'warn'"
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/openbmc/phosphor-webui/app/configuration/components/
H A Dcard.js14 <div class="card-component">
16 ng-class="{
17 'card__header--success' : $ctrl.status === 'success',
18 'card__header--error' : $ctrl.status === 'error' }">
19 <p class="card__header__label inline">{{$ctrl.headerLabel}}</p>
20 <p class="card__header__value inline">{{$ctrl.headerValue}}</p>
23 ng-if="$ctrl.body">
25 <div class="column small-6">
27 {{$ctrl.bmcStatus || 'n/a'}}
29 <div class="column small-6">
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/openbmc/u-boot/arch/m68k/include/asm/
H A Dimmap_520x.h1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
46 /* System Controller Module */
50 u32 pacra; /* 0x20 Peripheral Access Ctrl A */
51 u32 pacrb; /* 0x24 Peripheral Access Ctrl B */
52 u32 pacrc; /* 0x28 Peripheral Access Ctrl C */
53 u32 pacrd; /* 0x2C Peripheral Access Ctrl D */
55 u32 pacre; /* 0x40 Peripheral Access Ctrl E */
56 u32 pacrf; /* 0x44 Peripheral Access Ctrl F */
[all …]
H A Dimmap_5301x.h1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
63 /* System Controller Module */
67 u32 pacra; /* 0x20 Peripheral Access Ctrl A */
68 u32 pacrb; /* 0x24 Peripheral Access Ctrl B */
69 u32 pacrc; /* 0x28 Peripheral Access Ctrl C */
70 u32 pacrd; /* 0x2C Peripheral Access Ctrl D */
72 u32 pacre; /* 0x40 Peripheral Access Ctrl E */
73 u32 pacrf; /* 0x44 Peripheral Access Ctrl F */
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/openbmc/phosphor-webui/app/common/components/table/
H A Dtable-checkbox.js44 <div class="bmc-table__checkbox-container">
45 <label class="bmc-table__checkbox"
46 ng-class="{
47 'checked': $ctrl.ngModel,
48 'indeterminate': $ctrl.indeterminate
51 class="bmc-table__checkbox-input"
52 ng-model="$ctrl.ngModel"
53 ng-change="$ctrl.onSelectChange()"
54 aria-label="Select row"/>
55 <span class="screen-reader-offscreen">Select row</span>
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H A Dtable-toolbar.js9 * The <table-toolbar> component expects an 'actions' attribute
15 * {type: 'Edit', label: 'Edit', file: 'icon-edit.svg'},
16 * {type: 'Delete', label: 'Edit', file: 'icon-trashcan.svg'}
73 <div class="bmc-table__toolbar" ng-if="$ctrl.active">
74 <p class="toolbar__selection-count">{{$ctrl.selectionCount}} selected</p>
75 <div class="toolbar__batch-actions" ng-show="$ctrl.actions.length > 0">
77 class="btn btn-tertiary"
79 aria-label="{{action.label}}"
80 ng-repeat="action in $ctrl.actions"
81 ng-click="$ctrl.onClick(action.type)">
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H A Dtable-actions.js9 * The <table-actions> component expects an 'actions' attribute
15 * {type: 'Edit', enabled: true, file: 'icon-edit.svg'},
16 * {type: 'Delete', enabled: false, file: 'icon-trashcan.svg'}
70 class="btn btn-tertiary"
72 aria-label="{{action.type}}"
73 ng-repeat="action in $ctrl.actions track by $index"
74 ng-disabled="!action.enabled"
75 ng-click="$ctrl.onClick(action.type)">
76 <icon ng-if="action.file" ng-file="{{action.file}}"></icon>
77 <span ng-if="!action.file">{{action.type}}</span>
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/openbmc/qemu/hw/ipack/
H A Dtpci200.c18 #include "qemu/module.h"
56 #define IP_N_FROM_REG(REG) ((REG) / 2 - 1)
68 uint8_t ctrl[N_MODULES]; member
111 PCIDevice *pcidev = PCI_DEVICE(BUS(bus)->parent); in tpci200_set_irq()
113 unsigned ip_n = ip->slot; in tpci200_set_irq()
114 uint16_t prev_status = dev->status; in tpci200_set_irq()
116 assert(ip->slot >= 0 && ip->slot < N_MODULES); in tpci200_set_irq()
120 if (!(dev->ctrl[ip_n] & CTRL_INT(intno))) { in tpci200_set_irq()
126 dev->status |= STATUS_INT(ip_n, intno); in tpci200_set_irq()
128 dev->status &= ~STATUS_INT(ip_n, intno); in tpci200_set_irq()
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/openbmc/u-boot/drivers/spi/
H A Dfsl_dspi.c1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2000-2003
6 * Copyright (C) 2004-2009, 2015 Freescale Semiconductor, Inc.
7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
42 /* CTAR register pre-configure value */
51 /* CTAR register pre-configure mask */
61 * struct fsl_dspi_platdata - platform data for Freescale DSPI
76 * struct fsl_dspi_priv - private data for Freescale DSPI
136 mcr_val = dspi_read32(priv->flags, &priv->regs->mcr); in dspi_halt()
143 dspi_write32(priv->flags, &priv->regs->mcr, mcr_val); in dspi_halt()
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/openbmc/u-boot/arch/m68k/include/asm/coldfire/
H A Dflexcan.h1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
16 u8 ctrl; /* 0x01 Control */ member
22 u16 ctrl; /* 0x00 Control/Status */
30 /* MSGBUF CTRL */
47 /* MSGBUF CTRL */
63 /* FlexCan module */
65 u32 mcr; /* 0x00 Module Configuration */
66 u32 ctrl; /* 0x04 Control */ member
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/openbmc/u-boot/board/compulab/cl-som-am57x/
H A Deth.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Ethernet specific code for CompuLab CL-SOM-AM57x module
59 * cl_som_am57x_efuse_read_mac_addr() - read Ethernet port MAC address.
69 mac_lo = readl((*ctrl)->control_core_mac_id_1_lo); in cl_som_am57x_efuse_read_mac_addr()
70 mac_hi = readl((*ctrl)->control_core_mac_id_1_hi); in cl_som_am57x_efuse_read_mac_addr()
72 mac_lo = readl((*ctrl)->control_core_mac_id_0_lo); in cl_som_am57x_efuse_read_mac_addr()
73 mac_hi = readl((*ctrl)->control_core_mac_id_0_hi); in cl_som_am57x_efuse_read_mac_addr()
85 * cl_som_am57x_handle_mac_address() - set MAC address in the U-Boot
89 * @env_name: U-Boot environment name.
108 return -1; in cl_som_am57x_handle_mac_address()
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/openbmc/u-boot/board/theobroma-systems/puma_rk3399/
H A Dpuma-rk3399.c1 // SPDX-License-Identifier: GPL-2.0+
14 #include <dm/uclass-internal.h>
24 #include <u-boot/sha256.h>
46 debug("%s: trying to force a power-on reset\n", __func__); in rk3399_force_power_on_reset()
54 if (gpio_request_by_name_nodev(node, "sysreset-gpio", 0, in rk3399_force_power_on_reset()
56 debug("%s: could not find a /config/sysreset-gpio\n", __func__); in rk3399_force_power_on_reset()
71 * This may cause issues during boot-up for some configurations of in spl_board_init()
75 * a power-on reset and (if not) issue an overtemp-reset to reset in spl_board_init()
76 * the entire module. in spl_board_init()
79 * that could generate a software reset (e.g. U-Boot's sysreset in spl_board_init()
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/openbmc/qemu/hw/misc/
H A Darm_l2x0.c4 * Copyright (c) 2010-2012 Calxeda
22 #include "hw/qdev-properties.h"
26 #include "qemu/module.h"
29 /* L2C-310 r3p2 */
40 uint32_t ctrl; member
53 VMSTATE_UINT32(ctrl, L2x0State),
78 cache_data = (s->aux_ctrl & (7 << 17)) >> 15; in l2x0_priv_read()
79 cache_data |= (s->aux_ctrl & (1 << 16)) >> 16; in l2x0_priv_read()
80 return s->cache_type |= (cache_data << 18) | (cache_data << 6); in l2x0_priv_read()
82 return s->ctrl; in l2x0_priv_read()
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/openbmc/qemu/hw/timer/
H A Dcmsdk-apb-timer.c12 /* This is a model of the "APB timer" which is part of the Cortex-M
13 * System Design Kit (CMSDK) and documented in the Cortex-M System
15 * https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit
27 * interrupt (as there is no further 1->0 transition).
32 #include "qemu/module.h"
38 #include "hw/qdev-clock.h"
39 #include "hw/timer/cmsdk-apb-timer.h"
42 REG32(CTRL, 0)
43 FIELD(CTRL, EN, 0, 1)
44 FIELD(CTRL, SELEXTEN, 1, 1)
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/openbmc/u-boot/arch/arm/include/asm/arch-am33xx/
H A Dhardware_am43xx.h1 /* SPDX-License-Identifier: GPL-2.0+ */
7 * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
13 /* Module base addresses */
27 /* Control Module Base Address */
45 /* USB CTRL Base Address */
/openbmc/phosphor-webui/app/common/directives/
H A Dpassword-confirmation.js8 * Also include attribute 'first-password' with value set to first password
11 * <input password-confirmation first-password="ctrl.password"
15 angular.module('app.common.directives')
/openbmc/qemu/hw/char/
H A Dmax78000_uart.c6 * SPDX-License-Identifier: GPL-2.0-or-later
12 #include "hw/qdev-properties.h"
13 #include "hw/qdev-properties-system.h"
15 #include "qemu/module.h"
23 if (!(s->ctrl & UART_BCLKEN)) { in max78000_uart_can_receive()
26 return fifo8_num_free(&s->rx_fifo); in max78000_uart_can_receive()
33 interrupt_level = s->int_fl & s->int_en; in max78000_update_irq()
34 qemu_set_irq(s->irq, interrupt_level); in max78000_update_irq()
41 assert(size <= fifo8_num_free(&s->rx_fifo)); in max78000_uart_receive()
43 fifo8_push_all(&s->rx_fifo, buf, size); in max78000_uart_receive()
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H A Dcmsdk-apb-uart.c12 /* This is a model of the "APB UART" which is part of the Cortex-M
13 * System Design Kit (CMSDK) and documented in the Cortex-M System
15 * https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit
20 #include "qemu/module.h"
26 #include "chardev/char-fe.h"
27 #include "chardev/char-serial.h"
28 #include "hw/char/cmsdk-apb-uart.h"
30 #include "hw/qdev-properties-system.h"
38 REG32(CTRL, 8)
39 FIELD(CTRL, TX_EN, 0, 1)
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/openbmc/qemu/hw/s390x/
H A D3270-ccw.c2 * Emulated ccw-attached 3270 implementation
9 * your option) any later version. See the COPYING file in the top-level
15 #include "qemu/module.h"
17 #include "hw/s390x/css-bridge.h"
18 #include "hw/qdev-properties.h"
19 #include "hw/s390x/3270-ccw.h"
28 if (!ccw->cda) { in handle_payload_3270_read()
29 return -EFAULT; in handle_payload_3270_read()
32 len = ck->read_payload_3270(dev); in handle_payload_3270_read()
36 ccw_dev->sch->curr_status.scsw.count = ccw->count - len; in handle_payload_3270_read()
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/openbmc/qemu/hw/mem/
H A Dcxl_type3.c7 * COPYING file in the top-level directory.
9 * SPDX-License-Identifier: GPL-v2-only
15 #include "qemu/error-report.h"
16 #include "qapi/qapi-commands-cxl.h"
17 #include "hw/mem/memory-device.h"
18 #include "hw/mem/pc-dimm.h"
20 #include "hw/qdev-properties.h"
21 #include "hw/qdev-properties-system.h"
24 #include "qemu/module.h"
28 #include "qemu/guest-random.h"
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/openbmc/qemu/hw/dma/
H A Dxlnx-zynq-devcfg.c28 #include "hw/dma/xlnx-zynq-devcfg.h"
34 #include "qemu/module.h"
50 REG32(CTRL, 0x00)
51 FIELD(CTRL, FORCE_RST, 31, 1) /* Not supported, wr ignored */
52 FIELD(CTRL, PCAP_PR, 27, 1) /* Forced to 0 on bad unlock */
53 FIELD(CTRL, PCAP_MODE, 26, 1)
54 FIELD(CTRL, MULTIBOOT_EN, 24, 1)
55 FIELD(CTRL, USER_MODE, 15, 1)
56 FIELD(CTRL, PCFG_AES_FUSE, 12, 1)
57 FIELD(CTRL, PCFG_AES_EN, 9, 3)
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/openbmc/u-boot/arch/arm/mach-socfpga/
H A Dsystem_manager_s10.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
26 * Populate the value for SYSMGR.FPGAINTF.MODULE based on pinmux setting.
27 * The value is not wrote to SYSMGR.FPGAINTF.MODULE but
35 if (readl(&sysmgr_regs->nandusefpga) == SYSMGR_FPGAINTF_USEFPGA) in populate_sysmgr_fpgaintf_module()
37 if (readl(&sysmgr_regs->sdmmcusefpga) == SYSMGR_FPGAINTF_USEFPGA) in populate_sysmgr_fpgaintf_module()
39 if (readl(&sysmgr_regs->spim0usefpga) == SYSMGR_FPGAINTF_USEFPGA) in populate_sysmgr_fpgaintf_module()
41 if (readl(&sysmgr_regs->spim1usefpga) == SYSMGR_FPGAINTF_USEFPGA) in populate_sysmgr_fpgaintf_module()
43 writel(handoff_val, &sysmgr_regs->fpgaintf_en_2); in populate_sysmgr_fpgaintf_module()
46 if (readl(&sysmgr_regs->rgmii0usefpga) == SYSMGR_FPGAINTF_USEFPGA) in populate_sysmgr_fpgaintf_module()
[all …]

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