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/openbmc/linux/drivers/accel/habanalabs/common/
H A Dcommand_submission.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2021 HabanaLabs, Ltd.
23 * enum hl_cs_wait_status - cs wait status
24 * @CS_WAIT_STATUS_BUSY: cs was not completed yet
25 * @CS_WAIT_STATUS_COMPLETED: cs completed
26 * @CS_WAIT_STATUS_GONE: cs completed but fence is already gone
47 * CS outcome store supports the following operations: in hl_push_cs_outcome()
48 * push outcome - store a recent CS outcome in the store in hl_push_cs_outcome()
49 * pop outcome - retrieve a SPECIFIC (by seq) CS outcome from the store in hl_push_cs_outcome()
51 * It has a pre-allocated amount of nodes, each node stores in hl_push_cs_outcome()
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H A Dhw_queue.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2019 HabanaLabs, Ltd.
13 * hl_queue_add_ptr - add to pi or ci and checks if it wraps around
23 ptr &= ((HL_QUEUE_LENGTH << 1) - 1); in hl_hw_queue_add_ptr()
28 return atomic_read(ci) & ((queue_len << 1) - 1); in queue_ci_get()
33 int delta = (q->pi - queue_ci_get(&q->ci, queue_len)); in queue_free_slots()
36 return (queue_len - delta); in queue_free_slots()
38 return (abs(delta) - queue_len); in queue_free_slots()
41 void hl_hw_queue_update_ci(struct hl_cs *cs) in hl_hw_queue_update_ci() argument
43 struct hl_device *hdev = cs->ctx->hdev; in hl_hw_queue_update_ci()
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/openbmc/linux/drivers/gpu/drm/i915/gt/
H A Dintel_migrate.c1 // SPDX-License-Identifier: MIT
33 GEM_BUG_ON(engine->class != COPY_ENGINE_CLASS); in engine_supports_migration()
48 vm->insert_page(vm, 0, d->offset, in xehpsdv_toggle_pdes()
49 i915_gem_get_pat_index(vm->i915, I915_CACHE_NONE), in xehpsdv_toggle_pdes()
51 GEM_BUG_ON(!pt->is_compact); in xehpsdv_toggle_pdes()
52 d->offset += SZ_2M; in xehpsdv_toggle_pdes()
68 vm->insert_page(vm, px_dma(pt), d->offset, in xehpsdv_insert_pte()
69 i915_gem_get_pat_index(vm->i915, I915_CACHE_NONE), in xehpsdv_insert_pte()
71 d->offset += SZ_64K; in xehpsdv_insert_pte()
80 vm->insert_page(vm, px_dma(pt), d->offset, in insert_pte()
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H A Dselftest_engine_cs.c1 // SPDX-License-Identifier: GPL-2.0
21 return *a - *b; in cmp_u32()
29 atomic_inc(&gt->rps.num_waiters); in perf_begin()
30 queue_work(gt->i915->unordered_wq, &gt->rps.work); in perf_begin()
31 flush_work(&gt->rps.work); in perf_begin()
36 atomic_dec(&gt->rps.num_waiters); in perf_end()
39 return igt_flush_test(gt->i915); in perf_end()
44 struct drm_i915_private *i915 = engine->i915; in timestamp_reg()
47 return RING_TIMESTAMP_UDW(engine->mmio_base); in timestamp_reg()
49 return RING_TIMESTAMP(engine->mmio_base); in timestamp_reg()
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H A Dselftest_execlists.c1 // SPDX-License-Identifier: MIT
24 #define CS_GPR(engine, n) ((engine)->mmio_base + 0x600 + (n) * 4)
47 tasklet_hi_schedule(&engine->sched_engine->tasklet); in wait_for_submit()
58 if (!READ_ONCE(engine->execlists.pending[0]) && is_active(rq)) in wait_for_submit()
62 return -ETIME; in wait_for_submit()
78 if (READ_ONCE(engine->execlists.pending[0])) in wait_for_reset()
84 if (READ_ONCE(rq->fence.error)) in wait_for_reset()
88 if (rq->fence.error != -EIO) { in wait_for_reset()
90 engine->name, in wait_for_reset()
91 rq->fence.context, in wait_for_reset()
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H A Dselftest_timeline.c1 // SPDX-License-Identifier: MIT
3 * Copyright © 2017-2018 Intel Corporation
29 struct drm_i915_gem_object *obj = tl->hwsp_ggtt->obj; in hwsp_page()
32 return sg_page(obj->mm.pages->sgl); in hwsp_page()
39 return (address + offset_in_page(tl->hwsp_offset)) / TIMELINE_SEQNO_BYTES; in hwsp_cacheline()
49 err = i915_gem_object_lock(tl->hwsp_ggtt->obj, &ww); in selftest_tl_pin()
53 if (err == -EDEADLK) { in selftest_tl_pin()
81 tl = xchg(&state->history[idx], tl); in __mock_hwsp_record()
83 radix_tree_delete(&state->cachelines, hwsp_cacheline(tl)); in __mock_hwsp_record()
96 while (count--) { in __mock_hwsp_timeline()
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H A Dselftest_rc6.c1 // SPDX-License-Identifier: MIT
34 struct intel_rc6 *rc6 = &gt->rc6; in live_rc6_manual()
47 if (!rc6->enabled) in live_rc6_manual()
51 if (IS_VALLEYVIEW(gt->i915) || IS_CHERRYVIEW(gt->i915)) in live_rc6_manual()
54 has_power = librapl_supported(gt->i915); in live_rc6_manual()
55 wakeref = intel_runtime_pm_get(gt->uncore->rpm); in live_rc6_manual()
66 rc0_power = librapl_energy_uJ() - rc0_power; in live_rc6_manual()
69 if ((res[1] - res[0]) >> 10) { in live_rc6_manual()
71 (res[1] - res[0]) >> 10); in live_rc6_manual()
72 err = -EINVAL; in live_rc6_manual()
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H A Dselftest_ring_submission.c1 // SPDX-License-Identifier: MIT
13 u32 *cs; in create_wally() local
16 obj = i915_gem_object_create_internal(engine->i915, 4096); in create_wally()
20 vma = i915_vma_instance(obj, engine->gt->vm, NULL); in create_wally()
38 cs = i915_gem_object_pin_map_unlocked(obj, I915_MAP_WC); in create_wally()
39 if (IS_ERR(cs)) { in create_wally()
41 return ERR_CAST(cs); in create_wally()
44 if (GRAPHICS_VER(engine->i915) >= 6) { in create_wally()
45 *cs++ = MI_STORE_DWORD_IMM_GEN4; in create_wally()
46 *cs++ = 0; in create_wally()
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/openbmc/linux/drivers/gpu/drm/i915/selftests/
H A Di915_perf.c2 * SPDX-License-Identifier: MIT
17 #define TEST_OA_CONFIG_UUID "12345678-1234-1234-1234-1234567890ab"
26 return -ENOMEM; in alloc_empty_config()
28 oa_config->perf = perf; in alloc_empty_config()
29 kref_init(&oa_config->ref); in alloc_empty_config()
31 strscpy(oa_config->uuid, TEST_OA_CONFIG_UUID, sizeof(oa_config->uuid)); in alloc_empty_config()
33 mutex_lock(&perf->metrics_lock); in alloc_empty_config()
35 oa_config->id = idr_alloc(&perf->metrics_idr, oa_config, 2, 0, GFP_KERNEL); in alloc_empty_config()
36 if (oa_config->id < 0) { in alloc_empty_config()
37 mutex_unlock(&perf->metrics_lock); in alloc_empty_config()
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H A Di915_request.c20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
75 request = mock_request(rcs0(i915)->kernel_context, HZ / 10); in igt_add_request()
77 return -ENOMEM; in igt_add_request()
89 int err = -EINVAL; in igt_wait_request()
93 request = mock_request(rcs0(i915)->kernel_context, T); in igt_wait_request()
95 return -ENOMEM; in igt_wait_request()
99 if (i915_request_wait(request, 0, 0) != -ETIME) { in igt_wait_request()
104 if (i915_request_wait(request, 0, T) != -ETIME) { in igt_wait_request()
116 if (i915_request_wait(request, 0, 0) != -ETIME) { in igt_wait_request()
126 if (i915_request_wait(request, 0, T / 2) != -ETIME) { in igt_wait_request()
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/openbmc/linux/fs/fuse/
H A Ddev.c3 Copyright (C) 2001-2008 Miklos Szeredi <miklos@szeredi.hu>
37 * Lockless access is OK, because file->private data is set in fuse_get_dev()
40 return READ_ONCE(file->private_data); in fuse_get_dev()
45 INIT_LIST_HEAD(&req->list); in fuse_request_init()
46 INIT_LIST_HEAD(&req->intr_entry); in fuse_request_init()
47 init_waitqueue_head(&req->waitq); in fuse_request_init()
48 refcount_set(&req->count, 1); in fuse_request_init()
49 __set_bit(FR_PENDING, &req->flags); in fuse_request_init()
50 req->fm = fm; in fuse_request_init()
69 refcount_inc(&req->count); in __fuse_get_request()
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/openbmc/linux/drivers/spi/
H A Dspi-omap2-mcspi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
15 #include <linux/dma-mapping.h>
30 #include <linux/platform_data/spi-omap2-mcspi.h>
47 /* per-channel banks, 0x14 bytes each, first is: */
54 /* per-register bitmasks: */
90 /* We have 2 DMA channels per CS, one for RX and one for TX */
115 struct list_head cs; member
151 writel_relaxed(val, mcspi->base + idx); in mcspi_write_reg()
158 return readl_relaxed(mcspi->base + idx); in mcspi_read_reg()
164 struct omap2_mcspi_cs *cs = spi->controller_state; in mcspi_write_cs_reg() local
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/openbmc/linux/tools/testing/selftests/cachestat/
H A Dtest_cachestat.c1 // SPDX-License-Identifier: GPL-2.0
28 void print_cachestat(struct cachestat *cs) in print_cachestat() argument
32 cs->nr_cache, cs->nr_dirty, cs->nr_writeback, in print_cachestat()
33 cs->nr_evicted, cs->nr_recently_evicted); in print_cachestat()
46 goto out; in write_exactly()
68 remained -= read_len; in write_exactly()
84 remained -= write_len; in write_exactly()
93 out: in write_exactly()
126 struct cachestat cs; in test_cachestat() local
131 if (fd == -1) { in test_cachestat()
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/openbmc/qemu/target/i386/kvm/
H A Dxen-emu.c8 * See the COPYING file in the top-level directory.
14 #include "qemu/main-loop.h"
15 #include "qemu/error-report.h"
20 #include "exec/address-spaces.h"
21 #include "xen-emu.h"
26 #include "hw/i386/apic-msidef.h"
43 #include "xen-compat.h"
47 static int vcpuop_stop_singleshot_timer(CPUState *cs);
55 static bool kvm_gva_to_gpa(CPUState *cs, uint64_t gva, uint64_t *gpa, in kvm_gva_to_gpa() argument
63 *len = TARGET_PAGE_SIZE - (gva & ~TARGET_PAGE_MASK); in kvm_gva_to_gpa()
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/openbmc/u-boot/drivers/spi/
H A Datmel_spi.c1 // SPDX-License-Identifier: GPL-2.0+
37 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, in spi_setup_slave() argument
45 if (!spi_cs_is_valid(bus, cs)) in spi_setup_slave()
72 scbr = (get_spi_clk_rate(bus) + max_hz - 1) / max_hz; in spi_setup_slave()
86 as = spi_alloc_slave(struct atmel_spi_slave, bus, cs); in spi_setup_slave()
90 as->regs = regs; in spi_setup_slave()
91 as->mr = ATMEL_SPI_MR_MSTR | ATMEL_SPI_MR_MODFDIS in spi_setup_slave()
92 | ATMEL_SPI_MR_PCS(~(1 << cs) & 0xf); in spi_setup_slave()
94 as->mr |= ATMEL_SPI_MR_WDRBT; in spi_setup_slave()
96 spi_writel(as, CSR(cs), csrx); in spi_setup_slave()
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H A Domap3_spi.c1 // SPDX-License-Identifier: GPL-2.0+
9 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
43 /* per-register bitmasks */
104 /* channel0: 0x2C - 0x3C, bus 0 & 1 & 2 & 3 */
105 /* channel1: 0x40 - 0x50, bus 0 & 1 */
106 /* channel2: 0x54 - 0x64, bus 0 & 1 */
107 /* channel3: 0x68 - 0x78, bus 0 */
115 unsigned int cs; member
124 writel(val, &priv->regs->channel[priv->cs].chconf); in omap3_spi_write_chconf()
126 readl(&priv->regs->channel[priv->cs].chconf); in omap3_spi_write_chconf()
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H A Ddavinci_spi.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
60 * driver. Platform can configure number of CS using CONFIG_SYS_SPI0_NUM_CS
61 * if more than one CS is supported and by defining CONFIG_SYS_SPI0.
70 * define CONFIG_SYS_SPI1 when platform has spi-1 device (bus #1) and
71 * CONFIG_SYS_SPI1_NUM_CS defines number of CS on this bus
80 * define CONFIG_SYS_SPI2 when platform has spi-2 device (bus #2) and
81 * CONFIG_SYS_SPI2_NUM_CS defines number of CS on this bus
128 u8 num_cs; /* total no. of CS available */
129 u8 cur_cs; /* CS of current slave */
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/openbmc/linux/kernel/cgroup/
H A Dcpuset.c7 * Copyright (C) 2004-2007 Silicon Graphics, Inc.
11 * sysfs is Copyright (c) 2001-3 Patrick Mochel
13 * 2003-10-10 Written by Simon Derr.
14 * 2003-10-22 Updates by Stephen Hemminger.
15 * 2004 May-July Rework by Paul Jackson.
24 #include "cgroup-internal.h"
53 * node binding, add this key to provide a quick low-cost judgment
99 * The user-configured masks can only be changed by writing to
113 * The user-configured masks are always the same with effective masks.
116 /* user-configured CPUs and Memory Nodes allow to tasks */
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/openbmc/u-boot/drivers/video/
H A Dhitachi_tx18d42vm_lcd.c1 // SPDX-License-Identifier: GPL-2.0+
18 static void lcd_panel_spi_write(int cs, int clk, int mosi, in lcd_panel_spi_write() argument
23 gpio_direction_output(cs, 0); in lcd_panel_spi_write()
26 offset = (bits - 1) - i; in lcd_panel_spi_write()
32 gpio_direction_output(cs, 1); in lcd_panel_spi_write()
48 int i, cs, clk, mosi, ret = 0; in hitachi_tx18d42vm_init() local
50 cs = name_to_gpio(CONFIG_VIDEO_LCD_SPI_CS); in hitachi_tx18d42vm_init()
54 if (cs == -1 || clk == -1 || mosi == 1) { in hitachi_tx18d42vm_init()
56 return -EINVAL; in hitachi_tx18d42vm_init()
59 if (gpio_request(cs, "tx18d42vm-spi-cs") != 0 || in hitachi_tx18d42vm_init()
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/openbmc/qemu/monitor/
H A Dhmp-cmds-target.c2 * Miscellaneous target-dependent HMP commands
4 * Copyright (c) 2003-2004 Fabrice Bellard
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 #include "exec/address-spaces.h"
29 #include "monitor/hmp-target.h"
30 #include "monitor/monitor-internal.h"
42 return -1; in monitor_set_cpu()
44 g_free(mon->mon_cpu_path); in monitor_set_cpu()
45 mon->mon_cpu_path = object_get_canonical_path(OBJECT(cpu)); in monitor_set_cpu()
54 if (mon->mon_cpu_path) { in mon_get_cpu_sync()
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/openbmc/linux/drivers/gpu/drm/i915/gvt/
H A Dmmio_context.c2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
168 struct intel_gvt *gvt = engine->i915->gvt; in load_render_mocs()
169 struct intel_uncore *uncore = engine->uncore; in load_render_mocs()
170 u32 cnt = gvt->engine_mmio_list.mocs_mmio_offset_list_cnt; in load_render_mocs()
171 u32 *regs = gvt->engine_mmio_list.mocs_mmio_offset_list; in load_render_mocs()
180 if (!HAS_ENGINE(engine->gt, ring_id)) in load_render_mocs()
204 u32 *cs; in restore_context_mmio_for_inhibit() local
207 struct intel_gvt *gvt = vgpu->gvt; in restore_context_mmio_for_inhibit()
208 int ring_id = req->engine->id; in restore_context_mmio_for_inhibit()
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/openbmc/linux/arch/arm64/boot/dts/hisilicon/
H A Dhi6220-coresight.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
14 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
17 clock-names = "apb_pclk";
19 out-ports {
22 remote-endpoint =
28 in-ports {
31 remote-endpoint =
39 compatible = "arm,coresight-tmc", "arm,primecell";
42 clock-names = "apb_pclk";
44 in-ports {
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/openbmc/qemu/target/s390x/
H A Dcpu.c26 #include "s390x-internal.h"
31 #include "qapi/qapi-types-machine.h"
33 #include "hw/qdev-properties.h"
34 #include "hw/qdev-properties-system.h"
36 #include "fpu/softfloat-helpers.h"
42 #include "hw/s390x/cpu-topology.h"
70 uint64_t old_mask = env->psw.mask; in s390_cpu_set_psw()
73 env->psw.addr = addr; in s390_cpu_set_psw()
74 env->psw.mask = mask; in s390_cpu_set_psw()
80 env->cc_op = (mask >> 44) & 3; in s390_cpu_set_psw()
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/openbmc/qemu/target/ppc/
H A Dtimebase_helper.c4 * Copyright (c) 2003-2007 Jocelyn Mayer
22 #include "exec/helper-proto.h"
23 #include "exec/exec-all.h"
25 #include "qemu/main-loop.h"
63 CPUState *cs = env_cpu(env); in helper_store_purr() local
66 if (ppc_cpu_lpar_single_threaded(cs)) { in helper_store_purr()
71 THREAD_SIBLING_FOREACH(cs, ccs) { in helper_store_purr()
72 CPUPPCState *cenv = &POWERPC_CPU(ccs)->env; in helper_store_purr()
81 CPUState *cs = env_cpu(env); in helper_store_tbl() local
84 if (ppc_cpu_lpar_single_threaded(cs)) { in helper_store_tbl()
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/openbmc/u-boot/include/
H A Dspi.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Common SPI Interface: Controller-specific definitions
21 #define SPI_CS_HIGH BIT(2) /* CS active high */
22 #define SPI_LSB_FIRST BIT(3) /* per-word bits-on-wire */
46 * struct dm_spi_platdata - platform data for all SPI slaves
50 * dev_get_parent_platdata(slave->dev).
55 * @cs: Chip select number (0..n-1)
60 unsigned int cs; member
68 * struct spi_slave - Representation of a SPI slave
70 * For driver model this is the per-child data used by the SPI bus. It can
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