Lines Matching +full:cs +full:- +full:out
1 // SPDX-License-Identifier: GPL-2.0-or-later
15 #include <linux/dma-mapping.h>
30 #include <linux/platform_data/spi-omap2-mcspi.h>
47 /* per-channel banks, 0x14 bytes each, first is: */
54 /* per-register bitmasks: */
90 /* We have 2 DMA channels per CS, one for RX and one for TX */
115 struct list_head cs; member
151 writel_relaxed(val, mcspi->base + idx); in mcspi_write_reg()
158 return readl_relaxed(mcspi->base + idx); in mcspi_read_reg()
164 struct omap2_mcspi_cs *cs = spi->controller_state; in mcspi_write_cs_reg() local
166 writel_relaxed(val, cs->base + idx); in mcspi_write_cs_reg()
171 struct omap2_mcspi_cs *cs = spi->controller_state; in mcspi_read_cs_reg() local
173 return readl_relaxed(cs->base + idx); in mcspi_read_cs_reg()
178 struct omap2_mcspi_cs *cs = spi->controller_state; in mcspi_cached_chconf0() local
180 return cs->chconf0; in mcspi_cached_chconf0()
185 struct omap2_mcspi_cs *cs = spi->controller_state; in mcspi_write_chconf0() local
187 cs->chconf0 = val; in mcspi_write_chconf0()
224 struct omap2_mcspi_cs *cs = spi->controller_state; in omap2_mcspi_set_enable() local
227 l = cs->chctrl0; in omap2_mcspi_set_enable()
232 cs->chctrl0 = l; in omap2_mcspi_set_enable()
233 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0); in omap2_mcspi_set_enable()
234 /* Flash post-writes */ in omap2_mcspi_set_enable()
240 struct omap2_mcspi *mcspi = spi_controller_get_devdata(spi->controller); in omap2_mcspi_set_cs()
247 if (spi->mode & SPI_CS_HIGH) in omap2_mcspi_set_cs()
250 if (spi->controller_state) { in omap2_mcspi_set_cs()
251 int err = pm_runtime_resume_and_get(mcspi->dev); in omap2_mcspi_set_cs()
253 dev_err(mcspi->dev, "failed to get sync: %d\n", err); in omap2_mcspi_set_cs()
266 pm_runtime_mark_last_busy(mcspi->dev); in omap2_mcspi_set_cs()
267 pm_runtime_put_autosuspend(mcspi->dev); in omap2_mcspi_set_cs()
274 struct omap2_mcspi_regs *ctx = &mcspi->ctx; in omap2_mcspi_set_mode()
290 ctx->modulctrl = l; in omap2_mcspi_set_mode()
296 struct spi_controller *ctlr = spi->controller; in omap2_mcspi_set_fifo()
297 struct omap2_mcspi_cs *cs = spi->controller_state; in omap2_mcspi_set_fifo() local
307 bytes_per_word = mcspi_bytes_per_word(cs->word_len); in omap2_mcspi_set_fifo()
308 if (t->len % bytes_per_word != 0) in omap2_mcspi_set_fifo()
311 if (t->rx_buf != NULL && t->tx_buf != NULL) in omap2_mcspi_set_fifo()
316 wcnt = t->len / bytes_per_word; in omap2_mcspi_set_fifo()
321 if (t->rx_buf != NULL) { in omap2_mcspi_set_fifo()
323 xferlevel |= (bytes_per_word - 1) << 8; in omap2_mcspi_set_fifo()
326 if (t->tx_buf != NULL) { in omap2_mcspi_set_fifo()
328 xferlevel |= bytes_per_word - 1; in omap2_mcspi_set_fifo()
333 mcspi->fifo_depth = max_fifo_depth; in omap2_mcspi_set_fifo()
339 if (t->rx_buf != NULL) in omap2_mcspi_set_fifo()
342 if (t->tx_buf != NULL) in omap2_mcspi_set_fifo()
346 mcspi->fifo_depth = 0; in omap2_mcspi_set_fifo()
357 return -ETIMEDOUT; in mcspi_wait_for_reg_bit()
369 if (spi_controller_is_target(mcspi->ctlr)) { in mcspi_wait_for_completion()
371 mcspi->target_aborted) in mcspi_wait_for_completion()
372 return -EINTR; in mcspi_wait_for_completion()
383 struct omap2_mcspi *mcspi = spi_controller_get_devdata(spi->controller); in omap2_mcspi_rx_callback()
384 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi_get_chipselect(spi, 0)]; in omap2_mcspi_rx_callback()
389 complete(&mcspi_dma->dma_rx_completion); in omap2_mcspi_rx_callback()
395 struct omap2_mcspi *mcspi = spi_controller_get_devdata(spi->controller); in omap2_mcspi_tx_callback()
396 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi_get_chipselect(spi, 0)]; in omap2_mcspi_tx_callback()
401 complete(&mcspi_dma->dma_tx_completion); in omap2_mcspi_tx_callback()
412 mcspi = spi_controller_get_devdata(spi->controller); in omap2_mcspi_tx_dma()
413 mcspi_dma = &mcspi->dma_channels[spi_get_chipselect(spi, 0)]; in omap2_mcspi_tx_dma()
415 dmaengine_slave_config(mcspi_dma->dma_tx, &cfg); in omap2_mcspi_tx_dma()
417 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, xfer->tx_sg.sgl, in omap2_mcspi_tx_dma()
418 xfer->tx_sg.nents, in omap2_mcspi_tx_dma()
422 tx->callback = omap2_mcspi_tx_callback; in omap2_mcspi_tx_dma()
423 tx->callback_param = spi; in omap2_mcspi_tx_dma()
428 dma_async_issue_pending(mcspi_dma->dma_tx); in omap2_mcspi_tx_dma()
446 struct omap2_mcspi_cs *cs = spi->controller_state; in omap2_mcspi_rx_dma() local
447 void __iomem *chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0; in omap2_mcspi_rx_dma()
450 mcspi = spi_controller_get_devdata(spi->controller); in omap2_mcspi_rx_dma()
451 mcspi_dma = &mcspi->dma_channels[spi_get_chipselect(spi, 0)]; in omap2_mcspi_rx_dma()
452 count = xfer->len; in omap2_mcspi_rx_dma()
455 * In the "End-of-Transfer Procedure" section for DMA RX in OMAP35x TRM in omap2_mcspi_rx_dma()
459 if (mcspi->fifo_depth == 0) in omap2_mcspi_rx_dma()
462 word_len = cs->word_len; in omap2_mcspi_rx_dma()
473 dmaengine_slave_config(mcspi_dma->dma_rx, &cfg); in omap2_mcspi_rx_dma()
479 if ((l & OMAP2_MCSPI_CHCONF_TURBO) && mcspi->fifo_depth == 0) in omap2_mcspi_rx_dma()
484 sizes[0] = count - transfer_reduction; in omap2_mcspi_rx_dma()
496 ret = sg_split(xfer->rx_sg.sgl, xfer->rx_sg.nents, 0, nb_sizes, in omap2_mcspi_rx_dma()
500 dev_err(&spi->dev, "sg_split failed\n"); in omap2_mcspi_rx_dma()
504 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, sg_out[0], in omap2_mcspi_rx_dma()
508 tx->callback = omap2_mcspi_rx_callback; in omap2_mcspi_rx_dma()
509 tx->callback_param = spi; in omap2_mcspi_rx_dma()
515 dma_async_issue_pending(mcspi_dma->dma_rx); in omap2_mcspi_rx_dma()
518 ret = mcspi_wait_for_completion(mcspi, &mcspi_dma->dma_rx_completion); in omap2_mcspi_rx_dma()
519 if (ret || mcspi->target_aborted) { in omap2_mcspi_rx_dma()
520 dmaengine_terminate_sync(mcspi_dma->dma_rx); in omap2_mcspi_rx_dma()
528 if (mcspi->fifo_depth > 0) in omap2_mcspi_rx_dma()
537 elements = element_count - 1; in omap2_mcspi_rx_dma()
540 elements--; in omap2_mcspi_rx_dma()
548 ((u8 *)xfer->rx_buf)[elements++] = w; in omap2_mcspi_rx_dma()
550 ((u16 *)xfer->rx_buf)[elements++] = w; in omap2_mcspi_rx_dma()
552 ((u32 *)xfer->rx_buf)[elements++] = w; in omap2_mcspi_rx_dma()
555 dev_err(&spi->dev, "DMA RX penultimate word empty\n"); in omap2_mcspi_rx_dma()
556 count -= (bytes_per_word << 1); in omap2_mcspi_rx_dma()
566 ((u8 *)xfer->rx_buf)[elements] = w; in omap2_mcspi_rx_dma()
568 ((u16 *)xfer->rx_buf)[elements] = w; in omap2_mcspi_rx_dma()
570 ((u32 *)xfer->rx_buf)[elements] = w; in omap2_mcspi_rx_dma()
572 dev_err(&spi->dev, "DMA RX last word empty\n"); in omap2_mcspi_rx_dma()
573 count -= mcspi_bytes_per_word(word_len); in omap2_mcspi_rx_dma()
583 struct omap2_mcspi_cs *cs = spi->controller_state; in omap2_mcspi_txrx_dma() local
595 mcspi = spi_controller_get_devdata(spi->controller); in omap2_mcspi_txrx_dma()
596 mcspi_dma = &mcspi->dma_channels[spi_get_chipselect(spi, 0)]; in omap2_mcspi_txrx_dma()
598 if (cs->word_len <= 8) { in omap2_mcspi_txrx_dma()
601 } else if (cs->word_len <= 16) { in omap2_mcspi_txrx_dma()
609 count = xfer->len; in omap2_mcspi_txrx_dma()
612 cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0; in omap2_mcspi_txrx_dma()
613 cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0; in omap2_mcspi_txrx_dma()
619 rx = xfer->rx_buf; in omap2_mcspi_txrx_dma()
620 tx = xfer->tx_buf; in omap2_mcspi_txrx_dma()
622 mcspi->target_aborted = false; in omap2_mcspi_txrx_dma()
623 reinit_completion(&mcspi_dma->dma_tx_completion); in omap2_mcspi_txrx_dma()
624 reinit_completion(&mcspi_dma->dma_rx_completion); in omap2_mcspi_txrx_dma()
625 reinit_completion(&mcspi->txdone); in omap2_mcspi_txrx_dma()
628 if (spi_controller_is_target(spi->controller)) in omap2_mcspi_txrx_dma()
629 mcspi_write_reg(spi->controller, in omap2_mcspi_txrx_dma()
641 ret = mcspi_wait_for_completion(mcspi, &mcspi_dma->dma_tx_completion); in omap2_mcspi_txrx_dma()
642 if (ret || mcspi->target_aborted) { in omap2_mcspi_txrx_dma()
643 dmaengine_terminate_sync(mcspi_dma->dma_tx); in omap2_mcspi_txrx_dma()
648 if (spi_controller_is_target(mcspi->ctlr)) { in omap2_mcspi_txrx_dma()
649 ret = mcspi_wait_for_completion(mcspi, &mcspi->txdone); in omap2_mcspi_txrx_dma()
650 if (ret || mcspi->target_aborted) in omap2_mcspi_txrx_dma()
654 if (mcspi->fifo_depth > 0) { in omap2_mcspi_txrx_dma()
655 irqstat_reg = mcspi->base + OMAP2_MCSPI_IRQSTATUS; in omap2_mcspi_txrx_dma()
659 dev_err(&spi->dev, "EOW timed out\n"); in omap2_mcspi_txrx_dma()
661 mcspi_write_reg(mcspi->ctlr, OMAP2_MCSPI_IRQSTATUS, in omap2_mcspi_txrx_dma()
665 /* for TX_ONLY mode, be sure all words have shifted out */ in omap2_mcspi_txrx_dma()
667 chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0; in omap2_mcspi_txrx_dma()
668 if (mcspi->fifo_depth > 0) { in omap2_mcspi_txrx_dma()
672 dev_err(&spi->dev, "TXFFE timed out\n"); in omap2_mcspi_txrx_dma()
677 dev_err(&spi->dev, "TXS timed out\n"); in omap2_mcspi_txrx_dma()
682 dev_err(&spi->dev, "EOT timed out\n"); in omap2_mcspi_txrx_dma()
691 struct omap2_mcspi_cs *cs = spi->controller_state; in omap2_mcspi_txrx_pio() local
694 void __iomem *base = cs->base; in omap2_mcspi_txrx_pio()
700 count = xfer->len; in omap2_mcspi_txrx_pio()
702 word_len = cs->word_len; in omap2_mcspi_txrx_pio()
706 /* We store the pre-calculated register addresses on stack to speed in omap2_mcspi_txrx_pio()
719 rx = xfer->rx_buf; in omap2_mcspi_txrx_pio()
720 tx = xfer->tx_buf; in omap2_mcspi_txrx_pio()
723 c -= 1; in omap2_mcspi_txrx_pio()
727 dev_err(&spi->dev, "TXS timed out\n"); in omap2_mcspi_txrx_pio()
728 goto out; in omap2_mcspi_txrx_pio()
730 dev_vdbg(&spi->dev, "write-%d %02x\n", in omap2_mcspi_txrx_pio()
737 dev_err(&spi->dev, "RXS timed out\n"); in omap2_mcspi_txrx_pio()
738 goto out; in omap2_mcspi_txrx_pio()
745 dev_vdbg(&spi->dev, "read-%d %02x\n", in omap2_mcspi_txrx_pio()
746 word_len, *(rx - 1)); in omap2_mcspi_txrx_pio()
749 dev_err(&spi->dev, in omap2_mcspi_txrx_pio()
750 "RXS timed out\n"); in omap2_mcspi_txrx_pio()
751 goto out; in omap2_mcspi_txrx_pio()
759 dev_vdbg(&spi->dev, "read-%d %02x\n", in omap2_mcspi_txrx_pio()
760 word_len, *(rx - 1)); in omap2_mcspi_txrx_pio()
763 spi_delay_exec(&xfer->word_delay, xfer); in omap2_mcspi_txrx_pio()
769 rx = xfer->rx_buf; in omap2_mcspi_txrx_pio()
770 tx = xfer->tx_buf; in omap2_mcspi_txrx_pio()
772 c -= 2; in omap2_mcspi_txrx_pio()
776 dev_err(&spi->dev, "TXS timed out\n"); in omap2_mcspi_txrx_pio()
777 goto out; in omap2_mcspi_txrx_pio()
779 dev_vdbg(&spi->dev, "write-%d %04x\n", in omap2_mcspi_txrx_pio()
786 dev_err(&spi->dev, "RXS timed out\n"); in omap2_mcspi_txrx_pio()
787 goto out; in omap2_mcspi_txrx_pio()
794 dev_vdbg(&spi->dev, "read-%d %04x\n", in omap2_mcspi_txrx_pio()
795 word_len, *(rx - 1)); in omap2_mcspi_txrx_pio()
798 dev_err(&spi->dev, in omap2_mcspi_txrx_pio()
799 "RXS timed out\n"); in omap2_mcspi_txrx_pio()
800 goto out; in omap2_mcspi_txrx_pio()
808 dev_vdbg(&spi->dev, "read-%d %04x\n", in omap2_mcspi_txrx_pio()
809 word_len, *(rx - 1)); in omap2_mcspi_txrx_pio()
812 spi_delay_exec(&xfer->word_delay, xfer); in omap2_mcspi_txrx_pio()
818 rx = xfer->rx_buf; in omap2_mcspi_txrx_pio()
819 tx = xfer->tx_buf; in omap2_mcspi_txrx_pio()
821 c -= 4; in omap2_mcspi_txrx_pio()
825 dev_err(&spi->dev, "TXS timed out\n"); in omap2_mcspi_txrx_pio()
826 goto out; in omap2_mcspi_txrx_pio()
828 dev_vdbg(&spi->dev, "write-%d %08x\n", in omap2_mcspi_txrx_pio()
835 dev_err(&spi->dev, "RXS timed out\n"); in omap2_mcspi_txrx_pio()
836 goto out; in omap2_mcspi_txrx_pio()
843 dev_vdbg(&spi->dev, "read-%d %08x\n", in omap2_mcspi_txrx_pio()
844 word_len, *(rx - 1)); in omap2_mcspi_txrx_pio()
847 dev_err(&spi->dev, in omap2_mcspi_txrx_pio()
848 "RXS timed out\n"); in omap2_mcspi_txrx_pio()
849 goto out; in omap2_mcspi_txrx_pio()
857 dev_vdbg(&spi->dev, "read-%d %08x\n", in omap2_mcspi_txrx_pio()
858 word_len, *(rx - 1)); in omap2_mcspi_txrx_pio()
861 spi_delay_exec(&xfer->word_delay, xfer); in omap2_mcspi_txrx_pio()
865 /* for TX_ONLY mode, be sure all words have shifted out */ in omap2_mcspi_txrx_pio()
866 if (xfer->rx_buf == NULL) { in omap2_mcspi_txrx_pio()
869 dev_err(&spi->dev, "TXS timed out\n"); in omap2_mcspi_txrx_pio()
872 dev_err(&spi->dev, "EOT timed out\n"); in omap2_mcspi_txrx_pio()
880 out: in omap2_mcspi_txrx_pio()
882 return count - c; in omap2_mcspi_txrx_pio()
900 struct omap2_mcspi_cs *cs = spi->controller_state; in omap2_mcspi_setup_transfer() local
903 u8 word_len = spi->bits_per_word; in omap2_mcspi_setup_transfer()
904 u32 speed_hz = spi->max_speed_hz; in omap2_mcspi_setup_transfer()
906 mcspi = spi_controller_get_devdata(spi->controller); in omap2_mcspi_setup_transfer()
908 if (t != NULL && t->bits_per_word) in omap2_mcspi_setup_transfer()
909 word_len = t->bits_per_word; in omap2_mcspi_setup_transfer()
911 cs->word_len = word_len; in omap2_mcspi_setup_transfer()
913 if (t && t->speed_hz) in omap2_mcspi_setup_transfer()
914 speed_hz = t->speed_hz; in omap2_mcspi_setup_transfer()
916 ref_clk_hz = mcspi->ref_clk_hz; in omap2_mcspi_setup_transfer()
923 div = (ref_clk_hz + speed_hz - 1) / speed_hz; in omap2_mcspi_setup_transfer()
925 clkd = (div - 1) & 0xf; in omap2_mcspi_setup_transfer()
926 extclk = (div - 1) >> 4; in omap2_mcspi_setup_transfer()
932 /* standard 4-wire host mode: SCK, MOSI/out, MISO/in, nCS in omap2_mcspi_setup_transfer()
935 if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) { in omap2_mcspi_setup_transfer()
947 l |= (word_len - 1) << 7; in omap2_mcspi_setup_transfer()
950 if (!(spi->mode & SPI_CS_HIGH)) in omap2_mcspi_setup_transfer()
951 l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */ in omap2_mcspi_setup_transfer()
963 cs->chctrl0 &= ~OMAP2_MCSPI_CHCTRL_EXTCLK_MASK; in omap2_mcspi_setup_transfer()
964 cs->chctrl0 |= extclk << 8; in omap2_mcspi_setup_transfer()
965 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0); in omap2_mcspi_setup_transfer()
969 if (spi->mode & SPI_CPOL) in omap2_mcspi_setup_transfer()
973 if (spi->mode & SPI_CPHA) in omap2_mcspi_setup_transfer()
980 cs->mode = spi->mode; in omap2_mcspi_setup_transfer()
982 dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n", in omap2_mcspi_setup_transfer()
984 (spi->mode & SPI_CPHA) ? "trailing" : "leading", in omap2_mcspi_setup_transfer()
985 (spi->mode & SPI_CPOL) ? "inverted" : "normal"); in omap2_mcspi_setup_transfer()
999 mcspi_dma->dma_rx = dma_request_chan(mcspi->dev, in omap2_mcspi_request_dma()
1000 mcspi_dma->dma_rx_ch_name); in omap2_mcspi_request_dma()
1001 if (IS_ERR(mcspi_dma->dma_rx)) { in omap2_mcspi_request_dma()
1002 ret = PTR_ERR(mcspi_dma->dma_rx); in omap2_mcspi_request_dma()
1003 mcspi_dma->dma_rx = NULL; in omap2_mcspi_request_dma()
1007 mcspi_dma->dma_tx = dma_request_chan(mcspi->dev, in omap2_mcspi_request_dma()
1008 mcspi_dma->dma_tx_ch_name); in omap2_mcspi_request_dma()
1009 if (IS_ERR(mcspi_dma->dma_tx)) { in omap2_mcspi_request_dma()
1010 ret = PTR_ERR(mcspi_dma->dma_tx); in omap2_mcspi_request_dma()
1011 mcspi_dma->dma_tx = NULL; in omap2_mcspi_request_dma()
1012 dma_release_channel(mcspi_dma->dma_rx); in omap2_mcspi_request_dma()
1013 mcspi_dma->dma_rx = NULL; in omap2_mcspi_request_dma()
1016 init_completion(&mcspi_dma->dma_rx_completion); in omap2_mcspi_request_dma()
1017 init_completion(&mcspi_dma->dma_tx_completion); in omap2_mcspi_request_dma()
1029 for (i = 0; i < ctlr->num_chipselect; i++) { in omap2_mcspi_release_dma()
1030 mcspi_dma = &mcspi->dma_channels[i]; in omap2_mcspi_release_dma()
1032 if (mcspi_dma->dma_rx) { in omap2_mcspi_release_dma()
1033 dma_release_channel(mcspi_dma->dma_rx); in omap2_mcspi_release_dma()
1034 mcspi_dma->dma_rx = NULL; in omap2_mcspi_release_dma()
1036 if (mcspi_dma->dma_tx) { in omap2_mcspi_release_dma()
1037 dma_release_channel(mcspi_dma->dma_tx); in omap2_mcspi_release_dma()
1038 mcspi_dma->dma_tx = NULL; in omap2_mcspi_release_dma()
1045 struct omap2_mcspi_cs *cs; in omap2_mcspi_cleanup() local
1047 if (spi->controller_state) { in omap2_mcspi_cleanup()
1049 cs = spi->controller_state; in omap2_mcspi_cleanup()
1050 list_del(&cs->node); in omap2_mcspi_cleanup()
1052 kfree(cs); in omap2_mcspi_cleanup()
1060 struct omap2_mcspi *mcspi = spi_controller_get_devdata(spi->controller); in omap2_mcspi_setup()
1061 struct omap2_mcspi_regs *ctx = &mcspi->ctx; in omap2_mcspi_setup()
1062 struct omap2_mcspi_cs *cs = spi->controller_state; in omap2_mcspi_setup() local
1064 if (!cs) { in omap2_mcspi_setup()
1065 cs = kzalloc(sizeof(*cs), GFP_KERNEL); in omap2_mcspi_setup()
1066 if (!cs) in omap2_mcspi_setup()
1067 return -ENOMEM; in omap2_mcspi_setup()
1068 cs->base = mcspi->base + spi_get_chipselect(spi, 0) * 0x14; in omap2_mcspi_setup()
1069 cs->phys = mcspi->phys + spi_get_chipselect(spi, 0) * 0x14; in omap2_mcspi_setup()
1070 cs->mode = 0; in omap2_mcspi_setup()
1071 cs->chconf0 = 0; in omap2_mcspi_setup()
1072 cs->chctrl0 = 0; in omap2_mcspi_setup()
1073 spi->controller_state = cs; in omap2_mcspi_setup()
1075 list_add_tail(&cs->node, &ctx->cs); in omap2_mcspi_setup()
1079 ret = pm_runtime_resume_and_get(mcspi->dev); in omap2_mcspi_setup()
1091 pm_runtime_mark_last_busy(mcspi->dev); in omap2_mcspi_setup()
1092 pm_runtime_put_autosuspend(mcspi->dev); in omap2_mcspi_setup()
1102 irqstat = mcspi_read_reg(mcspi->ctlr, OMAP2_MCSPI_IRQSTATUS); in omap2_mcspi_irq_handler()
1107 mcspi_write_reg(mcspi->ctlr, OMAP2_MCSPI_IRQENABLE, 0); in omap2_mcspi_irq_handler()
1109 complete(&mcspi->txdone); in omap2_mcspi_irq_handler()
1117 struct omap2_mcspi_dma *mcspi_dma = mcspi->dma_channels; in omap2_mcspi_target_abort()
1119 mcspi->target_aborted = true; in omap2_mcspi_target_abort()
1120 complete(&mcspi_dma->dma_rx_completion); in omap2_mcspi_target_abort()
1121 complete(&mcspi_dma->dma_tx_completion); in omap2_mcspi_target_abort()
1122 complete(&mcspi->txdone); in omap2_mcspi_target_abort()
1132 /* We only enable one channel at a time -- the one whose message is in omap2_mcspi_transfer_one()
1133 * -- although this controller would gladly in omap2_mcspi_transfer_one()
1136 * chipselect with the FORCE bit ... CS != channel enable. in omap2_mcspi_transfer_one()
1141 struct omap2_mcspi_cs *cs; in omap2_mcspi_transfer_one() local
1148 mcspi_dma = mcspi->dma_channels + spi_get_chipselect(spi, 0); in omap2_mcspi_transfer_one()
1149 cs = spi->controller_state; in omap2_mcspi_transfer_one()
1150 cd = spi->controller_data; in omap2_mcspi_transfer_one()
1153 * The target driver could have changed spi->mode in which case in omap2_mcspi_transfer_one()
1154 * it will be different from cs->mode (the current hardware setup). in omap2_mcspi_transfer_one()
1159 if (spi->mode != cs->mode) in omap2_mcspi_transfer_one()
1165 omap2_mcspi_set_cs(spi, spi->mode & SPI_CS_HIGH); in omap2_mcspi_transfer_one()
1168 (t->speed_hz != spi->max_speed_hz) || in omap2_mcspi_transfer_one()
1169 (t->bits_per_word != spi->bits_per_word)) { in omap2_mcspi_transfer_one()
1173 goto out; in omap2_mcspi_transfer_one()
1174 if (t->speed_hz == spi->max_speed_hz && in omap2_mcspi_transfer_one()
1175 t->bits_per_word == spi->bits_per_word) in omap2_mcspi_transfer_one()
1178 if (cd && cd->cs_per_word) { in omap2_mcspi_transfer_one()
1179 chconf = mcspi->ctx.modulctrl; in omap2_mcspi_transfer_one()
1182 mcspi->ctx.modulctrl = in omap2_mcspi_transfer_one()
1190 if (t->tx_buf == NULL) in omap2_mcspi_transfer_one()
1192 else if (t->rx_buf == NULL) in omap2_mcspi_transfer_one()
1195 if (cd && cd->turbo_mode && t->tx_buf == NULL) { in omap2_mcspi_transfer_one()
1197 if (t->len > ((cs->word_len + 7) >> 3)) in omap2_mcspi_transfer_one()
1203 if (t->len) { in omap2_mcspi_transfer_one()
1206 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) && in omap2_mcspi_transfer_one()
1207 ctlr->cur_msg_mapped && in omap2_mcspi_transfer_one()
1208 ctlr->can_dma(ctlr, spi, t)) in omap2_mcspi_transfer_one()
1214 if (t->tx_buf == NULL) in omap2_mcspi_transfer_one()
1215 writel_relaxed(0, cs->base in omap2_mcspi_transfer_one()
1218 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) && in omap2_mcspi_transfer_one()
1219 ctlr->cur_msg_mapped && in omap2_mcspi_transfer_one()
1220 ctlr->can_dma(ctlr, spi, t)) in omap2_mcspi_transfer_one()
1225 if (count != t->len) { in omap2_mcspi_transfer_one()
1226 status = -EIO; in omap2_mcspi_transfer_one()
1227 goto out; in omap2_mcspi_transfer_one()
1233 if (mcspi->fifo_depth > 0) in omap2_mcspi_transfer_one()
1236 out: in omap2_mcspi_transfer_one()
1243 if (cd && cd->cs_per_word) { in omap2_mcspi_transfer_one()
1244 chconf = mcspi->ctx.modulctrl; in omap2_mcspi_transfer_one()
1247 mcspi->ctx.modulctrl = in omap2_mcspi_transfer_one()
1254 omap2_mcspi_set_cs(spi, !(spi->mode & SPI_CS_HIGH)); in omap2_mcspi_transfer_one()
1256 if (mcspi->fifo_depth > 0 && t) in omap2_mcspi_transfer_one()
1266 struct omap2_mcspi_regs *ctx = &mcspi->ctx; in omap2_mcspi_prepare_message()
1267 struct omap2_mcspi_cs *cs; in omap2_mcspi_prepare_message() local
1274 list_for_each_entry(cs, &ctx->cs, node) { in omap2_mcspi_prepare_message()
1275 if (msg->spi->controller_state == cs) in omap2_mcspi_prepare_message()
1278 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE)) { in omap2_mcspi_prepare_message()
1279 cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE; in omap2_mcspi_prepare_message()
1280 writel_relaxed(cs->chconf0, in omap2_mcspi_prepare_message()
1281 cs->base + OMAP2_MCSPI_CHCONF0); in omap2_mcspi_prepare_message()
1282 readl_relaxed(cs->base + OMAP2_MCSPI_CHCONF0); in omap2_mcspi_prepare_message()
1293 struct omap2_mcspi *mcspi = spi_controller_get_devdata(spi->controller); in omap2_mcspi_can_dma()
1295 &mcspi->dma_channels[spi_get_chipselect(spi, 0)]; in omap2_mcspi_can_dma()
1297 if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) in omap2_mcspi_can_dma()
1303 ctlr->dma_rx = mcspi_dma->dma_rx; in omap2_mcspi_can_dma()
1304 ctlr->dma_tx = mcspi_dma->dma_tx; in omap2_mcspi_can_dma()
1306 return (xfer->len >= DMA_MIN_BYTES); in omap2_mcspi_can_dma()
1311 struct omap2_mcspi *mcspi = spi_controller_get_devdata(spi->controller); in omap2_mcspi_max_xfer_size()
1313 &mcspi->dma_channels[spi_get_chipselect(spi, 0)]; in omap2_mcspi_max_xfer_size()
1315 if (mcspi->max_xfer_len && mcspi_dma->dma_rx) in omap2_mcspi_max_xfer_size()
1316 return mcspi->max_xfer_len; in omap2_mcspi_max_xfer_size()
1323 struct spi_controller *ctlr = mcspi->ctlr; in omap2_mcspi_controller_setup()
1324 struct omap2_mcspi_regs *ctx = &mcspi->ctx; in omap2_mcspi_controller_setup()
1327 ret = pm_runtime_resume_and_get(mcspi->dev); in omap2_mcspi_controller_setup()
1333 ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN; in omap2_mcspi_controller_setup()
1336 pm_runtime_mark_last_busy(mcspi->dev); in omap2_mcspi_controller_setup()
1337 pm_runtime_put_autosuspend(mcspi->dev); in omap2_mcspi_controller_setup()
1353 * When SPI wake up from off-mode, CS is in activate state. If it was in
1361 struct omap2_mcspi_regs *ctx = &mcspi->ctx; in omap_mcspi_runtime_resume()
1362 struct omap2_mcspi_cs *cs; in omap_mcspi_runtime_resume() local
1370 mcspi_write_reg(ctlr, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl); in omap_mcspi_runtime_resume()
1371 mcspi_write_reg(ctlr, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable); in omap_mcspi_runtime_resume()
1373 list_for_each_entry(cs, &ctx->cs, node) { in omap_mcspi_runtime_resume()
1375 * We need to toggle CS state for OMAP take this in omap_mcspi_runtime_resume()
1378 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) { in omap_mcspi_runtime_resume()
1379 cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE; in omap_mcspi_runtime_resume()
1380 writel_relaxed(cs->chconf0, in omap_mcspi_runtime_resume()
1381 cs->base + OMAP2_MCSPI_CHCONF0); in omap_mcspi_runtime_resume()
1382 cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE; in omap_mcspi_runtime_resume()
1383 writel_relaxed(cs->chconf0, in omap_mcspi_runtime_resume()
1384 cs->base + OMAP2_MCSPI_CHCONF0); in omap_mcspi_runtime_resume()
1386 writel_relaxed(cs->chconf0, in omap_mcspi_runtime_resume()
1387 cs->base + OMAP2_MCSPI_CHCONF0); in omap_mcspi_runtime_resume()
1404 .max_xfer_len = SZ_4K - 1,
1409 .compatible = "ti,omap2-mcspi",
1413 .compatible = "ti,omap4-mcspi",
1417 .compatible = "ti,am654-mcspi",
1432 struct device_node *node = pdev->dev.of_node; in omap2_mcspi_probe()
1435 if (of_property_read_bool(node, "spi-slave")) in omap2_mcspi_probe()
1436 ctlr = spi_alloc_target(&pdev->dev, sizeof(*mcspi)); in omap2_mcspi_probe()
1438 ctlr = spi_alloc_host(&pdev->dev, sizeof(*mcspi)); in omap2_mcspi_probe()
1440 return -ENOMEM; in omap2_mcspi_probe()
1442 /* the spi->mode bits understood by this driver: */ in omap2_mcspi_probe()
1443 ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; in omap2_mcspi_probe()
1444 ctlr->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); in omap2_mcspi_probe()
1445 ctlr->setup = omap2_mcspi_setup; in omap2_mcspi_probe()
1446 ctlr->auto_runtime_pm = true; in omap2_mcspi_probe()
1447 ctlr->prepare_message = omap2_mcspi_prepare_message; in omap2_mcspi_probe()
1448 ctlr->can_dma = omap2_mcspi_can_dma; in omap2_mcspi_probe()
1449 ctlr->transfer_one = omap2_mcspi_transfer_one; in omap2_mcspi_probe()
1450 ctlr->set_cs = omap2_mcspi_set_cs; in omap2_mcspi_probe()
1451 ctlr->cleanup = omap2_mcspi_cleanup; in omap2_mcspi_probe()
1452 ctlr->target_abort = omap2_mcspi_target_abort; in omap2_mcspi_probe()
1453 ctlr->dev.of_node = node; in omap2_mcspi_probe()
1454 ctlr->use_gpio_descriptors = true; in omap2_mcspi_probe()
1459 mcspi->ctlr = ctlr; in omap2_mcspi_probe()
1461 match = of_match_device(omap_mcspi_of_match, &pdev->dev); in omap2_mcspi_probe()
1464 pdata = match->data; in omap2_mcspi_probe()
1466 of_property_read_u32(node, "ti,spi-num-cs", &num_cs); in omap2_mcspi_probe()
1467 ctlr->num_chipselect = num_cs; in omap2_mcspi_probe()
1468 if (of_property_read_bool(node, "ti,pindir-d0-out-d1-in")) in omap2_mcspi_probe()
1469 mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN; in omap2_mcspi_probe()
1471 pdata = dev_get_platdata(&pdev->dev); in omap2_mcspi_probe()
1472 ctlr->num_chipselect = pdata->num_cs; in omap2_mcspi_probe()
1473 mcspi->pin_dir = pdata->pin_dir; in omap2_mcspi_probe()
1475 regs_offset = pdata->regs_offset; in omap2_mcspi_probe()
1476 if (pdata->max_xfer_len) { in omap2_mcspi_probe()
1477 mcspi->max_xfer_len = pdata->max_xfer_len; in omap2_mcspi_probe()
1478 ctlr->max_transfer_size = omap2_mcspi_max_xfer_size; in omap2_mcspi_probe()
1481 mcspi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &r); in omap2_mcspi_probe()
1482 if (IS_ERR(mcspi->base)) { in omap2_mcspi_probe()
1483 status = PTR_ERR(mcspi->base); in omap2_mcspi_probe()
1486 mcspi->phys = r->start + regs_offset; in omap2_mcspi_probe()
1487 mcspi->base += regs_offset; in omap2_mcspi_probe()
1489 mcspi->dev = &pdev->dev; in omap2_mcspi_probe()
1491 INIT_LIST_HEAD(&mcspi->ctx.cs); in omap2_mcspi_probe()
1493 mcspi->dma_channels = devm_kcalloc(&pdev->dev, ctlr->num_chipselect, in omap2_mcspi_probe()
1496 if (mcspi->dma_channels == NULL) { in omap2_mcspi_probe()
1497 status = -ENOMEM; in omap2_mcspi_probe()
1501 for (i = 0; i < ctlr->num_chipselect; i++) { in omap2_mcspi_probe()
1502 sprintf(mcspi->dma_channels[i].dma_rx_ch_name, "rx%d", i); in omap2_mcspi_probe()
1503 sprintf(mcspi->dma_channels[i].dma_tx_ch_name, "tx%d", i); in omap2_mcspi_probe()
1506 &mcspi->dma_channels[i]); in omap2_mcspi_probe()
1507 if (status == -EPROBE_DEFER) in omap2_mcspi_probe()
1514 init_completion(&mcspi->txdone); in omap2_mcspi_probe()
1515 status = devm_request_irq(&pdev->dev, status, in omap2_mcspi_probe()
1516 omap2_mcspi_irq_handler, 0, pdev->name, in omap2_mcspi_probe()
1519 dev_err(&pdev->dev, "Cannot request IRQ"); in omap2_mcspi_probe()
1523 mcspi->ref_clk = devm_clk_get_optional_enabled(&pdev->dev, NULL); in omap2_mcspi_probe()
1524 if (IS_ERR(mcspi->ref_clk)) { in omap2_mcspi_probe()
1525 status = PTR_ERR(mcspi->ref_clk); in omap2_mcspi_probe()
1526 dev_err_probe(&pdev->dev, status, "Failed to get ref_clk"); in omap2_mcspi_probe()
1529 if (mcspi->ref_clk) in omap2_mcspi_probe()
1530 mcspi->ref_clk_hz = clk_get_rate(mcspi->ref_clk); in omap2_mcspi_probe()
1532 mcspi->ref_clk_hz = OMAP2_MCSPI_MAX_FREQ; in omap2_mcspi_probe()
1533 ctlr->max_speed_hz = mcspi->ref_clk_hz; in omap2_mcspi_probe()
1534 ctlr->min_speed_hz = mcspi->ref_clk_hz >> 15; in omap2_mcspi_probe()
1536 pm_runtime_use_autosuspend(&pdev->dev); in omap2_mcspi_probe()
1537 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT); in omap2_mcspi_probe()
1538 pm_runtime_enable(&pdev->dev); in omap2_mcspi_probe()
1544 status = devm_spi_register_controller(&pdev->dev, ctlr); in omap2_mcspi_probe()
1551 pm_runtime_dont_use_autosuspend(&pdev->dev); in omap2_mcspi_probe()
1552 pm_runtime_put_sync(&pdev->dev); in omap2_mcspi_probe()
1553 pm_runtime_disable(&pdev->dev); in omap2_mcspi_probe()
1567 pm_runtime_dont_use_autosuspend(mcspi->dev); in omap2_mcspi_remove()
1568 pm_runtime_put_sync(mcspi->dev); in omap2_mcspi_remove()
1569 pm_runtime_disable(&pdev->dev); in omap2_mcspi_remove()
1583 dev_warn(mcspi->dev, "%s: failed to set pins: %i\n", in omap2_mcspi_suspend()
1588 dev_warn(mcspi->dev, "%s: controller suspend failed: %i\n", in omap2_mcspi_suspend()
1602 dev_warn(mcspi->dev, "%s: controller resume failed: %i\n", in omap2_mcspi_resume()