4  *  Copyright (c) 2003-2007 Jocelyn Mayer
22 #include "exec/helper-proto.h"
23 #include "exec/exec-all.h"
25 #include "qemu/main-loop.h"
63     CPUState *cs = env_cpu(env);  in helper_store_purr()  local
66     if (ppc_cpu_lpar_single_threaded(cs)) {  in helper_store_purr()
71     THREAD_SIBLING_FOREACH(cs, ccs) {  in helper_store_purr()
72         CPUPPCState *cenv = &POWERPC_CPU(ccs)->env;  in helper_store_purr()
81     CPUState *cs = env_cpu(env);  in helper_store_tbl()  local
84     if (ppc_cpu_lpar_single_threaded(cs)) {  in helper_store_tbl()
89     THREAD_SIBLING_FOREACH(cs, ccs) {  in helper_store_tbl()
90         CPUPPCState *cenv = &POWERPC_CPU(ccs)->env;  in helper_store_tbl()
97     CPUState *cs = env_cpu(env);  in helper_store_tbu()  local
100     if (ppc_cpu_lpar_single_threaded(cs)) {  in helper_store_tbu()
105     THREAD_SIBLING_FOREACH(cs, ccs) {  in helper_store_tbu()
106         CPUPPCState *cenv = &POWERPC_CPU(ccs)->env;  in helper_store_tbu()
138     CPUState *cs = env_cpu(env);  in helper_store_hdecr()  local
141     if (ppc_cpu_lpar_single_threaded(cs)) {  in helper_store_hdecr()
146     THREAD_SIBLING_FOREACH(cs, ccs) {  in helper_store_hdecr()
147         CPUPPCState *cenv = &POWERPC_CPU(ccs)->env;  in helper_store_hdecr()
154     CPUState *cs = env_cpu(env);  in helper_store_vtb()  local
157     if (ppc_cpu_lpar_single_threaded(cs)) {  in helper_store_vtb()
162     THREAD_SIBLING_FOREACH(cs, ccs) {  in helper_store_vtb()
163         CPUPPCState *cenv = &POWERPC_CPU(ccs)->env;  in helper_store_vtb()
170     CPUState *cs = env_cpu(env);  in helper_store_tbu40()  local
173     if (ppc_cpu_lpar_single_threaded(cs)) {  in helper_store_tbu40()
178     THREAD_SIBLING_FOREACH(cs, ccs) {  in helper_store_tbu40()
179         CPUPPCState *cenv = &POWERPC_CPU(ccs)->env;  in helper_store_tbu40()
216  * qemu-user breaks with pnv headers, so they go under ifdefs for now.
227  * The TBST is the timebase state machine, which is a per-core machine that
237  * +----------------+----------------------------------+-----+
249  * - LOAD_TOD_MOD will also move states 2,6 to state 1, omitted from table
252  * - The ERROR state can be entered from most/all other states on invalid
262  * TB starts out synchronized across all vCPUs (hardware threads) in
268     return (tfmr & TFMR_TBST_ENCODED) >> (63 - 31);  in tfmr_get_tb_state()
276     tfmr |= (uint64_t)tbst << (63 - 31); /* move new state to state */  in tfmr_new_tb_state()
289     CPUState *cs = env_cpu(env);  in write_tfmr()  local
291     if (ppc_cpu_core_single_threaded(cs)) {  in write_tfmr()
292         env->spr[SPR_TFMR] = val;  in write_tfmr()
295         THREAD_SIBLING_FOREACH(cs, ccs) {  in write_tfmr()
296             CPUPPCState *cenv = &POWERPC_CPU(ccs)->env;  in write_tfmr()
297             cenv->spr[SPR_TFMR] = val;  in write_tfmr()
304     PnvCore *pc = pnv_cpu_state(cpu)->pnv_core;  in cpu_get_tbst()
306     if (pc->big_core && pc->tod_state.big_core_quirk) {  in cpu_get_tbst()
308         int core_id = CPU_CORE(pc)->core_id;  in cpu_get_tbst()
310             pc = pc->chip->cores[core_id & ~1];  in cpu_get_tbst()
314     return &pc->tod_state;  in cpu_get_tbst()
321     uint64_t tfmr = env->spr[SPR_TFMR];  in tb_state_machine_step()
328     if (tod_state->tb_sync_pulse_timer) {  in tb_state_machine_step()
329         tod_state->tb_sync_pulse_timer--;  in tb_state_machine_step()
335     if (tod_state->tb_state_timer) {  in tb_state_machine_step()
336         tod_state->tb_state_timer--;  in tb_state_machine_step()
353             tod_state->tb_state_timer = 3;  in tb_state_machine_step()
355             if (tod_state->tod_sent_to_tb) {  in tb_state_machine_step()
358                 tod_state->tb_ready_for_tod = 0;  in tb_state_machine_step()
359                 tod_state->tod_sent_to_tb = 0;  in tb_state_machine_step()
366             tod_state->tb_ready_for_tod = 0;  in tb_state_machine_step()
377     return env->spr[SPR_TFMR] | TFMR_TB_ECLIPZ;  in helper_load_tfmr()
384     uint64_t tfmr = env->spr[SPR_TFMR];  in helper_store_tfmr()
389         qemu_log_mask(LOG_UNIMP, "TFMR non-ECLIPZ mode not implemented\n");  in helper_store_tfmr()
392         goto out;  in helper_store_tfmr()
398     /* Several bits are clear-on-write, only one is implemented so far */  in helper_store_tfmr()
407     tod_state->tb_sync_pulse_timer = 1;  in helper_store_tfmr()
415         tod_state->tb_ready_for_tod = 0;  in helper_store_tfmr()
416         goto out;  in helper_store_tfmr()
429         tod_state->tb_ready_for_tod = 0;  in helper_store_tfmr()
430         tod_state->tod_sent_to_tb = 0;  in helper_store_tfmr()
431         goto out;  in helper_store_tfmr()
443         tod_state->tb_state_timer = 3;  in helper_store_tfmr()
447             tod_state->tb_ready_for_tod = 1;  in helper_store_tfmr()
448             tod_state->tb_state_timer = 3; /* arbitrary */  in helper_store_tfmr()
455             tod_state->tb_ready_for_tod = 0;  in helper_store_tfmr()
459 out:  in helper_store_tfmr()
467 /* XXX: to be improved to check access rights when in user-mode */
472     if (unlikely(env->dcr_env == NULL)) {  in helper_load_dcr()
481         ret = ppc_dcr_read(env->dcr_env, (uint32_t)dcrn, &val);  in helper_load_dcr()
496     if (unlikely(env->dcr_env == NULL)) {  in helper_store_dcr()
504         ret = ppc_dcr_write(env->dcr_env, (uint32_t)dcrn, (uint32_t)val);  in helper_store_dcr()