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/openbmc/qemu/target/arm/tcg/
H A Dcpu32.c2 * QEMU ARM TCG-only CPUs.
8 * SPDX-License-Identifier: GPL-2.0-or-later
12 #include "cpu.h"
13 #include "hw/core/tcg-cpu-ops.h"
22 /* Share AArch32 -cpu max features with AArch64. */
23 void aa32_max_features(ARMCPU *cpu) in aa32_max_features() argument
28 t = cpu->isar.id_isar5; in aa32_max_features()
30 t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); /* FEAT_SHA1 */ in aa32_max_features()
31 t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); /* FEAT_SHA256 */ in aa32_max_features()
32 t = FIELD_DP32(t, ID_ISAR5, CRC32, 1); in aa32_max_features()
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H A Dcpu64.c18 * <http://www.gnu.org/licenses/gpl-2.0.html>
23 #include "cpu.h"
26 #include "hw/qdev-properties.h"
29 #include "cpu-features.h"
34 ARMCPU *cpu = ARM_CPU(obj); in aarch64_a35_initfn() local
36 cpu->dtb_compatible = "arm,cortex-a35"; in aarch64_a35_initfn()
37 set_feature(&cpu->env, ARM_FEATURE_V8); in aarch64_a35_initfn()
38 set_feature(&cpu->env, ARM_FEATURE_NEON); in aarch64_a35_initfn()
39 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); in aarch64_a35_initfn()
40 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); in aarch64_a35_initfn()
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/openbmc/linux/tools/testing/selftests/cpu-hotplug/
H A Dcpu-on-off-test.sh2 # SPDX-License-Identifier: GPL-2.0
5 # Kselftest framework requirement - SKIP code is 4.
18 taskset -p 01 $$
20 SYSFS=`mount -t sysfs | head -1 | awk '{ print $3 }'`
22 if [ ! -d "$SYSFS" ]; then
27 if ! ls $SYSFS/devices/system/cpu/cpu* > /dev/null 2>&1; then
28 echo $msg cpu hotplug is not supported >&2
32 echo "CPU online/offline summary:"
33 online_cpus=`cat $SYSFS/devices/system/cpu/online`
34 online_max=${online_cpus##*-}
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/openbmc/linux/tools/power/cpupower/lib/
H A Dcpupower.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * (C) 2004-2009 Dominik Brodowski <linux@dominikbrodowski.de>
19 if (access(path, F_OK) == -1) in is_valid_path()
21 return 1; in is_valid_path()
30 if (fd == -1) in cpupower_read_sysfs()
33 numread = read(fd, buf, buflen - 1); in cpupower_read_sysfs()
34 if (numread < 1) { in cpupower_read_sysfs()
51 if (fd == -1) in cpupower_write_sysfs()
54 numwritten = write(fd, buf, buflen - 1); in cpupower_write_sysfs()
55 if (numwritten < 1) { in cpupower_write_sysfs()
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/openbmc/linux/Documentation/arch/x86/
H A Dtopology.rst1 .. SPDX-License-Identifier: GPL-2.0
11 The architecture-agnostic topology definitions are in
12 Documentation/admin-guide/cputopology.rst. This file holds x86-specific
17 Needless to say, code should use the generic functions - this file is *only*
35 - packages
36 - cores
37 - threads
48 Package-related topology information in the kernel:
50 - cpuinfo_x86.x86_max_cores:
54 - cpuinfo_x86.x86_max_dies:
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/openbmc/linux/tools/perf/util/
H A Dcpumap.c1 // SPDX-License-Identifier: GPL-2.0
22 * CPU number.
30 __u32 bit_mask32 = 1U << (i & 31); in perf_record_cpu_map_data__test_bit()
32 __u64 bit_mask64 = ((__u64)1) << (i & 63); in perf_record_cpu_map_data__test_bit()
34 return (data->mask32_data.long_size == 4) in perf_record_cpu_map_data__test_bit()
35 ? (bit_word32 < data->mask32_data.nr) && in perf_record_cpu_map_data__test_bit()
36 (data->mask32_data.mask[bit_word32] & bit_mask32) != 0 in perf_record_cpu_map_data__test_bit()
37 : (bit_word64 < data->mask64_data.nr) && in perf_record_cpu_map_data__test_bit()
38 (data->mask64_data.mask[bit_word64] & bit_mask64) != 0; in perf_record_cpu_map_data__test_bit()
41 /* Read ith mask value from data into the given 64-bit sized bitmap */
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/openbmc/linux/arch/arm/mach-bcm/
H A Dplatsmp-brcmstb.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Broadcom STB CPU SMP and hotplug support for ARM
5 * Copyright (C) 2013-2014 Broadcom Corporation
22 #include <asm/mach-types.h>
27 ZONE_MAN_RESET_CNTL_MASK = BIT(1),
40 CPU0_PWR_ZONE_CTRL_REG = 1,
52 * We must quiesce a dying CPU before it can be killed by the boot CPU. Because
59 static int per_cpu_sw_state_rd(u32 cpu) in per_cpu_sw_state_rd() argument
61 sync_cache_r(SHIFT_PERCPU_PTR(&per_cpu_sw_state, per_cpu_offset(cpu))); in per_cpu_sw_state_rd()
62 return per_cpu(per_cpu_sw_state, cpu); in per_cpu_sw_state_rd()
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/openbmc/linux/tools/testing/selftests/net/forwarding/
H A Dtsn_lib.sh2 # SPDX-License-Identifier: GPL-2.0
3 # Copyright 2021-2022 NXP
10 ISOCHRON_CPU=1
13 # https://github.com/vladimiroltean/tsn-scripts
14 # WARNING: isochron versions pre-1.0 are unstable,
25 local uds_address=$1
28 if ! [ -z "${uds_address}" ]; then
29 extra_args="${extra_args} -z ${uds_address}"
34 chrt -f 10 phc2sys -m \
35 -a -rr \
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/openbmc/linux/tools/power/x86/x86_energy_perf_policy/
H A Dx86_energy_perf_policy.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * x86_energy_perf_policy -- set the energy versus performance
7 * Copyright (c) 2010 - 2017 Intel Corporation.
30 #define OPTARG_NORMAL (INT_MAX - 1)
31 #define OPTARG_POWER (INT_MAX - 2)
32 #define OPTARG_BALANCE_POWER (INT_MAX - 3)
33 #define OPTARG_BALANCE_PERFORMANCE (INT_MAX - 4)
34 #define OPTARG_PERFORMANCE (INT_MAX - 5)
94 #define PATH_TO_CPU "/sys/devices/system/cpu/"
103 fprintf(stderr, "scope: --cpu cpu-list [--hwp-use-pkg #] | --pkg pkg-list\n"); in usage()
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/openbmc/linux/tools/perf/tests/
H A Dtopology.c1 // SPDX-License-Identifier: GPL-2.0
14 #define TEMPL "/tmp/perf-test-XXXXXX"
26 return -1; in get_temp()
44 session->evlist = evlist__new_default(); in session_write_header()
45 TEST_ASSERT_VAL("can't get evlist", session->evlist); in session_write_header()
47 perf_header__set_feat(&session->header, HEADER_CPU_TOPOLOGY); in session_write_header()
48 perf_header__set_feat(&session->header, HEADER_NRCPUS); in session_write_header()
49 perf_header__set_feat(&session->header, HEADER_ARCH); in session_write_header()
51 session->header.data_size += DATA_SIZE; in session_write_header()
54 !perf_session__write_header(session, session->evlist, data.file.fd, true)); in session_write_header()
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/openbmc/linux/tools/perf/pmu-events/arch/s390/cf_z16/
H A Dextended.json3 "Unit": "CPU-M-CF",
6 "BriefDescription": "L1D Read-only Exclusive Writes",
7 …blicDescription": "A directory write to the Level-1 Data cache where the line was originally in a …
10 "Unit": "CPU-M-CF",
14 …Translation Lookaside Buffer 2 (TLB2) and the request was made by the Level-1 Data cache. This is …
17 "Unit": "CPU-M-CF",
21 …ress for a request made by the Level-1 Data cache. Incremented by one for every TLB2 miss in progr…
24 "Unit": "CPU-M-CF",
28 … into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page…
31 "Unit": "CPU-M-CF",
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/openbmc/qemu/hw/intc/
H A Darm_gic.c4 * Copyright (c) 2006-2007 CodeSourcery.
11 * controller, MPCore distributed interrupt controller and ARMv7-M
14 * (1) as a standalone file to produce a sysbus device which is a GIC
26 #include "hw/core/cpu.h"
36 #define DEBUG_GIC_GATE 1
61 if (!qtest_enabled() && s->num_cpu > 1) { in gic_get_current_cpu()
62 return current_cpu->cpu_index; in gic_get_current_cpu()
77 return s->revision == 2 || s->security_extn; in gic_has_groups()
80 static inline bool gic_cpu_ns_access(GICState *s, int cpu, MemTxAttrs attrs) in gic_cpu_ns_access() argument
82 return !gic_is_vcpu(cpu) && s->security_extn && !attrs.secure; in gic_cpu_ns_access()
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/openbmc/qemu/docs/system/s390x/
H A Dcpu-topology.rst1 .. _cpu-topology-s390x:
3 CPU topology on s390x
6 Since QEMU 8.2, CPU topology on s390x provides up to 3 levels of
8 tree-shaped hierarchy.
10 The socket container has one or more CPU entries.
11 Each of these CPU entries consists of a bitmap and three CPU attributes:
13 - CPU type
14 - entitlement
15 - dedication
17 Each bit set in the bitmap correspond to a core-id of a vCPU with matching
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/openbmc/qemu/target/i386/hvf/
H A Dhvf.c30 * 1. Redistributions of source code must retain the above copyright
50 #include "qemu/error-report.h"
59 #include "hvf-i386.h"
75 #include "qemu/main-loop.h"
77 #include "target/i386/cpu.h"
81 void vmx_update_tpr(CPUState *cpu) in vmx_update_tpr() argument
84 X86CPU *x86_cpu = X86_CPU(cpu); in vmx_update_tpr()
85 int tpr = cpu_get_apic_tpr(x86_cpu->apic_state) << 4; in vmx_update_tpr()
86 int irr = apic_get_highest_priority_irr(x86_cpu->apic_state); in vmx_update_tpr()
88 wreg(cpu->accel->fd, HV_X86_TPR, tpr); in vmx_update_tpr()
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H A Dx86.h127 uint64_t s:1;
129 uint64_t p:1;
131 uint64_t avl:1;
132 uint64_t l:1;
133 uint64_t db:1;
134 uint64_t g:1;
140 return (uint32_t)((desc->base2 << 24) | (desc->base1 << 16) | desc->base0); in x86_segment_base()
146 desc->base2 = base >> 24; in x86_set_segment_base()
147 desc->base1 = (base >> 16) & 0xff; in x86_set_segment_base()
148 desc->base0 = base & 0xffff; in x86_set_segment_base()
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/openbmc/linux/arch/powerpc/kernel/
H A Dsmp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 * PowerPC-64 Support added by Dave Engebretsen, Peter Bergner, and
29 #include <linux/cpu.h>
75 /* State of each CPU during hotplug phases */
106 #define THREAD_GROUP_SHARE_L1 1
125 * On big-cores system, thread_group_l1_cache_map for each CPU corresponds to
126 * the set its siblings that share the L1-cache.
131 * On some big-cores system, thread_group_l2_cache_map for each CPU
133 * L2-cache.
138 * On P10, thread_group_l3_cache_map for each CPU is equal to the
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/openbmc/qemu/docs/specs/
H A Dacpi_cpu_hotplug.rst1 QEMU<->ACPI BIOS CPU hotplug interface
4 QEMU supports CPU hotplug via ACPI. This document
7 ACPI BIOS GPE.2 handler is dedicated for notifying OS about CPU hot-add
8 and hot-remove events.
11 Legacy ACPI CPU hotplug interface registers
12 -------------------------------------------
14 CPU present bitmap for:
16 - ICH9-LPC (IO port 0x0cd8-0xcf7, 1-byte access)
17 - PIIX-PM (IO port 0xaf00-0xaf1f, 1-byte access)
18 - One bit per CPU. Bit position reflects corresponding CPU APIC ID. Read-only.
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/openbmc/qemu/hw/ppc/
H A Dspapr_cpu_core.c2 * sPAPR CPU core device, acts as container of CPU thread devices.
7 * See the COPYING file in the top-level directory.
11 #include "hw/cpu/core.h"
13 #include "hw/qdev-properties.h"
15 #include "target/ppc/cpu.h"
22 #include "target/ppc/mmu-hash64.h"
23 #include "target/ppc/power8-pmu.h"
27 #include "qemu/error-report.h"
29 static void spapr_reset_vcpu(PowerPCCPU *cpu) in spapr_reset_vcpu() argument
31 CPUState *cs = CPU(cpu); in spapr_reset_vcpu()
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/openbmc/linux/tools/perf/pmu-events/arch/s390/cf_z10/
H A Dbasic.json3 "Unit": "CPU-M-CF",
7 …tion": "This counter counts the total number of CPU cycles, excluding the number of cycles while t…
10 "Unit": "CPU-M-CF",
11 "EventCode": "1",
14 "PublicDescription": "This counter counts the total number of instructions executed by the CPU."
17 "Unit": "CPU-M-CF",
20 "BriefDescription": "Level-1 I-Cache Directory Write Count",
21 …Description": "This counter counts the total number of level-1 instruction-cache or unified-cache …
24 "Unit": "CPU-M-CF",
27 "BriefDescription": "Level-1 I-Cache Penalty Cycle Count",
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/openbmc/linux/tools/perf/pmu-events/arch/s390/cf_z13/
H A Dbasic.json3 "Unit": "CPU-M-CF",
7 …tion": "This counter counts the total number of CPU cycles, excluding the number of cycles while t…
10 "Unit": "CPU-M-CF",
11 "EventCode": "1",
14 "PublicDescription": "This counter counts the total number of instructions executed by the CPU."
17 "Unit": "CPU-M-CF",
20 "BriefDescription": "Level-1 I-Cache Directory Write Count",
21 …Description": "This counter counts the total number of level-1 instruction-cache or unified-cache …
24 "Unit": "CPU-M-CF",
27 "BriefDescription": "Level-1 I-Cache Penalty Cycle Count",
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/openbmc/linux/tools/perf/pmu-events/arch/s390/cf_z196/
H A Dbasic.json3 "Unit": "CPU-M-CF",
7 …tion": "This counter counts the total number of CPU cycles, excluding the number of cycles while t…
10 "Unit": "CPU-M-CF",
11 "EventCode": "1",
14 "PublicDescription": "This counter counts the total number of instructions executed by the CPU."
17 "Unit": "CPU-M-CF",
20 "BriefDescription": "Level-1 I-Cache Directory Write Count",
21 …Description": "This counter counts the total number of level-1 instruction-cache or unified-cache …
24 "Unit": "CPU-M-CF",
27 "BriefDescription": "Level-1 I-Cache Penalty Cycle Count",
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/openbmc/linux/tools/perf/pmu-events/arch/s390/cf_zec12/
H A Dbasic.json3 "Unit": "CPU-M-CF",
7 …tion": "This counter counts the total number of CPU cycles, excluding the number of cycles while t…
10 "Unit": "CPU-M-CF",
11 "EventCode": "1",
14 "PublicDescription": "This counter counts the total number of instructions executed by the CPU."
17 "Unit": "CPU-M-CF",
20 "BriefDescription": "Level-1 I-Cache Directory Write Count",
21 …Description": "This counter counts the total number of level-1 instruction-cache or unified-cache …
24 "Unit": "CPU-M-CF",
27 "BriefDescription": "Level-1 I-Cache Penalty Cycle Count",
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/openbmc/qemu/
H A Dcpu-common.c2 * CPU thread main loop - common bits for user and system mode emulation
4 * Copyright (c) 2003-2005 Fabrice Bellard
21 #include "qemu/main-loop.h"
22 #include "exec/cpu-common.h"
23 #include "hw/core/cpu.h"
26 #include "trace/trace-root.h"
33 /* >= 1 if a thread is inside start_exclusive/end_exclusive. Written
67 if (some_cpu->cpu_index >= max_cpu_index) { in cpu_get_free_index()
68 max_cpu_index = some_cpu->cpu_index + 1; in cpu_get_free_index()
82 void cpu_list_add(CPUState *cpu) in cpu_list_add() argument
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/openbmc/linux/Documentation/devicetree/bindings/cpu/
H A Dcpu-capacity.txt2 CPU capacity bindings
6 1 - Introduction
15 2 - CPU capacity definition
18 CPU capacity is a number that provides the scheduler information about CPUs
19 heterogeneity. Such heterogeneity can come from micro-architectural differences
23 capture a first-order approximation of the relative performance of CPUs.
25 CPU capacities are obtained by running a suitable benchmark. This binding makes
29 * A "single-threaded" or CPU affine benchmark
30 * Divided by the running frequency of the CPU executing the benchmark
31 * Not subject to dynamic frequency scaling of the CPU
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/openbmc/linux/arch/arm64/boot/dts/hisilicon/
H A Dhip07.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip07-d05";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
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