docs/specs/acpi_cpu_hotplug.rst

1 QEMU<->ACPI BIOS CPU hotplug interface
4 QEMU supports CPU hotplug via ACPI. This document
7 ACPI BIOS GPE.2 handler is dedicated for notifying OS about CPU hot-add
8 and hot-remove events.
11 Legacy ACPI CPU hotplug interface registers
12 -------------------------------------------
14 CPU present bitmap for:
16 - ICH9-LPC (IO port 0x0cd8-0xcf7, 1-byte access)
17 - PIIX-PM  (IO port 0xaf00-0xaf1f, 1-byte access)
18 - One bit per CPU. Bit position reflects corresponding CPU APIC ID. Read-only.
19 - The first DWORD in bitmap is used in write mode to switch from legacy
20   to modern CPU hotplug interface, write 0 into it to do switch.
22 QEMU sets corresponding CPU bit on hot-add event and issues SCI
23 with GPE.2 event set. CPU present map is read by ACPI BIOS GPE.2 handler
24 to notify OS about CPU hot-add events. CPU hot-remove isn't supported.
27 Modern ACPI CPU hotplug interface registers
28 -------------------------------------------
32 - ICH9-LPC IO port 0x0cd8
33 - PIIX-PM  IO port 0xaf00
37 - ACPI_CPU_HOTPLUG_REG_LEN = 12
39 All accesses to registers described below, imply little-endian byte order.
43 - write accesses are ignored
44 - read accesses return all bits set to 0.
46 The last stored value in 'CPU selector' must refer to a possible CPU, otherwise
48 - reads from any register return 0
49 - writes to any other register are ignored until valid value is stored into it
51 On QEMU start, 'CPU selector' is initialized to a valid value, on reset it
57 offset [0x0-0x3]
65     upper 32 bits of architecture specific CPU ID value
70   CPU device status fields: (1 byte access)
76   1:
87     if set to 1, OSPM requests firmware to perform device eject.
88   5-7:
91 offset [0x5-0x7]
100     contains 'CPU selector' value of a CPU with pending event[s]
102     lower 32 bits of architecture specific CPU ID value
110 offset [0x0-0x3]
111   CPU selector: (DWORD access)
113   Selects active CPU device. All following accesses to other
114   registers will read/store data from/to selected CPU.
118   CPU device control fields: (1 byte access)
124   1:
125     if set to 1 clears device insert event, set by OSPM
127     selected CPU device
129     if set to 1 clears device remove event, set by OSPM
131     selected CPU device.
133     if set to 1 initiates device eject, set by OSPM when it
134     triggers CPU device removal and calls _EJ0 method or by firmware
138     if set to 1, OSPM hands over device eject to firmware.
141     it's asked firmware to perform CPU device eject.
142   5-7:
146   Command field: (1 byte access)
151     selects a CPU device with inserting/removing events and
153     selected CPU ('CPU selector' value).
154     If no CPU with events found, the current 'CPU selector' doesn't
157   1:
165     architecture specific CPU ID value for currently selected CPU.
169 offset [0x6-0x7]
177   1:
187 ----------------
189 (x86) Detecting and enabling modern CPU hotplug interface
192 QEMU starts with legacy CPU hotplug interface enabled. Detecting and
193 switching to modern interface is based on the 2 legacy CPU hotplug features:
195 #. Writes into CPU bitmap are ignored.
196 #. CPU bitmap always has bit #0 set, corresponding to boot CPU.
198 Use following steps to detect and enable modern CPU hotplug interface:
200 #. Store 0x0 to the 'CPU selector' register, attempting to switch to modern mode
201 #. Store 0x0 to the 'CPU selector' register, to ensure valid selector value
205    Otherwise legacy or no CPU hotplug interface available
207 Get a cpu with pending event
210 #. Store 0x0 to the 'CPU selector' register.
212 #. Read the 'CPU device status fields' register.
213 #. If both bit #1 and bit #2 are clear in the value read, there is no CPU
214    with a pending event and selected CPU remains unchanged.
216    selector of the CPU with the pending event (which is already selected).
221 #. Set the present CPU count to 0.
223 #. Store 0x0 to the 'CPU selector' register, to ensure that it's in
226    register return 'CPU selector' value of selected CPU
227 #. Read the 'CPU device status fields' register.
228 #. If bit #0 is set, increment the present CPU count.
230 #. Store the iterator to the 'CPU selector' register.
233 #. Otherwise store 0x0 to the 'CPU selector' register, to put it