Lines Matching +full:cpu +full:- +full:1
2 * QEMU ARM TCG-only CPUs.
8 * SPDX-License-Identifier: GPL-2.0-or-later
12 #include "cpu.h"
13 #include "hw/core/tcg-cpu-ops.h"
22 /* Share AArch32 -cpu max features with AArch64. */
23 void aa32_max_features(ARMCPU *cpu) in aa32_max_features() argument
28 t = cpu->isar.id_isar5; in aa32_max_features()
30 t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); /* FEAT_SHA1 */ in aa32_max_features()
31 t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); /* FEAT_SHA256 */ in aa32_max_features()
32 t = FIELD_DP32(t, ID_ISAR5, CRC32, 1); in aa32_max_features()
33 t = FIELD_DP32(t, ID_ISAR5, RDM, 1); /* FEAT_RDM */ in aa32_max_features()
34 t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); /* FEAT_FCMA */ in aa32_max_features()
35 cpu->isar.id_isar5 = t; in aa32_max_features()
37 t = cpu->isar.id_isar6; in aa32_max_features()
38 t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); /* FEAT_JSCVT */ in aa32_max_features()
39 t = FIELD_DP32(t, ID_ISAR6, DP, 1); /* Feat_DotProd */ in aa32_max_features()
40 t = FIELD_DP32(t, ID_ISAR6, FHM, 1); /* FEAT_FHM */ in aa32_max_features()
41 t = FIELD_DP32(t, ID_ISAR6, SB, 1); /* FEAT_SB */ in aa32_max_features()
42 t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); /* FEAT_SPECRES */ in aa32_max_features()
43 t = FIELD_DP32(t, ID_ISAR6, BF16, 1); /* FEAT_AA32BF16 */ in aa32_max_features()
44 t = FIELD_DP32(t, ID_ISAR6, I8MM, 1); /* FEAT_AA32I8MM */ in aa32_max_features()
45 cpu->isar.id_isar6 = t; in aa32_max_features()
47 t = cpu->isar.mvfr1; in aa32_max_features()
50 cpu->isar.mvfr1 = t; in aa32_max_features()
52 t = cpu->isar.mvfr2; in aa32_max_features()
55 cpu->isar.mvfr2 = t; in aa32_max_features()
57 t = cpu->isar.id_mmfr3; in aa32_max_features()
59 cpu->isar.id_mmfr3 = t; in aa32_max_features()
61 t = cpu->isar.id_mmfr4; in aa32_max_features()
63 t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ in aa32_max_features()
64 t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */ in aa32_max_features()
65 t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX */ in aa32_max_features()
67 cpu->isar.id_mmfr4 = t; in aa32_max_features()
69 t = cpu->isar.id_mmfr5; in aa32_max_features()
71 cpu->isar.id_mmfr5 = t; in aa32_max_features()
73 t = cpu->isar.id_pfr0; in aa32_max_features()
75 t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */ in aa32_max_features()
76 t = FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */ in aa32_max_features()
77 cpu->isar.id_pfr0 = t; in aa32_max_features()
79 t = cpu->isar.id_pfr2; in aa32_max_features()
80 t = FIELD_DP32(t, ID_PFR2, CSV3, 1); /* FEAT_CSV3 */ in aa32_max_features()
81 t = FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */ in aa32_max_features()
82 cpu->isar.id_pfr2 = t; in aa32_max_features()
84 t = cpu->isar.id_dfr0; in aa32_max_features()
88 cpu->isar.id_dfr0 = t; in aa32_max_features()
94 t = FIELD_DP32(t, DBGDIDR, SE_IMP, 1); in aa32_max_features()
95 t = FIELD_DP32(t, DBGDIDR, NSUHD_IMP, 1); in aa32_max_features()
97 t = FIELD_DP32(t, DBGDIDR, CTX_CMPS, 1); in aa32_max_features()
100 cpu->isar.dbgdidr = t; in aa32_max_features()
104 t = FIELD_DP32(t, DBGDEVID, WPADDRMASK, 1); in aa32_max_features()
107 t = FIELD_DP32(t, DBGDEVID, VIRTEXTNS, 1); in aa32_max_features()
108 t = FIELD_DP32(t, DBGDEVID, DOUBLELOCK, 1); in aa32_max_features()
111 cpu->isar.dbgdevid = t; in aa32_max_features()
116 cpu->isar.dbgdevid1 = t; in aa32_max_features()
118 t = cpu->isar.id_dfr1; in aa32_max_features()
119 t = FIELD_DP32(t, ID_DFR1, HPMN0, 1); /* FEAT_HPMN0 */ in aa32_max_features()
120 cpu->isar.id_dfr1 = t; in aa32_max_features()
123 /* CPU models. These are not needed for the AArch64 linux-user build. */
128 ARMCPU *cpu = ARM_CPU(obj); in arm926_initfn() local
130 cpu->dtb_compatible = "arm,arm926"; in arm926_initfn()
131 set_feature(&cpu->env, ARM_FEATURE_V5); in arm926_initfn()
132 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); in arm926_initfn()
133 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); in arm926_initfn()
134 cpu->midr = 0x41069265; in arm926_initfn()
135 cpu->reset_fpsid = 0x41011090; in arm926_initfn()
136 cpu->ctr = 0x1dd20d2; in arm926_initfn()
137 cpu->reset_sctlr = 0x00090078; in arm926_initfn()
143 cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1); in arm926_initfn()
148 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); in arm926_initfn()
149 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1); in arm926_initfn()
150 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1); in arm926_initfn()
155 ARMCPU *cpu = ARM_CPU(obj); in arm946_initfn() local
157 cpu->dtb_compatible = "arm,arm946"; in arm946_initfn()
158 set_feature(&cpu->env, ARM_FEATURE_V5); in arm946_initfn()
159 set_feature(&cpu->env, ARM_FEATURE_PMSA); in arm946_initfn()
160 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); in arm946_initfn()
161 cpu->midr = 0x41059461; in arm946_initfn()
162 cpu->ctr = 0x0f004006; in arm946_initfn()
163 cpu->reset_sctlr = 0x00000078; in arm946_initfn()
168 ARMCPU *cpu = ARM_CPU(obj); in arm1026_initfn() local
170 cpu->dtb_compatible = "arm,arm1026"; in arm1026_initfn()
171 set_feature(&cpu->env, ARM_FEATURE_V5); in arm1026_initfn()
172 set_feature(&cpu->env, ARM_FEATURE_AUXCR); in arm1026_initfn()
173 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); in arm1026_initfn()
174 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); in arm1026_initfn()
175 cpu->midr = 0x4106a262; in arm1026_initfn()
176 cpu->reset_fpsid = 0x410110a0; in arm1026_initfn()
177 cpu->ctr = 0x1dd20d2; in arm1026_initfn()
178 cpu->reset_sctlr = 0x00090078; in arm1026_initfn()
179 cpu->reset_auxcr = 1; in arm1026_initfn()
185 cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1); in arm1026_initfn()
190 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); in arm1026_initfn()
191 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1); in arm1026_initfn()
192 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1); in arm1026_initfn()
195 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */ in arm1026_initfn()
197 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, in arm1026_initfn()
202 define_one_arm_cp_reg(cpu, &ifar); in arm1026_initfn()
208 ARMCPU *cpu = ARM_CPU(obj); in arm1136_r2_initfn() local
218 cpu->dtb_compatible = "arm,arm1136"; in arm1136_r2_initfn()
219 set_feature(&cpu->env, ARM_FEATURE_V6); in arm1136_r2_initfn()
220 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); in arm1136_r2_initfn()
221 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); in arm1136_r2_initfn()
222 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); in arm1136_r2_initfn()
223 cpu->midr = 0x4107b362; in arm1136_r2_initfn()
224 cpu->reset_fpsid = 0x410120b4; in arm1136_r2_initfn()
225 cpu->isar.mvfr0 = 0x11111111; in arm1136_r2_initfn()
226 cpu->isar.mvfr1 = 0x00000000; in arm1136_r2_initfn()
227 cpu->ctr = 0x1dd20d2; in arm1136_r2_initfn()
228 cpu->reset_sctlr = 0x00050078; in arm1136_r2_initfn()
229 cpu->isar.id_pfr0 = 0x111; in arm1136_r2_initfn()
230 cpu->isar.id_pfr1 = 0x1; in arm1136_r2_initfn()
231 cpu->isar.id_dfr0 = 0x2; in arm1136_r2_initfn()
232 cpu->id_afr0 = 0x3; in arm1136_r2_initfn()
233 cpu->isar.id_mmfr0 = 0x01130003; in arm1136_r2_initfn()
234 cpu->isar.id_mmfr1 = 0x10030302; in arm1136_r2_initfn()
235 cpu->isar.id_mmfr2 = 0x01222110; in arm1136_r2_initfn()
236 cpu->isar.id_isar0 = 0x00140011; in arm1136_r2_initfn()
237 cpu->isar.id_isar1 = 0x12002111; in arm1136_r2_initfn()
238 cpu->isar.id_isar2 = 0x11231111; in arm1136_r2_initfn()
239 cpu->isar.id_isar3 = 0x01102131; in arm1136_r2_initfn()
240 cpu->isar.id_isar4 = 0x141; in arm1136_r2_initfn()
241 cpu->reset_auxcr = 7; in arm1136_r2_initfn()
246 ARMCPU *cpu = ARM_CPU(obj); in arm1136_initfn() local
248 cpu->dtb_compatible = "arm,arm1136"; in arm1136_initfn()
249 set_feature(&cpu->env, ARM_FEATURE_V6K); in arm1136_initfn()
250 set_feature(&cpu->env, ARM_FEATURE_V6); in arm1136_initfn()
251 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); in arm1136_initfn()
252 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); in arm1136_initfn()
253 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); in arm1136_initfn()
254 cpu->midr = 0x4117b363; in arm1136_initfn()
255 cpu->reset_fpsid = 0x410120b4; in arm1136_initfn()
256 cpu->isar.mvfr0 = 0x11111111; in arm1136_initfn()
257 cpu->isar.mvfr1 = 0x00000000; in arm1136_initfn()
258 cpu->ctr = 0x1dd20d2; in arm1136_initfn()
259 cpu->reset_sctlr = 0x00050078; in arm1136_initfn()
260 cpu->isar.id_pfr0 = 0x111; in arm1136_initfn()
261 cpu->isar.id_pfr1 = 0x1; in arm1136_initfn()
262 cpu->isar.id_dfr0 = 0x2; in arm1136_initfn()
263 cpu->id_afr0 = 0x3; in arm1136_initfn()
264 cpu->isar.id_mmfr0 = 0x01130003; in arm1136_initfn()
265 cpu->isar.id_mmfr1 = 0x10030302; in arm1136_initfn()
266 cpu->isar.id_mmfr2 = 0x01222110; in arm1136_initfn()
267 cpu->isar.id_isar0 = 0x00140011; in arm1136_initfn()
268 cpu->isar.id_isar1 = 0x12002111; in arm1136_initfn()
269 cpu->isar.id_isar2 = 0x11231111; in arm1136_initfn()
270 cpu->isar.id_isar3 = 0x01102131; in arm1136_initfn()
271 cpu->isar.id_isar4 = 0x141; in arm1136_initfn()
272 cpu->reset_auxcr = 7; in arm1136_initfn()
277 ARMCPU *cpu = ARM_CPU(obj); in arm1176_initfn() local
279 cpu->dtb_compatible = "arm,arm1176"; in arm1176_initfn()
280 set_feature(&cpu->env, ARM_FEATURE_V6K); in arm1176_initfn()
281 set_feature(&cpu->env, ARM_FEATURE_VAPA); in arm1176_initfn()
282 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); in arm1176_initfn()
283 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); in arm1176_initfn()
284 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); in arm1176_initfn()
285 set_feature(&cpu->env, ARM_FEATURE_EL3); in arm1176_initfn()
286 cpu->midr = 0x410fb767; in arm1176_initfn()
287 cpu->reset_fpsid = 0x410120b5; in arm1176_initfn()
288 cpu->isar.mvfr0 = 0x11111111; in arm1176_initfn()
289 cpu->isar.mvfr1 = 0x00000000; in arm1176_initfn()
290 cpu->ctr = 0x1dd20d2; in arm1176_initfn()
291 cpu->reset_sctlr = 0x00050078; in arm1176_initfn()
292 cpu->isar.id_pfr0 = 0x111; in arm1176_initfn()
293 cpu->isar.id_pfr1 = 0x11; in arm1176_initfn()
294 cpu->isar.id_dfr0 = 0x33; in arm1176_initfn()
295 cpu->id_afr0 = 0; in arm1176_initfn()
296 cpu->isar.id_mmfr0 = 0x01130003; in arm1176_initfn()
297 cpu->isar.id_mmfr1 = 0x10030302; in arm1176_initfn()
298 cpu->isar.id_mmfr2 = 0x01222100; in arm1176_initfn()
299 cpu->isar.id_isar0 = 0x0140011; in arm1176_initfn()
300 cpu->isar.id_isar1 = 0x12002111; in arm1176_initfn()
301 cpu->isar.id_isar2 = 0x11231121; in arm1176_initfn()
302 cpu->isar.id_isar3 = 0x01102131; in arm1176_initfn()
303 cpu->isar.id_isar4 = 0x01141; in arm1176_initfn()
304 cpu->reset_auxcr = 7; in arm1176_initfn()
309 ARMCPU *cpu = ARM_CPU(obj); in arm11mpcore_initfn() local
311 cpu->dtb_compatible = "arm,arm11mpcore"; in arm11mpcore_initfn()
312 set_feature(&cpu->env, ARM_FEATURE_V6K); in arm11mpcore_initfn()
313 set_feature(&cpu->env, ARM_FEATURE_VAPA); in arm11mpcore_initfn()
314 set_feature(&cpu->env, ARM_FEATURE_MPIDR); in arm11mpcore_initfn()
315 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); in arm11mpcore_initfn()
316 cpu->midr = 0x410fb022; in arm11mpcore_initfn()
317 cpu->reset_fpsid = 0x410120b4; in arm11mpcore_initfn()
318 cpu->isar.mvfr0 = 0x11111111; in arm11mpcore_initfn()
319 cpu->isar.mvfr1 = 0x00000000; in arm11mpcore_initfn()
320 cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ in arm11mpcore_initfn()
321 cpu->isar.id_pfr0 = 0x111; in arm11mpcore_initfn()
322 cpu->isar.id_pfr1 = 0x1; in arm11mpcore_initfn()
323 cpu->isar.id_dfr0 = 0; in arm11mpcore_initfn()
324 cpu->id_afr0 = 0x2; in arm11mpcore_initfn()
325 cpu->isar.id_mmfr0 = 0x01100103; in arm11mpcore_initfn()
326 cpu->isar.id_mmfr1 = 0x10020302; in arm11mpcore_initfn()
327 cpu->isar.id_mmfr2 = 0x01222000; in arm11mpcore_initfn()
328 cpu->isar.id_isar0 = 0x00100011; in arm11mpcore_initfn()
329 cpu->isar.id_isar1 = 0x12002111; in arm11mpcore_initfn()
330 cpu->isar.id_isar2 = 0x11221011; in arm11mpcore_initfn()
331 cpu->isar.id_isar3 = 0x01102131; in arm11mpcore_initfn()
332 cpu->isar.id_isar4 = 0x141; in arm11mpcore_initfn()
333 cpu->reset_auxcr = 1; in arm11mpcore_initfn()
337 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
339 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
345 ARMCPU *cpu = ARM_CPU(obj); in cortex_a8_initfn() local
347 cpu->dtb_compatible = "arm,cortex-a8"; in cortex_a8_initfn()
348 set_feature(&cpu->env, ARM_FEATURE_V7); in cortex_a8_initfn()
349 set_feature(&cpu->env, ARM_FEATURE_NEON); in cortex_a8_initfn()
350 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); in cortex_a8_initfn()
351 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); in cortex_a8_initfn()
352 set_feature(&cpu->env, ARM_FEATURE_EL3); in cortex_a8_initfn()
353 set_feature(&cpu->env, ARM_FEATURE_PMU); in cortex_a8_initfn()
354 cpu->midr = 0x410fc080; in cortex_a8_initfn()
355 cpu->reset_fpsid = 0x410330c0; in cortex_a8_initfn()
356 cpu->isar.mvfr0 = 0x11110222; in cortex_a8_initfn()
357 cpu->isar.mvfr1 = 0x00011111; in cortex_a8_initfn()
358 cpu->ctr = 0x82048004; in cortex_a8_initfn()
359 cpu->reset_sctlr = 0x00c50078; in cortex_a8_initfn()
360 cpu->isar.id_pfr0 = 0x1031; in cortex_a8_initfn()
361 cpu->isar.id_pfr1 = 0x11; in cortex_a8_initfn()
362 cpu->isar.id_dfr0 = 0x400; in cortex_a8_initfn()
363 cpu->id_afr0 = 0; in cortex_a8_initfn()
364 cpu->isar.id_mmfr0 = 0x31100003; in cortex_a8_initfn()
365 cpu->isar.id_mmfr1 = 0x20000000; in cortex_a8_initfn()
366 cpu->isar.id_mmfr2 = 0x01202000; in cortex_a8_initfn()
367 cpu->isar.id_mmfr3 = 0x11; in cortex_a8_initfn()
368 cpu->isar.id_isar0 = 0x00101111; in cortex_a8_initfn()
369 cpu->isar.id_isar1 = 0x12112111; in cortex_a8_initfn()
370 cpu->isar.id_isar2 = 0x21232031; in cortex_a8_initfn()
371 cpu->isar.id_isar3 = 0x11112131; in cortex_a8_initfn()
372 cpu->isar.id_isar4 = 0x00111142; in cortex_a8_initfn()
373 cpu->isar.dbgdidr = 0x15141000; in cortex_a8_initfn()
374 cpu->clidr = (1 << 27) | (2 << 24) | 3; in cortex_a8_initfn()
375 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ in cortex_a8_initfn()
376 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ in cortex_a8_initfn()
377 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ in cortex_a8_initfn()
378 cpu->reset_auxcr = 2; in cortex_a8_initfn()
379 cpu->isar.reset_pmcr_el0 = 0x41002000; in cortex_a8_initfn()
380 define_arm_cp_regs(cpu, cortexa8_cp_reginfo); in cortex_a8_initfn()
391 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
397 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
414 ARMCPU *cpu = ARM_CPU(obj); in cortex_a9_initfn() local
416 cpu->dtb_compatible = "arm,cortex-a9"; in cortex_a9_initfn()
417 set_feature(&cpu->env, ARM_FEATURE_V7); in cortex_a9_initfn()
418 set_feature(&cpu->env, ARM_FEATURE_NEON); in cortex_a9_initfn()
419 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); in cortex_a9_initfn()
420 set_feature(&cpu->env, ARM_FEATURE_EL3); in cortex_a9_initfn()
421 set_feature(&cpu->env, ARM_FEATURE_PMU); in cortex_a9_initfn()
424 * A9UP and single-core A9MP (which are both different in cortex_a9_initfn()
427 set_feature(&cpu->env, ARM_FEATURE_V7MP); in cortex_a9_initfn()
428 set_feature(&cpu->env, ARM_FEATURE_CBAR); in cortex_a9_initfn()
429 cpu->midr = 0x410fc090; in cortex_a9_initfn()
430 cpu->reset_fpsid = 0x41033090; in cortex_a9_initfn()
431 cpu->isar.mvfr0 = 0x11110222; in cortex_a9_initfn()
432 cpu->isar.mvfr1 = 0x01111111; in cortex_a9_initfn()
433 cpu->ctr = 0x80038003; in cortex_a9_initfn()
434 cpu->reset_sctlr = 0x00c50078; in cortex_a9_initfn()
435 cpu->isar.id_pfr0 = 0x1031; in cortex_a9_initfn()
436 cpu->isar.id_pfr1 = 0x11; in cortex_a9_initfn()
437 cpu->isar.id_dfr0 = 0x000; in cortex_a9_initfn()
438 cpu->id_afr0 = 0; in cortex_a9_initfn()
439 cpu->isar.id_mmfr0 = 0x00100103; in cortex_a9_initfn()
440 cpu->isar.id_mmfr1 = 0x20000000; in cortex_a9_initfn()
441 cpu->isar.id_mmfr2 = 0x01230000; in cortex_a9_initfn()
442 cpu->isar.id_mmfr3 = 0x00002111; in cortex_a9_initfn()
443 cpu->isar.id_isar0 = 0x00101111; in cortex_a9_initfn()
444 cpu->isar.id_isar1 = 0x13112111; in cortex_a9_initfn()
445 cpu->isar.id_isar2 = 0x21232041; in cortex_a9_initfn()
446 cpu->isar.id_isar3 = 0x11112131; in cortex_a9_initfn()
447 cpu->isar.id_isar4 = 0x00111142; in cortex_a9_initfn()
448 cpu->isar.dbgdidr = 0x35141000; in cortex_a9_initfn()
449 cpu->clidr = (1 << 27) | (1 << 24) | 3; in cortex_a9_initfn()
450 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */ in cortex_a9_initfn()
451 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */ in cortex_a9_initfn()
452 cpu->isar.reset_pmcr_el0 = 0x41093000; in cortex_a9_initfn()
453 define_arm_cp_regs(cpu, cortexa9_cp_reginfo); in cortex_a9_initfn()
463 * Might as well set the interrupt-controller bit too. in a15_l2ctlr_read()
465 return ((ms->smp.cpus - 1) << 24) | (1 << 23); in a15_l2ctlr_read()
471 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
475 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
481 ARMCPU *cpu = ARM_CPU(obj); in cortex_a7_initfn() local
483 cpu->dtb_compatible = "arm,cortex-a7"; in cortex_a7_initfn()
484 set_feature(&cpu->env, ARM_FEATURE_V7VE); in cortex_a7_initfn()
485 set_feature(&cpu->env, ARM_FEATURE_NEON); in cortex_a7_initfn()
486 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); in cortex_a7_initfn()
487 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); in cortex_a7_initfn()
488 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); in cortex_a7_initfn()
489 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); in cortex_a7_initfn()
490 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); in cortex_a7_initfn()
491 set_feature(&cpu->env, ARM_FEATURE_EL2); in cortex_a7_initfn()
492 set_feature(&cpu->env, ARM_FEATURE_EL3); in cortex_a7_initfn()
493 set_feature(&cpu->env, ARM_FEATURE_PMU); in cortex_a7_initfn()
494 cpu->midr = 0x410fc075; in cortex_a7_initfn()
495 cpu->reset_fpsid = 0x41023075; in cortex_a7_initfn()
496 cpu->isar.mvfr0 = 0x10110222; in cortex_a7_initfn()
497 cpu->isar.mvfr1 = 0x11111111; in cortex_a7_initfn()
498 cpu->ctr = 0x84448003; in cortex_a7_initfn()
499 cpu->reset_sctlr = 0x00c50078; in cortex_a7_initfn()
500 cpu->isar.id_pfr0 = 0x00001131; in cortex_a7_initfn()
501 cpu->isar.id_pfr1 = 0x00011011; in cortex_a7_initfn()
502 cpu->isar.id_dfr0 = 0x02010555; in cortex_a7_initfn()
503 cpu->id_afr0 = 0x00000000; in cortex_a7_initfn()
504 cpu->isar.id_mmfr0 = 0x10101105; in cortex_a7_initfn()
505 cpu->isar.id_mmfr1 = 0x40000000; in cortex_a7_initfn()
506 cpu->isar.id_mmfr2 = 0x01240000; in cortex_a7_initfn()
507 cpu->isar.id_mmfr3 = 0x02102211; in cortex_a7_initfn()
509 * a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but in cortex_a7_initfn()
510 * table 4-41 gives 0x02101110, which includes the arm div insns. in cortex_a7_initfn()
512 cpu->isar.id_isar0 = 0x02101110; in cortex_a7_initfn()
513 cpu->isar.id_isar1 = 0x13112111; in cortex_a7_initfn()
514 cpu->isar.id_isar2 = 0x21232041; in cortex_a7_initfn()
515 cpu->isar.id_isar3 = 0x11112131; in cortex_a7_initfn()
516 cpu->isar.id_isar4 = 0x10011142; in cortex_a7_initfn()
517 cpu->isar.dbgdidr = 0x3515f005; in cortex_a7_initfn()
518 cpu->isar.dbgdevid = 0x01110f13; in cortex_a7_initfn()
519 cpu->isar.dbgdevid1 = 0x1; in cortex_a7_initfn()
520 cpu->clidr = 0x0a200023; in cortex_a7_initfn()
521 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ in cortex_a7_initfn()
522 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ in cortex_a7_initfn()
523 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ in cortex_a7_initfn()
524 cpu->isar.reset_pmcr_el0 = 0x41072000; in cortex_a7_initfn()
525 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ in cortex_a7_initfn()
530 ARMCPU *cpu = ARM_CPU(obj); in cortex_a15_initfn() local
532 cpu->dtb_compatible = "arm,cortex-a15"; in cortex_a15_initfn()
533 set_feature(&cpu->env, ARM_FEATURE_V7VE); in cortex_a15_initfn()
534 set_feature(&cpu->env, ARM_FEATURE_NEON); in cortex_a15_initfn()
535 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); in cortex_a15_initfn()
536 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); in cortex_a15_initfn()
537 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); in cortex_a15_initfn()
538 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); in cortex_a15_initfn()
539 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); in cortex_a15_initfn()
540 set_feature(&cpu->env, ARM_FEATURE_EL2); in cortex_a15_initfn()
541 set_feature(&cpu->env, ARM_FEATURE_EL3); in cortex_a15_initfn()
542 set_feature(&cpu->env, ARM_FEATURE_PMU); in cortex_a15_initfn()
543 /* r4p0 cpu, not requiring expensive tlb flush errata */ in cortex_a15_initfn()
544 cpu->midr = 0x414fc0f0; in cortex_a15_initfn()
545 cpu->revidr = 0x0; in cortex_a15_initfn()
546 cpu->reset_fpsid = 0x410430f0; in cortex_a15_initfn()
547 cpu->isar.mvfr0 = 0x10110222; in cortex_a15_initfn()
548 cpu->isar.mvfr1 = 0x11111111; in cortex_a15_initfn()
549 cpu->ctr = 0x8444c004; in cortex_a15_initfn()
550 cpu->reset_sctlr = 0x00c50078; in cortex_a15_initfn()
551 cpu->isar.id_pfr0 = 0x00001131; in cortex_a15_initfn()
552 cpu->isar.id_pfr1 = 0x00011011; in cortex_a15_initfn()
553 cpu->isar.id_dfr0 = 0x02010555; in cortex_a15_initfn()
554 cpu->id_afr0 = 0x00000000; in cortex_a15_initfn()
555 cpu->isar.id_mmfr0 = 0x10201105; in cortex_a15_initfn()
556 cpu->isar.id_mmfr1 = 0x20000000; in cortex_a15_initfn()
557 cpu->isar.id_mmfr2 = 0x01240000; in cortex_a15_initfn()
558 cpu->isar.id_mmfr3 = 0x02102211; in cortex_a15_initfn()
559 cpu->isar.id_isar0 = 0x02101110; in cortex_a15_initfn()
560 cpu->isar.id_isar1 = 0x13112111; in cortex_a15_initfn()
561 cpu->isar.id_isar2 = 0x21232041; in cortex_a15_initfn()
562 cpu->isar.id_isar3 = 0x11112131; in cortex_a15_initfn()
563 cpu->isar.id_isar4 = 0x10011142; in cortex_a15_initfn()
564 cpu->isar.dbgdidr = 0x3515f021; in cortex_a15_initfn()
565 cpu->isar.dbgdevid = 0x01110f13; in cortex_a15_initfn()
566 cpu->isar.dbgdevid1 = 0x0; in cortex_a15_initfn()
567 cpu->clidr = 0x0a200023; in cortex_a15_initfn()
568 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ in cortex_a15_initfn()
569 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ in cortex_a15_initfn()
570 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ in cortex_a15_initfn()
571 cpu->isar.reset_pmcr_el0 = 0x410F3000; in cortex_a15_initfn()
572 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); in cortex_a15_initfn()
577 { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
579 { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
587 ARMCPU *cpu = ARM_CPU(obj); in cortex_r5_initfn() local
589 set_feature(&cpu->env, ARM_FEATURE_V7); in cortex_r5_initfn()
590 set_feature(&cpu->env, ARM_FEATURE_V7MP); in cortex_r5_initfn()
591 set_feature(&cpu->env, ARM_FEATURE_PMSA); in cortex_r5_initfn()
592 set_feature(&cpu->env, ARM_FEATURE_PMU); in cortex_r5_initfn()
593 cpu->midr = 0x411fc153; /* r1p3 */ in cortex_r5_initfn()
594 cpu->isar.id_pfr0 = 0x0131; in cortex_r5_initfn()
595 cpu->isar.id_pfr1 = 0x001; in cortex_r5_initfn()
596 cpu->isar.id_dfr0 = 0x010400; in cortex_r5_initfn()
597 cpu->id_afr0 = 0x0; in cortex_r5_initfn()
598 cpu->isar.id_mmfr0 = 0x0210030; in cortex_r5_initfn()
599 cpu->isar.id_mmfr1 = 0x00000000; in cortex_r5_initfn()
600 cpu->isar.id_mmfr2 = 0x01200000; in cortex_r5_initfn()
601 cpu->isar.id_mmfr3 = 0x0211; in cortex_r5_initfn()
602 cpu->isar.id_isar0 = 0x02101111; in cortex_r5_initfn()
603 cpu->isar.id_isar1 = 0x13112111; in cortex_r5_initfn()
604 cpu->isar.id_isar2 = 0x21232141; in cortex_r5_initfn()
605 cpu->isar.id_isar3 = 0x01112131; in cortex_r5_initfn()
606 cpu->isar.id_isar4 = 0x0010142; in cortex_r5_initfn()
607 cpu->isar.id_isar5 = 0x0; in cortex_r5_initfn()
608 cpu->isar.id_isar6 = 0x0; in cortex_r5_initfn()
609 cpu->mp_is_up = true; in cortex_r5_initfn()
610 cpu->pmsav7_dregion = 16; in cortex_r5_initfn()
611 cpu->isar.reset_pmcr_el0 = 0x41151800; in cortex_r5_initfn()
612 define_arm_cp_regs(cpu, cortexr5_cp_reginfo); in cortex_r5_initfn()
619 .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
622 .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
625 .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 2,
628 .cp = 15, .opc1 = 1, .crn = 9, .crm = 1, .opc2 = 0,
631 .cp = 15, .opc1 = 1, .crn = 9, .crm = 1, .opc2 = 1,
634 .cp = 15, .opc1 = 1, .crn = 9, .crm = 1, .opc2 = 2,
643 .cp = 15, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 1,
652 .cp = 15, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 1,
655 .cp = 15, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 2,
658 .cp = 15, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 4,
664 .cp = 15, .opc1 = 2, .crn = 15, .crm = 0, .opc2 = 1,
667 .cp = 15, .opc1 = 2, .crn = 15, .crm = 1, .opc2 = 0,
670 .cp = 15, .opc1 = 2, .crn = 15, .crm = 1, .opc2 = 1,
676 .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 1,
688 .cp = 15, .opc1 = 2, .crn = 15, .crm = 3, .opc2 = 1,
694 .cp = 15, .opc1 = 3, .crn = 15, .crm = 0, .opc2 = 1,
700 .cp = 15, .opc1 = 4, .crn = 15, .crm = 0, .opc2 = 1,
709 .cp = 15, .opc1 = 3, .crn = 15, .crm = 2, .opc2 = 1,
715 .cp = 15, .opc1 = 3, .crn = 15, .crm = 4, .opc2 = 1,
722 ARMCPU *cpu = ARM_CPU(obj); in cortex_r52_initfn() local
724 set_feature(&cpu->env, ARM_FEATURE_V8); in cortex_r52_initfn()
725 set_feature(&cpu->env, ARM_FEATURE_EL2); in cortex_r52_initfn()
726 set_feature(&cpu->env, ARM_FEATURE_PMSA); in cortex_r52_initfn()
727 set_feature(&cpu->env, ARM_FEATURE_NEON); in cortex_r52_initfn()
728 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); in cortex_r52_initfn()
729 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); in cortex_r52_initfn()
730 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); in cortex_r52_initfn()
731 set_feature(&cpu->env, ARM_FEATURE_AUXCR); in cortex_r52_initfn()
732 cpu->midr = 0x411fd133; /* r1p3 */ in cortex_r52_initfn()
733 cpu->revidr = 0x00000000; in cortex_r52_initfn()
734 cpu->reset_fpsid = 0x41034023; in cortex_r52_initfn()
735 cpu->isar.mvfr0 = 0x10110222; in cortex_r52_initfn()
736 cpu->isar.mvfr1 = 0x12111111; in cortex_r52_initfn()
737 cpu->isar.mvfr2 = 0x00000043; in cortex_r52_initfn()
738 cpu->ctr = 0x8144c004; in cortex_r52_initfn()
739 cpu->reset_sctlr = 0x30c50838; in cortex_r52_initfn()
740 cpu->isar.id_pfr0 = 0x00000131; in cortex_r52_initfn()
741 cpu->isar.id_pfr1 = 0x10111001; in cortex_r52_initfn()
742 cpu->isar.id_dfr0 = 0x03010006; in cortex_r52_initfn()
743 cpu->id_afr0 = 0x00000000; in cortex_r52_initfn()
744 cpu->isar.id_mmfr0 = 0x00211040; in cortex_r52_initfn()
745 cpu->isar.id_mmfr1 = 0x40000000; in cortex_r52_initfn()
746 cpu->isar.id_mmfr2 = 0x01200000; in cortex_r52_initfn()
747 cpu->isar.id_mmfr3 = 0xf0102211; in cortex_r52_initfn()
748 cpu->isar.id_mmfr4 = 0x00000010; in cortex_r52_initfn()
749 cpu->isar.id_isar0 = 0x02101110; in cortex_r52_initfn()
750 cpu->isar.id_isar1 = 0x13112111; in cortex_r52_initfn()
751 cpu->isar.id_isar2 = 0x21232142; in cortex_r52_initfn()
752 cpu->isar.id_isar3 = 0x01112131; in cortex_r52_initfn()
753 cpu->isar.id_isar4 = 0x00010142; in cortex_r52_initfn()
754 cpu->isar.id_isar5 = 0x00010001; in cortex_r52_initfn()
755 cpu->isar.dbgdidr = 0x77168000; in cortex_r52_initfn()
756 cpu->clidr = (1 << 27) | (1 << 24) | 0x3; in cortex_r52_initfn()
757 cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */ in cortex_r52_initfn()
758 cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */ in cortex_r52_initfn()
760 cpu->pmsav7_dregion = 16; in cortex_r52_initfn()
761 cpu->pmsav8r_hdregion = 16; in cortex_r52_initfn()
763 define_arm_cp_regs(cpu, cortex_r52_cp_reginfo); in cortex_r52_initfn()
768 ARMCPU *cpu = ARM_CPU(obj); in cortex_r5f_initfn() local
771 cpu->isar.mvfr0 = 0x10110221; in cortex_r5f_initfn()
772 cpu->isar.mvfr1 = 0x00000011; in cortex_r5f_initfn()
777 ARMCPU *cpu = ARM_CPU(obj); in ti925t_initfn() local
778 set_feature(&cpu->env, ARM_FEATURE_V4T); in ti925t_initfn()
779 set_feature(&cpu->env, ARM_FEATURE_OMAPCP); in ti925t_initfn()
780 cpu->midr = ARM_CPUID_TI925T; in ti925t_initfn()
781 cpu->ctr = 0x5109149; in ti925t_initfn()
782 cpu->reset_sctlr = 0x00000070; in ti925t_initfn()
787 ARMCPU *cpu = ARM_CPU(obj); in sa1100_initfn() local
789 cpu->dtb_compatible = "intel,sa1100"; in sa1100_initfn()
790 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); in sa1100_initfn()
791 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); in sa1100_initfn()
792 cpu->midr = 0x4401A11B; in sa1100_initfn()
793 cpu->reset_sctlr = 0x00000070; in sa1100_initfn()
798 ARMCPU *cpu = ARM_CPU(obj); in sa1110_initfn() local
799 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); in sa1110_initfn()
800 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); in sa1110_initfn()
801 cpu->midr = 0x6901B119; in sa1110_initfn()
802 cpu->reset_sctlr = 0x00000070; in sa1110_initfn()
807 ARMCPU *cpu = ARM_CPU(obj); in pxa250_initfn() local
809 cpu->dtb_compatible = "marvell,xscale"; in pxa250_initfn()
810 set_feature(&cpu->env, ARM_FEATURE_V5); in pxa250_initfn()
811 set_feature(&cpu->env, ARM_FEATURE_XSCALE); in pxa250_initfn()
812 cpu->midr = 0x69052100; in pxa250_initfn()
813 cpu->ctr = 0xd172172; in pxa250_initfn()
814 cpu->reset_sctlr = 0x00000078; in pxa250_initfn()
819 ARMCPU *cpu = ARM_CPU(obj); in pxa255_initfn() local
821 cpu->dtb_compatible = "marvell,xscale"; in pxa255_initfn()
822 set_feature(&cpu->env, ARM_FEATURE_V5); in pxa255_initfn()
823 set_feature(&cpu->env, ARM_FEATURE_XSCALE); in pxa255_initfn()
824 cpu->midr = 0x69052d00; in pxa255_initfn()
825 cpu->ctr = 0xd172172; in pxa255_initfn()
826 cpu->reset_sctlr = 0x00000078; in pxa255_initfn()
831 ARMCPU *cpu = ARM_CPU(obj); in pxa260_initfn() local
833 cpu->dtb_compatible = "marvell,xscale"; in pxa260_initfn()
834 set_feature(&cpu->env, ARM_FEATURE_V5); in pxa260_initfn()
835 set_feature(&cpu->env, ARM_FEATURE_XSCALE); in pxa260_initfn()
836 cpu->midr = 0x69052903; in pxa260_initfn()
837 cpu->ctr = 0xd172172; in pxa260_initfn()
838 cpu->reset_sctlr = 0x00000078; in pxa260_initfn()
843 ARMCPU *cpu = ARM_CPU(obj); in pxa261_initfn() local
845 cpu->dtb_compatible = "marvell,xscale"; in pxa261_initfn()
846 set_feature(&cpu->env, ARM_FEATURE_V5); in pxa261_initfn()
847 set_feature(&cpu->env, ARM_FEATURE_XSCALE); in pxa261_initfn()
848 cpu->midr = 0x69052d05; in pxa261_initfn()
849 cpu->ctr = 0xd172172; in pxa261_initfn()
850 cpu->reset_sctlr = 0x00000078; in pxa261_initfn()
855 ARMCPU *cpu = ARM_CPU(obj); in pxa262_initfn() local
857 cpu->dtb_compatible = "marvell,xscale"; in pxa262_initfn()
858 set_feature(&cpu->env, ARM_FEATURE_V5); in pxa262_initfn()
859 set_feature(&cpu->env, ARM_FEATURE_XSCALE); in pxa262_initfn()
860 cpu->midr = 0x69052d06; in pxa262_initfn()
861 cpu->ctr = 0xd172172; in pxa262_initfn()
862 cpu->reset_sctlr = 0x00000078; in pxa262_initfn()
867 ARMCPU *cpu = ARM_CPU(obj); in pxa270a0_initfn() local
869 cpu->dtb_compatible = "marvell,xscale"; in pxa270a0_initfn()
870 set_feature(&cpu->env, ARM_FEATURE_V5); in pxa270a0_initfn()
871 set_feature(&cpu->env, ARM_FEATURE_XSCALE); in pxa270a0_initfn()
872 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); in pxa270a0_initfn()
873 cpu->midr = 0x69054110; in pxa270a0_initfn()
874 cpu->ctr = 0xd172172; in pxa270a0_initfn()
875 cpu->reset_sctlr = 0x00000078; in pxa270a0_initfn()
880 ARMCPU *cpu = ARM_CPU(obj); in pxa270a1_initfn() local
882 cpu->dtb_compatible = "marvell,xscale"; in pxa270a1_initfn()
883 set_feature(&cpu->env, ARM_FEATURE_V5); in pxa270a1_initfn()
884 set_feature(&cpu->env, ARM_FEATURE_XSCALE); in pxa270a1_initfn()
885 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); in pxa270a1_initfn()
886 cpu->midr = 0x69054111; in pxa270a1_initfn()
887 cpu->ctr = 0xd172172; in pxa270a1_initfn()
888 cpu->reset_sctlr = 0x00000078; in pxa270a1_initfn()
893 ARMCPU *cpu = ARM_CPU(obj); in pxa270b0_initfn() local
895 cpu->dtb_compatible = "marvell,xscale"; in pxa270b0_initfn()
896 set_feature(&cpu->env, ARM_FEATURE_V5); in pxa270b0_initfn()
897 set_feature(&cpu->env, ARM_FEATURE_XSCALE); in pxa270b0_initfn()
898 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); in pxa270b0_initfn()
899 cpu->midr = 0x69054112; in pxa270b0_initfn()
900 cpu->ctr = 0xd172172; in pxa270b0_initfn()
901 cpu->reset_sctlr = 0x00000078; in pxa270b0_initfn()
906 ARMCPU *cpu = ARM_CPU(obj); in pxa270b1_initfn() local
908 cpu->dtb_compatible = "marvell,xscale"; in pxa270b1_initfn()
909 set_feature(&cpu->env, ARM_FEATURE_V5); in pxa270b1_initfn()
910 set_feature(&cpu->env, ARM_FEATURE_XSCALE); in pxa270b1_initfn()
911 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); in pxa270b1_initfn()
912 cpu->midr = 0x69054113; in pxa270b1_initfn()
913 cpu->ctr = 0xd172172; in pxa270b1_initfn()
914 cpu->reset_sctlr = 0x00000078; in pxa270b1_initfn()
919 ARMCPU *cpu = ARM_CPU(obj); in pxa270c0_initfn() local
921 cpu->dtb_compatible = "marvell,xscale"; in pxa270c0_initfn()
922 set_feature(&cpu->env, ARM_FEATURE_V5); in pxa270c0_initfn()
923 set_feature(&cpu->env, ARM_FEATURE_XSCALE); in pxa270c0_initfn()
924 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); in pxa270c0_initfn()
925 cpu->midr = 0x69054114; in pxa270c0_initfn()
926 cpu->ctr = 0xd172172; in pxa270c0_initfn()
927 cpu->reset_sctlr = 0x00000078; in pxa270c0_initfn()
932 ARMCPU *cpu = ARM_CPU(obj); in pxa270c5_initfn() local
934 cpu->dtb_compatible = "marvell,xscale"; in pxa270c5_initfn()
935 set_feature(&cpu->env, ARM_FEATURE_V5); in pxa270c5_initfn()
936 set_feature(&cpu->env, ARM_FEATURE_XSCALE); in pxa270c5_initfn()
937 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); in pxa270c5_initfn()
938 cpu->midr = 0x69054117; in pxa270c5_initfn()
939 cpu->ctr = 0xd172172; in pxa270c5_initfn()
940 cpu->reset_sctlr = 0x00000078; in pxa270c5_initfn()
945 * -cpu max: a CPU with as many features enabled as our emulation supports.
946 * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c;
951 ARMCPU *cpu = ARM_CPU(obj); in arm_max_initfn() local
954 cpu->dtb_compatible = "arm,cortex-a57"; in arm_max_initfn()
955 set_feature(&cpu->env, ARM_FEATURE_V8); in arm_max_initfn()
956 set_feature(&cpu->env, ARM_FEATURE_NEON); in arm_max_initfn()
957 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); in arm_max_initfn()
958 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); in arm_max_initfn()
959 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); in arm_max_initfn()
960 set_feature(&cpu->env, ARM_FEATURE_EL2); in arm_max_initfn()
961 set_feature(&cpu->env, ARM_FEATURE_EL3); in arm_max_initfn()
962 set_feature(&cpu->env, ARM_FEATURE_PMU); in arm_max_initfn()
963 cpu->midr = 0x411fd070; in arm_max_initfn()
964 cpu->revidr = 0x00000000; in arm_max_initfn()
965 cpu->reset_fpsid = 0x41034070; in arm_max_initfn()
966 cpu->isar.mvfr0 = 0x10110222; in arm_max_initfn()
967 cpu->isar.mvfr1 = 0x12111111; in arm_max_initfn()
968 cpu->isar.mvfr2 = 0x00000043; in arm_max_initfn()
969 cpu->ctr = 0x8444c004; in arm_max_initfn()
970 cpu->reset_sctlr = 0x00c50838; in arm_max_initfn()
971 cpu->isar.id_pfr0 = 0x00000131; in arm_max_initfn()
972 cpu->isar.id_pfr1 = 0x00011011; in arm_max_initfn()
973 cpu->isar.id_dfr0 = 0x03010066; in arm_max_initfn()
974 cpu->id_afr0 = 0x00000000; in arm_max_initfn()
975 cpu->isar.id_mmfr0 = 0x10101105; in arm_max_initfn()
976 cpu->isar.id_mmfr1 = 0x40000000; in arm_max_initfn()
977 cpu->isar.id_mmfr2 = 0x01260000; in arm_max_initfn()
978 cpu->isar.id_mmfr3 = 0x02102211; in arm_max_initfn()
979 cpu->isar.id_isar0 = 0x02101110; in arm_max_initfn()
980 cpu->isar.id_isar1 = 0x13112111; in arm_max_initfn()
981 cpu->isar.id_isar2 = 0x21232042; in arm_max_initfn()
982 cpu->isar.id_isar3 = 0x01112131; in arm_max_initfn()
983 cpu->isar.id_isar4 = 0x00011142; in arm_max_initfn()
984 cpu->isar.id_isar5 = 0x00011121; in arm_max_initfn()
985 cpu->isar.id_isar6 = 0; in arm_max_initfn()
986 cpu->isar.reset_pmcr_el0 = 0x41013000; in arm_max_initfn()
987 cpu->clidr = 0x0a200023; in arm_max_initfn()
988 cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ in arm_max_initfn()
989 cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ in arm_max_initfn()
990 cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */ in arm_max_initfn()
991 define_cortex_a72_a57_a53_cp_reginfo(cpu); in arm_max_initfn()
993 aa32_max_features(cpu); in arm_max_initfn()
997 * Break with true ARMv8 and add back old-style VFP short-vector support. in arm_max_initfn()
998 * Only do this for user-mode, where -cpu max is the default, so that in arm_max_initfn()
1001 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); in arm_max_initfn()
1011 * What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
1015 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn },
1019 { .name = "cortex-a7", .initfn = cortex_a7_initfn },
1020 { .name = "cortex-a8", .initfn = cortex_a8_initfn },
1021 { .name = "cortex-a9", .initfn = cortex_a9_initfn },
1022 { .name = "cortex-a15", .initfn = cortex_a15_initfn },
1023 { .name = "cortex-r5", .initfn = cortex_r5_initfn },
1024 { .name = "cortex-r5f", .initfn = cortex_r5f_initfn },
1025 { .name = "cortex-r52", .initfn = cortex_r52_initfn },
1034 /* "pxa270" is an alias for "pxa270-a0" */
1036 { .name = "pxa270-a0", .initfn = pxa270a0_initfn },
1037 { .name = "pxa270-a1", .initfn = pxa270a1_initfn },
1038 { .name = "pxa270-b0", .initfn = pxa270b0_initfn },
1039 { .name = "pxa270-b1", .initfn = pxa270b1_initfn },
1040 { .name = "pxa270-c0", .initfn = pxa270c0_initfn },
1041 { .name = "pxa270-c5", .initfn = pxa270c5_initfn },