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/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Drenesas,cpg-div6-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,cpg-div6-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas CPG DIV6 Clock
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 The CPG DIV6 clocks are variable factor clocks provided by the Clock Pulse
14 Generator (CPG). Their clock input is divided by a configurable factor from 1
20 - enum:
21 - renesas,r8a73a4-div6-clock # R-Mobile APE6
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/openbmc/linux/arch/arm/boot/dts/renesas/
H A Dsh73a0.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the SH-Mobile AG5 (R8A73A00/SH73A0) SoC
8 #include <dt-bindings/clock/sh73a0-clock.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <1>;
16 #size-cells = <1>;
19 #address-cells = <1>;
20 #size-cells = <0>;
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H A Dr8a73a4.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/r8a73a4-clock.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 #address-cells = <1>;
21 #size-cells = <0>;
25 compatible = "arm,cortex-a15";
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H A Dr8a7740.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Mobile A1 (R8A77400) SoC
8 #include <dt-bindings/clock/r8a7740-clock.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <1>;
16 #size-cells = <1>;
19 #address-cells = <1>;
20 #size-cells = <0>;
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/openbmc/linux/drivers/clk/renesas/
H A Dclk-div6.c1 // SPDX-License-Identifier: GPL-2.0
3 * r8a7790 Common Clock Framework support
10 #include <linux/clk-provider.h>
20 #include "clk-div6.h"
27 * struct div6_clock - CPG 6 bit divider clock
28 * @hw: handle between common and hardware-specific interfaces
29 * @reg: IO-remapped register
30 * @div: divisor value (1-64)
31 * @src_mask: Bitmask covering the register bits to select the parent clock
32 * @nb: Notifier block to save/restore clock state for system resume
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H A Drenesas-cpg-mssr.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Renesas Clock Pulse Generator / Module Standby and Software Reset
12 * Definitions of CPG Core Clocks
15 * - Clock outputs exported to DT
16 * - External input clocks
17 * - Internal CPG clocks
34 CLK_TYPE_IN, /* External Clock Input */
35 CLK_TYPE_FF, /* Fixed Factor Clock */
36 CLK_TYPE_DIV6P1, /* DIV6 Clock with 1 parent clock */
37 CLK_TYPE_DIV6_RO, /* DIV6 Clock read only with extra divisor */
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H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 obj-$(CONFIG_CLK_EMEV2) += clk-emev2.o
4 obj-$(CONFIG_CLK_RZA1) += clk-rz.o
5 obj-$(CONFIG_CLK_R7S9210) += r7s9210-cpg-mssr.o
6 obj-$(CONFIG_CLK_R8A73A4) += clk-r8a73a4.o
7 obj-$(CONFIG_CLK_R8A7740) += clk-r8a7740.o
8 obj-$(CONFIG_CLK_R8A7742) += r8a7742-cpg-mssr.o
9 obj-$(CONFIG_CLK_R8A7743) += r8a7743-cpg-mssr.o
10 obj-$(CONFIG_CLK_R8A7745) += r8a7745-cpg-mssr.o
11 obj-$(CONFIG_CLK_R8A77470) += r8a77470-cpg-mssr.o
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
4 bool "Renesas SoC clock support" if COMPILE_TEST && !ARCH_RENESAS
47 bool "Emma Mobile EV2 clock support" if COMPILE_TEST
50 bool "RZ/A1H clock support" if COMPILE_TEST
54 bool "RZ/A2 clock support" if COMPILE_TEST
58 bool "R-Mobile APE6 clock support" if COMPILE_TEST
63 bool "R-Mobile A1 clock support" if COMPILE_TEST
68 bool "RZ/G1H clock support" if COMPILE_TEST
72 bool "RZ/G1M clock support" if COMPILE_TEST
76 bool "RZ/G1E clock support" if COMPILE_TEST
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H A Drenesas-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas Clock Pulse Generator / Module Standby and Software Reset
7 * Based on clk-mstp.c, clk-rcar-gen2.c, and clk-rcar-gen3.c
14 #include <linux/clk-provider.h>
28 #include <linux/reset-controller.h>
31 #include <dt-bindings/clock/renesas-cpg-mssr.h>
33 #include "renesas-cpg-mssr.h"
34 #include "clk-div6.h"
46 * If the registers exist, these are valid for SH-Mobile, R-Mobile,
47 * R-Car Gen2, R-Car Gen3, and RZ/G1.
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/openbmc/u-boot/drivers/clk/renesas/
H A Drenesas-cpg-mssr.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Renesas RCar Gen3 CPG MSSR driver
5 * Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com>
8 * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
35 * Definitions of CPG Core Clocks
38 * - Clock outputs exported to DT
39 * - External input clocks
40 * - Internal CPG clocks
56 CLK_TYPE_IN, /* External Clock Input */
57 CLK_TYPE_FF, /* Fixed Factor Clock */
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H A Dclk-rcar-gen2.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Renesas RCar Gen2 CPG MSSR driver
8 * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
14 #include <clk-uclass.h>
19 #include <dt-bindings/clock/renesas-cpg-mssr.h>
21 #include "renesas-cpg-mssr.h"
22 #include "rcar-gen2-cpg.h"
62 struct gen2_clk_priv *priv = dev_get_priv(clk->dev); in gen2_clk_enable()
64 return renesas_clk_endisable(clk, priv->base, true); in gen2_clk_enable()
69 struct gen2_clk_priv *priv = dev_get_priv(clk->dev); in gen2_clk_disable()
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/openbmc/linux/Documentation/devicetree/bindings/net/can/
H A Drenesas,rcar-can.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/can/renesas,rcar-can.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car CAN Controller
10 - Sergei Shtylyov <sergei.shtylyov@gmail.com>
15 - items:
16 - enum:
17 - renesas,can-r8a7778 # R-Car M1-A
18 - renesas,can-r8a7779 # R-Car H1
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H A Drenesas,rcar-canfd.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/can/renesas,rcar-canfd.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car CAN FD Controller
10 - Fabrizio Castro <fabrizio.castro.jz@renesas.com>
15 - items:
16 - enum:
17 - renesas,r8a774a1-canfd # RZ/G2M
18 - renesas,r8a774b1-canfd # RZ/G2N
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/openbmc/linux/drivers/sh/clk/
H A Dcpg.c2 * Helper routines for SuperH Clock Pulse Generator blocks (CPG).
5 * Copyright (C) 2010 - 2012 Paul Mundt
21 if (clk->flags & CLK_ENABLE_REG_8BIT) in sh_clk_read()
22 return ioread8(clk->mapped_reg); in sh_clk_read()
23 else if (clk->flags & CLK_ENABLE_REG_16BIT) in sh_clk_read()
24 return ioread16(clk->mapped_reg); in sh_clk_read()
26 return ioread32(clk->mapped_reg); in sh_clk_read()
31 if (clk->flags & CLK_ENABLE_REG_8BIT) in sh_clk_write()
32 iowrite8(value, clk->mapped_reg); in sh_clk_write()
33 else if (clk->flags & CLK_ENABLE_REG_16BIT) in sh_clk_write()
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/openbmc/linux/
H A Dopengrok0.0.log1 2024-12-28 20:09:05.996-0600 FINEST t1171 PendingFileCompleter.doRename: Moved pending as file: '/opengrok/data/xref/openbmc/linux/drivers/staging/media/av7110/video-continue.rst.gz'
2 2024-12-28 20:09:05.942-0600 FINEST t1149 PendingFileCompleter.doRename: Moved pending as file: '/opengrok/data/xref/openbmc/u-boot/arch/sh/config.mk.gz'
3 2024-12-2
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H A Dopengrok2.0.log1 2024-12-28 20:05:26.116-0600 FINEST t586 Statistics.logIt: Added: '/openbmc/linux/tools/testing/selftests/drivers/net/mlxsw/rtnetlink.sh' (ShAnalyzer) (took 79 ms)
2 2024-12-28 20:05:26.112-0600 FINER t592 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/qemu',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/qemu/chardev/spice.c'
3 2024-12-28 20:05:26.116-0600 FINEST t592 Statistics.logIt: Added: '/openbmc/qemu/chardev/spice.c' (CAnalyzer) (took 33 ms)
4 2024-1
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