1 // SPDX-License-Identifier: GPL-2.0
3  * Renesas Clock Pulse Generator / Module Standby and Software Reset
7  * Based on clk-mstp.c, clk-rcar-gen2.c, and clk-rcar-gen3.c
14 #include <linux/clk-provider.h>
28 #include <linux/reset-controller.h>
31 #include <dt-bindings/clock/renesas-cpg-mssr.h>
33 #include "renesas-cpg-mssr.h"
34 #include "clk-div6.h"
46  * If the registers exist, these are valid for SH-Mobile, R-Mobile,
47  * R-Car Gen2, R-Car Gen3, and RZ/G1.
48  * These are NOT valid for R-Car Gen1 and RZ/A1!
126  * struct cpg_mssr_priv - Clock Pulse Generator / Module Standby
130  * @dev: CPG/MSSR device
131  * @base: CPG/MSSR register block base address
132  * @reg_layout: CPG/MSSR register layout
134  * @np: Device node in DT for this CPG/MSSR module
137  * @last_dt_core_clk: ID of the last Core Clock exported to DT
138  * @notifiers: Notifier chain to save/restore clock state for system resume
177  * struct mstp_clock - MSTP gating clock
178  * @hw: handle between common and hardware-specific interfaces
179  * @index: MSTP clock number
180  * @priv: CPG/MSSR private data
192 	struct mstp_clock *clock = to_mstp_clock(hw);  in cpg_mstp_clock_endisable()  local
193 	struct cpg_mssr_priv *priv = clock->priv;  in cpg_mstp_clock_endisable()
194 	unsigned int reg = clock->index / 32;  in cpg_mstp_clock_endisable()
195 	unsigned int bit = clock->index % 32;  in cpg_mstp_clock_endisable()
196 	struct device *dev = priv->dev;  in cpg_mstp_clock_endisable()
202 	dev_dbg(dev, "MSTP %u%02u/%pC %s\n", reg, bit, hw->clk,  in cpg_mstp_clock_endisable()
204 	spin_lock_irqsave(&priv->rmw_lock, flags);  in cpg_mstp_clock_endisable()
206 	if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {  in cpg_mstp_clock_endisable()
207 		value = readb(priv->base + priv->control_regs[reg]);  in cpg_mstp_clock_endisable()
212 		writeb(value, priv->base + priv->control_regs[reg]);  in cpg_mstp_clock_endisable()
215 		readb(priv->base + priv->control_regs[reg]);  in cpg_mstp_clock_endisable()
216 		barrier_data(priv->base + priv->control_regs[reg]);  in cpg_mstp_clock_endisable()
218 		value = readl(priv->base + priv->control_regs[reg]);  in cpg_mstp_clock_endisable()
223 		writel(value, priv->base + priv->control_regs[reg]);  in cpg_mstp_clock_endisable()
226 	spin_unlock_irqrestore(&priv->rmw_lock, flags);  in cpg_mstp_clock_endisable()
228 	if (!enable || priv->reg_layout == CLK_REG_LAYOUT_RZ_A)  in cpg_mstp_clock_endisable()
231 	error = readl_poll_timeout_atomic(priv->base + priv->status_regs[reg],  in cpg_mstp_clock_endisable()
235 			priv->base + priv->control_regs[reg], bit);  in cpg_mstp_clock_endisable()
252 	struct mstp_clock *clock = to_mstp_clock(hw);  in cpg_mstp_clock_is_enabled()  local
253 	struct cpg_mssr_priv *priv = clock->priv;  in cpg_mstp_clock_is_enabled()
256 	if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)  in cpg_mstp_clock_is_enabled()
257 		value = readb(priv->base + priv->control_regs[clock->index / 32]);  in cpg_mstp_clock_is_enabled()
259 		value = readl(priv->base + priv->status_regs[clock->index / 32]);  in cpg_mstp_clock_is_enabled()
261 	return !(value & BIT(clock->index % 32));  in cpg_mstp_clock_is_enabled()
274 	unsigned int clkidx = clkspec->args[1];  in cpg_mssr_clk_src_twocell_get()
276 	struct device *dev = priv->dev;  in cpg_mssr_clk_src_twocell_get()
282 	switch (clkspec->args[0]) {  in cpg_mssr_clk_src_twocell_get()
285 		if (clkidx > priv->last_dt_core_clk) {  in cpg_mssr_clk_src_twocell_get()
286 			dev_err(dev, "Invalid %s clock index %u\n", type,  in cpg_mssr_clk_src_twocell_get()
288 			return ERR_PTR(-EINVAL);  in cpg_mssr_clk_src_twocell_get()
290 		clk = priv->clks[clkidx];  in cpg_mssr_clk_src_twocell_get()
295 		if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {  in cpg_mssr_clk_src_twocell_get()
297 			range_check = 7 - (clkidx % 10);  in cpg_mssr_clk_src_twocell_get()
300 			range_check = 31 - (clkidx % 100);  in cpg_mssr_clk_src_twocell_get()
302 		if (range_check < 0 || idx >= priv->num_mod_clks) {  in cpg_mssr_clk_src_twocell_get()
303 			dev_err(dev, "Invalid %s clock index %u\n", type,  in cpg_mssr_clk_src_twocell_get()
305 			return ERR_PTR(-EINVAL);  in cpg_mssr_clk_src_twocell_get()
307 		clk = priv->clks[priv->num_core_clks + idx];  in cpg_mssr_clk_src_twocell_get()
311 		dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]);  in cpg_mssr_clk_src_twocell_get()
312 		return ERR_PTR(-EINVAL);  in cpg_mssr_clk_src_twocell_get()
316 		dev_err(dev, "Cannot get %s clock %u: %ld", type, clkidx,  in cpg_mssr_clk_src_twocell_get()
319 		dev_dbg(dev, "clock (%u, %u) is %pC at %lu Hz\n",  in cpg_mssr_clk_src_twocell_get()
320 			clkspec->args[0], clkspec->args[1], clk,  in cpg_mssr_clk_src_twocell_get()
329 	struct clk *clk = ERR_PTR(-ENOTSUPP), *parent;  in cpg_mssr_register_core_clk()
330 	struct device *dev = priv->dev;  in cpg_mssr_register_core_clk()
331 	unsigned int id = core->id, div = core->div;  in cpg_mssr_register_core_clk()
334 	WARN_DEBUG(id >= priv->num_core_clks);  in cpg_mssr_register_core_clk()
335 	WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);  in cpg_mssr_register_core_clk()
337 	if (!core->name) {  in cpg_mssr_register_core_clk()
338 		/* Skip NULLified clock */  in cpg_mssr_register_core_clk()
342 	switch (core->type) {  in cpg_mssr_register_core_clk()
344 		clk = of_clk_get_by_name(priv->np, core->name);  in cpg_mssr_register_core_clk()
350 		WARN_DEBUG(core->parent >= priv->num_core_clks);  in cpg_mssr_register_core_clk()
351 		parent = priv->clks[core->parent];  in cpg_mssr_register_core_clk()
359 		if (core->type == CLK_TYPE_DIV6_RO)  in cpg_mssr_register_core_clk()
360 			/* Multiply with the DIV6 register value */  in cpg_mssr_register_core_clk()
361 			div *= (readl(priv->base + core->offset) & 0x3f) + 1;  in cpg_mssr_register_core_clk()
363 		if (core->type == CLK_TYPE_DIV6P1) {  in cpg_mssr_register_core_clk()
364 			clk = cpg_div6_register(core->name, 1, &parent_name,  in cpg_mssr_register_core_clk()
365 						priv->base + core->offset,  in cpg_mssr_register_core_clk()
366 						&priv->notifiers);  in cpg_mssr_register_core_clk()
368 			clk = clk_register_fixed_factor(NULL, core->name,  in cpg_mssr_register_core_clk()
370 							core->mult, div);  in cpg_mssr_register_core_clk()
375 		clk = clk_register_fixed_rate(NULL, core->name, NULL, 0,  in cpg_mssr_register_core_clk()
376 					      core->mult);  in cpg_mssr_register_core_clk()
380 		if (info->cpg_clk_register)  in cpg_mssr_register_core_clk()
381 			clk = info->cpg_clk_register(dev, core, info,  in cpg_mssr_register_core_clk()
382 						     priv->clks, priv->base,  in cpg_mssr_register_core_clk()
383 						     &priv->notifiers);  in cpg_mssr_register_core_clk()
385 			dev_err(dev, "%s has unsupported core clock type %u\n",  in cpg_mssr_register_core_clk()
386 				core->name, core->type);  in cpg_mssr_register_core_clk()
393 	dev_dbg(dev, "Core clock %pC at %lu Hz\n", clk, clk_get_rate(clk));  in cpg_mssr_register_core_clk()
394 	priv->clks[id] = clk;  in cpg_mssr_register_core_clk()
398 	dev_err(dev, "Failed to register %s clock %s: %ld\n", "core",  in cpg_mssr_register_core_clk()
399 		core->name, PTR_ERR(clk));  in cpg_mssr_register_core_clk()
406 	struct mstp_clock *clock = NULL;  in cpg_mssr_register_mod_clk()  local
407 	struct device *dev = priv->dev;  in cpg_mssr_register_mod_clk()
408 	unsigned int id = mod->id;  in cpg_mssr_register_mod_clk()
414 	WARN_DEBUG(id < priv->num_core_clks);  in cpg_mssr_register_mod_clk()
415 	WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks);  in cpg_mssr_register_mod_clk()
416 	WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks);  in cpg_mssr_register_mod_clk()
417 	WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);  in cpg_mssr_register_mod_clk()
419 	if (!mod->name) {  in cpg_mssr_register_mod_clk()
420 		/* Skip NULLified clock */  in cpg_mssr_register_mod_clk()
424 	parent = priv->clks[mod->parent];  in cpg_mssr_register_mod_clk()
430 	clock = kzalloc(sizeof(*clock), GFP_KERNEL);  in cpg_mssr_register_mod_clk()
431 	if (!clock) {  in cpg_mssr_register_mod_clk()
432 		clk = ERR_PTR(-ENOMEM);  in cpg_mssr_register_mod_clk()
436 	init.name = mod->name;  in cpg_mssr_register_mod_clk()
443 	clock->index = id - priv->num_core_clks;  in cpg_mssr_register_mod_clk()
444 	clock->priv = priv;  in cpg_mssr_register_mod_clk()
445 	clock->hw.init = &init;  in cpg_mssr_register_mod_clk()
447 	for (i = 0; i < info->num_crit_mod_clks; i++)  in cpg_mssr_register_mod_clk()
448 		if (id == info->crit_mod_clks[i] &&  in cpg_mssr_register_mod_clk()
449 		    cpg_mstp_clock_is_enabled(&clock->hw)) {  in cpg_mssr_register_mod_clk()
451 				mod->name);  in cpg_mssr_register_mod_clk()
456 	clk = clk_register(NULL, &clock->hw);  in cpg_mssr_register_mod_clk()
460 	dev_dbg(dev, "Module clock %pC at %lu Hz\n", clk, clk_get_rate(clk));  in cpg_mssr_register_mod_clk()
461 	priv->clks[id] = clk;  in cpg_mssr_register_mod_clk()
462 	priv->smstpcr_saved[clock->index / 32].mask |= BIT(clock->index % 32);  in cpg_mssr_register_mod_clk()
466 	dev_err(dev, "Failed to register %s clock %s: %ld\n", "module",  in cpg_mssr_register_mod_clk()
467 		mod->name, PTR_ERR(clk));  in cpg_mssr_register_mod_clk()
468 	kfree(clock);  in cpg_mssr_register_mod_clk()
484 	if (clkspec->np != pd->genpd.dev.of_node || clkspec->args_count != 2)  in cpg_mssr_is_pm_clk()
487 	switch (clkspec->args[0]) {  in cpg_mssr_is_pm_clk()
489 		for (i = 0; i < pd->num_core_pm_clks; i++)  in cpg_mssr_is_pm_clk()
490 			if (clkspec->args[1] == pd->core_pm_clks[i])  in cpg_mssr_is_pm_clk()
505 	struct device_node *np = dev->of_node;  in cpg_mssr_attach_dev()
512 		dev_dbg(dev, "CPG/MSSR clock domain not yet available\n");  in cpg_mssr_attach_dev()
513 		return -EPROBE_DEFER;  in cpg_mssr_attach_dev()
516 	while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,  in cpg_mssr_attach_dev()
566 	struct device_node *np = dev->of_node;  in cpg_mssr_add_clk_domain()
574 		return -ENOMEM;  in cpg_mssr_add_clk_domain()
576 	pd->num_core_pm_clks = num_core_pm_clks;  in cpg_mssr_add_clk_domain()
577 	memcpy(pd->core_pm_clks, core_pm_clks, pm_size);  in cpg_mssr_add_clk_domain()
579 	genpd = &pd->genpd;  in cpg_mssr_add_clk_domain()
580 	genpd->name = np->name;  in cpg_mssr_add_clk_domain()
581 	genpd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON |  in cpg_mssr_add_clk_domain()
583 	genpd->attach_dev = cpg_mssr_attach_dev;  in cpg_mssr_add_clk_domain()
584 	genpd->detach_dev = cpg_mssr_detach_dev;  in cpg_mssr_add_clk_domain()
610 	dev_dbg(priv->dev, "reset %u%02u\n", reg, bit);  in cpg_mssr_reset()
613 	writel(bitmask, priv->base + priv->reset_regs[reg]);  in cpg_mssr_reset()
615 	/* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */  in cpg_mssr_reset()
619 	writel(bitmask, priv->base + priv->reset_clear_regs[reg]);  in cpg_mssr_reset()
631 	dev_dbg(priv->dev, "assert %u%02u\n", reg, bit);  in cpg_mssr_assert()
633 	writel(bitmask, priv->base + priv->reset_regs[reg]);  in cpg_mssr_assert()
645 	dev_dbg(priv->dev, "deassert %u%02u\n", reg, bit);  in cpg_mssr_deassert()
647 	writel(bitmask, priv->base + priv->reset_clear_regs[reg]);  in cpg_mssr_deassert()
659 	return !!(readl(priv->base + priv->reset_regs[reg]) & bitmask);  in cpg_mssr_status()
673 	unsigned int unpacked = reset_spec->args[0];  in cpg_mssr_reset_xlate()
676 	if (unpacked % 100 > 31 || idx >= rcdev->nr_resets) {  in cpg_mssr_reset_xlate()
677 		dev_err(priv->dev, "Invalid reset index %u\n", unpacked);  in cpg_mssr_reset_xlate()
678 		return -EINVAL;  in cpg_mssr_reset_xlate()
686 	priv->rcdev.ops = &cpg_mssr_reset_ops;  in cpg_mssr_reset_controller_register()
687 	priv->rcdev.of_node = priv->dev->of_node;  in cpg_mssr_reset_controller_register()
688 	priv->rcdev.of_reset_n_cells = 1;  in cpg_mssr_reset_controller_register()
689 	priv->rcdev.of_xlate = cpg_mssr_reset_xlate;  in cpg_mssr_reset_controller_register()
690 	priv->rcdev.nr_resets = priv->num_mod_clks;  in cpg_mssr_reset_controller_register()
691 	return devm_reset_controller_register(priv->dev, &priv->rcdev);  in cpg_mssr_reset_controller_register()
705 		.compatible = "renesas,r7s9210-cpg-mssr",
711 		.compatible = "renesas,r8a7742-cpg-mssr",
717 		.compatible = "renesas,r8a7743-cpg-mssr",
722 		.compatible = "renesas,r8a7744-cpg-mssr",
728 		.compatible = "renesas,r8a7745-cpg-mssr",
734 		.compatible = "renesas,r8a77470-cpg-mssr",
740 		.compatible = "renesas,r8a774a1-cpg-mssr",
746 		.compatible = "renesas,r8a774b1-cpg-mssr",
752 		.compatible = "renesas,r8a774c0-cpg-mssr",
758 		.compatible = "renesas,r8a774e1-cpg-mssr",
764 		.compatible = "renesas,r8a7790-cpg-mssr",
770 		.compatible = "renesas,r8a7791-cpg-mssr",
773 	/* R-Car M2-N is (almost) identical to R-Car M2-W w.r.t. clocks. */
775 		.compatible = "renesas,r8a7793-cpg-mssr",
781 		.compatible = "renesas,r8a7792-cpg-mssr",
787 		.compatible = "renesas,r8a7794-cpg-mssr",
793 		.compatible = "renesas,r8a7795-cpg-mssr",
799 		.compatible = "renesas,r8a7796-cpg-mssr",
805 		.compatible = "renesas,r8a77961-cpg-mssr",
811 		.compatible = "renesas,r8a77965-cpg-mssr",
817 		.compatible = "renesas,r8a77970-cpg-mssr",
823 		.compatible = "renesas,r8a77980-cpg-mssr",
829 		.compatible = "renesas,r8a77990-cpg-mssr",
835 		.compatible = "renesas,r8a77995-cpg-mssr",
841 		.compatible = "renesas,r8a779a0-cpg-mssr",
847 		.compatible = "renesas,r8a779f0-cpg-mssr",
853 		.compatible = "renesas,r8a779g0-cpg-mssr",
876 	for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) {  in cpg_mssr_suspend_noirq()
877 		if (priv->smstpcr_saved[reg].mask)  in cpg_mssr_suspend_noirq()
878 			priv->smstpcr_saved[reg].val =  in cpg_mssr_suspend_noirq()
879 				priv->reg_layout == CLK_REG_LAYOUT_RZ_A ?  in cpg_mssr_suspend_noirq()
880 				readb(priv->base + priv->control_regs[reg]) :  in cpg_mssr_suspend_noirq()
881 				readl(priv->base + priv->control_regs[reg]);  in cpg_mssr_suspend_noirq()
885 	raw_notifier_call_chain(&priv->notifiers, PM_EVENT_SUSPEND, NULL);  in cpg_mssr_suspend_noirq()
902 	raw_notifier_call_chain(&priv->notifiers, PM_EVENT_RESUME, NULL);  in cpg_mssr_resume_noirq()
905 	for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) {  in cpg_mssr_resume_noirq()
906 		mask = priv->smstpcr_saved[reg].mask;  in cpg_mssr_resume_noirq()
910 		if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)  in cpg_mssr_resume_noirq()
911 			oldval = readb(priv->base + priv->control_regs[reg]);  in cpg_mssr_resume_noirq()
913 			oldval = readl(priv->base + priv->control_regs[reg]);  in cpg_mssr_resume_noirq()
915 		newval |= priv->smstpcr_saved[reg].val & mask;  in cpg_mssr_resume_noirq()
919 		if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {  in cpg_mssr_resume_noirq()
920 			writeb(newval, priv->base + priv->control_regs[reg]);  in cpg_mssr_resume_noirq()
922 			readb(priv->base + priv->control_regs[reg]);  in cpg_mssr_resume_noirq()
923 			barrier_data(priv->base + priv->control_regs[reg]);  in cpg_mssr_resume_noirq()
926 			writel(newval, priv->base + priv->control_regs[reg]);  in cpg_mssr_resume_noirq()
929 		mask &= ~priv->smstpcr_saved[reg].val;  in cpg_mssr_resume_noirq()
933 		error = readl_poll_timeout_atomic(priv->base + priv->status_regs[reg],  in cpg_mssr_resume_noirq()
960 	if (info->init) {  in cpg_mssr_common_init()
961 		error = info->init(dev);  in cpg_mssr_common_init()
966 	nclks = info->num_total_core_clks + info->num_hw_mod_clks;  in cpg_mssr_common_init()
969 		return -ENOMEM;  in cpg_mssr_common_init()
971 	priv->np = np;  in cpg_mssr_common_init()
972 	priv->dev = dev;  in cpg_mssr_common_init()
973 	spin_lock_init(&priv->rmw_lock);  in cpg_mssr_common_init()
975 	priv->base = of_iomap(np, 0);  in cpg_mssr_common_init()
976 	if (!priv->base) {  in cpg_mssr_common_init()
977 		error = -ENOMEM;  in cpg_mssr_common_init()
981 	priv->num_core_clks = info->num_total_core_clks;  in cpg_mssr_common_init()
982 	priv->num_mod_clks = info->num_hw_mod_clks;  in cpg_mssr_common_init()
983 	priv->last_dt_core_clk = info->last_dt_core_clk;  in cpg_mssr_common_init()
984 	RAW_INIT_NOTIFIER_HEAD(&priv->notifiers);  in cpg_mssr_common_init()
985 	priv->reg_layout = info->reg_layout;  in cpg_mssr_common_init()
986 	if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3) {  in cpg_mssr_common_init()
987 		priv->status_regs = mstpsr;  in cpg_mssr_common_init()
988 		priv->control_regs = smstpcr;  in cpg_mssr_common_init()
989 		priv->reset_regs = srcr;  in cpg_mssr_common_init()
990 		priv->reset_clear_regs = srstclr;  in cpg_mssr_common_init()
991 	} else if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {  in cpg_mssr_common_init()
992 		priv->control_regs = stbcr;  in cpg_mssr_common_init()
993 	} else if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_GEN4) {  in cpg_mssr_common_init()
994 		priv->status_regs = mstpsr_for_gen4;  in cpg_mssr_common_init()
995 		priv->control_regs = mstpcr_for_gen4;  in cpg_mssr_common_init()
996 		priv->reset_regs = srcr_for_gen4;  in cpg_mssr_common_init()
997 		priv->reset_clear_regs = srstclr_for_gen4;  in cpg_mssr_common_init()
999 		error = -EINVAL;  in cpg_mssr_common_init()
1004 		priv->clks[i] = ERR_PTR(-ENOENT);  in cpg_mssr_common_init()
1015 	if (priv->base)  in cpg_mssr_common_init()
1016 		iounmap(priv->base);  in cpg_mssr_common_init()
1032 	for (i = 0; i < info->num_early_core_clks; i++)  in cpg_mssr_early_init()
1033 		cpg_mssr_register_core_clk(&info->early_core_clks[i], info,  in cpg_mssr_early_init()
1036 	for (i = 0; i < info->num_early_mod_clks; i++)  in cpg_mssr_early_init()
1037 		cpg_mssr_register_mod_clk(&info->early_mod_clks[i], info,  in cpg_mssr_early_init()
1044 	struct device *dev = &pdev->dev;  in cpg_mssr_probe()
1045 	struct device_node *np = dev->of_node;  in cpg_mssr_probe()
1054 		error = cpg_mssr_common_init(dev, dev->of_node, info);  in cpg_mssr_probe()
1060 	priv->dev = dev;  in cpg_mssr_probe()
1063 	for (i = 0; i < info->num_core_clks; i++)  in cpg_mssr_probe()
1064 		cpg_mssr_register_core_clk(&info->core_clks[i], info, priv);  in cpg_mssr_probe()
1066 	for (i = 0; i < info->num_mod_clks; i++)  in cpg_mssr_probe()
1067 		cpg_mssr_register_mod_clk(&info->mod_clks[i], info, priv);  in cpg_mssr_probe()
1075 	error = cpg_mssr_add_clk_domain(dev, info->core_pm_clks,  in cpg_mssr_probe()
1076 					info->num_core_pm_clks);  in cpg_mssr_probe()
1081 	if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)  in cpg_mssr_probe()
1093 		.name	= "renesas-cpg-mssr",
1119 MODULE_DESCRIPTION("Renesas CPG/MSSR Driver");