Lines Matching +full:cpg +full:- +full:div6 +full:- +full:clock

1 /* SPDX-License-Identifier: GPL-2.0+ */
3  * Renesas RCar Gen3 CPG MSSR driver
5  * Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com>
8  * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
35  * Definitions of CPG Core Clocks
38  *   - Clock outputs exported to DT
39  *   - External input clocks
40  *   - Internal CPG clocks
56 	CLK_TYPE_IN,		/* External Clock Input */
57 	CLK_TYPE_FF,		/* Fixed Factor Clock */
58 	CLK_TYPE_DIV6P1,	/* DIV6 Clock with 1 parent clock */
59 	CLK_TYPE_DIV6_RO,	/* DIV6 Clock read only with extra divisor */
88 /* Convert from sparse base-100 to packed index space */
89 #define MOD_CLK_PACK(x)	((x) - ((x) / 100) * (100 - 32))