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/openbmc/openbmc-test-automation/ipmi/
H A Dtest_ipmi_poh_counter.robot2 Documentation This suite tests IPMI POH Counter Support in OpenBMC.
3 ... Feature: IPMI POH Counter Support
5 ... POH (Power-On Hours) counter is the incremental count of power ON
11 ... Get POH Counter Command Via IPMI
12 ... Verify Get POH Counter With Invalid Data Request Via IPMI
13 ... Verify POH Counter Reading With Wait Time
14 ... Verify POH Counter Reading With Host Power Off
15 ... Verify POH Counter Reading With Host Power On
17 ... Script compares Minutes per count and Counter reading for the above scenarios.
24 ... Comparison between Initial POH Counter reading and reading after wait
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/openbmc/qemu/include/hw/timer/
H A Dsse-counter.h2 * Arm SSE Subsystem System Counter
13 * This is a model of the "System counter" which is documented in
22 * Consumers of the system counter's timestamp, such as the SSE
25 * interact with an instance of the System Counter. Generally the
27 * code can set to the appropriate instance of the system counter.
37 #define TYPE_SSE_COUNTER "sse-counter"
71 * @counter: SSECounter
74 * Returns the value of the timestamp counter at the specified
78 uint64_t sse_counter_for_timestamp(SSECounter *counter, uint64_t ns);
82 * @counter: SSECounter
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/openbmc/u-boot/include/asm-generic/
H A Datomic.h6 typedef struct { volatile int counter; } atomic_t; member
8 typedef struct { volatile long long counter; } atomic64_t; member
10 typedef struct { volatile long counter; } atomic64_t; member
15 #define atomic_read(v) ((v)->counter)
16 #define atomic_set(v, i) ((v)->counter = (i))
25 v->counter += i; in atomic_add()
34 v->counter -= i; in atomic_sub()
43 ++v->counter; in atomic_inc()
52 --v->counter; in atomic_dec()
62 val = v->counter; in atomic_dec_and_test()
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/openbmc/u-boot/drivers/bootcount/
H A DKconfig20 bool "Generic default boot counter"
29 bool "Boot counter on EXT filesystem"
35 bool "Boot counter in AM33XX RTC IP block"
44 bool "Boot counter in environment"
56 bool "Boot counter in RAM"
62 bool "Boot counter on I2C device"
70 bool "Boot counter for Atmel AT91SAM9XE"
74 bool "Boot counter in a device-model device"
108 counter being cleared.
117 the boot counter.
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H A Dbootcount_ram.c47 ulong counter = 0; in bootcount_load() local
54 counter = readl(&save_addr[0]); in bootcount_load()
56 /* Is the counter reliable, check in the big pattern for bit errors */ in bootcount_load()
57 for (i = 0; (i < REPEAT_PATTERN) && (counter != 0); i++) { in bootcount_load()
60 counter = 0; in bootcount_load()
62 return counter; in bootcount_load()
/openbmc/qemu/include/hw/
H A Dptimer.h55 * - Starting to run with counter = 0 or setting it to "0" while timer
56 * is running causes a trigger and reloads counter with a limit value.
59 * - Counter value of the running timer is one less than the actual value.
63 * counter = counter value at the moment of change (.i.e. one less).
67 /* Periodic timer counter stays with "0" for a one period before wrapping
71 /* Running periodic timer that has counter = limit = 0 would continuously
75 /* Starting to run with/setting counter to "0" won't trigger immediately,
79 /* Starting to run with/setting counter to "0" won't re-load counter
83 /* Make counter value of the running timer represent the actual value and
88 * Starting to run with a zero counter, or setting the counter to "0" via
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/openbmc/qemu/hw/net/fsl_etsec/
H A Dregisters.c161 {0x680, "TR64", "Transmit and receive 64-byte frame counter ", ACC_RW, 0x0000000…
162 {0x684, "TR127", "Transmit and receive 65- to 127-byte frame counter", ACC_RW, 0x0000000…
163 {0x688, "TR255", "Transmit and receive 128- to 255-byte frame counter", ACC_RW, 0x0000000…
164 {0x68C, "TR511", "Transmit and receive 256- to 511-byte frame counter", ACC_RW, 0x0000000…
165 {0x690, "TR1K", "Transmit and receive 512- to 1023-byte frame counter", ACC_RW, 0x0000000…
166 {0x694, "TRMAX", "Transmit and receive 1024- to 1518-byte frame counter", ACC_RW, 0x0000000…
171 {0x69C, "RBYT", "Receive byte counter", ACC_RW, 0x00000000},
172 {0x6A0, "RPKT", "Receive packet counter", ACC_RW, 0x00000000},
173 {0x6A4, "RFCS", "Receive FCS error counter", ACC_RW, 0x00000000},
174 {0x6A8, "RMCA", "Receive multicast packet counter", ACC_RW, 0x00000000},
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/openbmc/qemu/target/arm/
H A Dcpregs-pmu.c48 * to occur. A negative value indicates the counter will never overflow, or
49 * that the counter has otherwise arranged for the overflow bit to be set
259 /* ER: event counter read trap control */ in pmreg_access_xevcntr()
289 /* ER: event counter read trap control */ in pmreg_access_selr()
303 /* CR: cycle counter read trap control */ in pmreg_access_ccntr()
315 * Returns true if the counter (pass 31 for PMCCNTR) should count events using
318 static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter) in pmu_counter_enabled() argument
341 (counter < hpmn || counter == 31)) { in pmu_counter_enabled()
346 enabled = e && (env->cp15.c9_pmcnten & (1 << counter)); in pmu_counter_enabled()
349 if (el == 2 && (counter < hpmn || counter == 31)) { in pmu_counter_enabled()
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/openbmc/u-boot/drivers/serial/
H A Dmcfuart.c29 u32 counter; in mcf_serial_init_common() local
49 counter = (u32) ((gd->bus_clk / 32) + (baudrate / 2)); in mcf_serial_init_common()
50 counter = counter / baudrate; in mcf_serial_init_common()
52 /* write to CTUR: divide counter upper byte */ in mcf_serial_init_common()
53 writeb((u8)((counter & 0xff00) >> 8), &uart->ubg1); in mcf_serial_init_common()
54 /* write to CTLR: divide counter lower byte */ in mcf_serial_init_common()
55 writeb((u8)(counter & 0x00ff), &uart->ubg2); in mcf_serial_init_common()
64 u32 counter; in mcf_serial_setbrg_common() local
67 counter = (u32) ((gd->bus_clk / 32) + (baudrate / 2)); in mcf_serial_setbrg_common()
68 counter = counter / baudrate; in mcf_serial_setbrg_common()
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/openbmc/qemu/hw/usb/
H A Du2f-emulated.c38 /* Counter which sync with a file */
40 /* Emulated device counter */
50 struct synced_counter *counter = (struct synced_counter *)vdev_counter; in counter_increment() local
51 ++counter->value; in counter_increment()
54 if (fseek(counter->fp, 0, SEEK_SET) == -1) { in counter_increment()
57 fprintf(counter->fp, "%u\n", counter->value); in counter_increment()
62 struct synced_counter *counter = (struct synced_counter *)vdev_counter; in counter_read() local
63 return counter->value; in counter_read()
82 char *counter; member
215 struct synced_counter *counter) in u2f_emulated_setup_counter() argument
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/openbmc/qemu/hw/timer/
H A Dnrf51_timer.c47 s->counter = (s->counter + ticks) % BIT(bitwidths[s->bitmode]); in update_counter()
57 /* Assumes s->counter is up-to-date */
70 if (s->cc[i] <= s->counter) { in rearm_timer()
72 s->counter + s->cc[i]); in rearm_timer()
74 delta_ns = ticks_to_ns(s, s->cc[i] - s->counter); in rearm_timer()
108 if (s->cc[i] > s->counter) { in timer_expire()
109 cc_remaining[i] = s->cc[i] - s->counter; in timer_expire()
112 s->counter + s->cc[i]; in timer_expire()
125 s->counter = 0; in timer_expire()
144 uint32_t counter = s->counter; in counter_compare() local
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H A Dsse-counter.c2 * Arm SSE Subsystem System Counter
13 * This is a model of the "System counter" which is documented in
17 * The system counter is a non-stop 64-bit up-counter. It provides
20 * from a clock. Internally to the counter the count is actually
34 #include "hw/timer/sse-counter.h"
50 * Although CNTCR defines interrupt-related bits, the counter doesn't
146 /* Counter is disabled and does not increment */ in sse_counter_for_timestamp()
154 * the underlying 88-bit counter for every tick of the in sse_counter_for_timestamp()
157 * how much the full 88-bit counter has moved on; we then in sse_counter_for_timestamp()
177 * Write one 32-bit half of the counter value; startbit is the in sse_write_cntcv()
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/openbmc/u-boot/arch/arm/include/asm/arch-lpc32xx/
H A Dtimer.h11 /* Timer/Counter Registers */
15 u32 tc; /* Timer Counter */
17 u32 pc; /* Prescale Counter */
27 /* Timer/Counter Interrupt Register bits */
31 /* Timer/Counter Timer Control Register bits */
36 /* Timer/Counter Match Control Register bits */
41 /* Timer/Counter Capture Control Register bits */
46 /* Timer/Counter External Match Register bits */
53 /* Timer/Counter Count Control Register bits */
/openbmc/u-boot/include/
H A Dfsl_fman.h43 u32 fmqm_etfc; /* enqueue total frame counter */
44 u32 fmqm_dtfc; /* dequeue total frame counter */
45 u32 fmqm_dc0; /* dequeue counter 0 */
46 u32 fmqm_dc1; /* dequeue counter 1 */
47 u32 fmqm_dc2; /* dequeue counter 2 */
48 u32 fmqm_dc3; /* dequeue counter 3 */
49 u32 fmqm_dfnoc; /* dequeue FQID not override counter */
50 u32 fmqm_dfcc; /* dequeue FQID from context counter */
51 u32 fmqm_dffc; /* dequeue FQID from FD counter */
52 u32 fmqm_dcc; /* dequeue confirm counter */
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/openbmc/qemu/target/riscv/
H A Dpmu.c108 PMUCTRState *counter = &env->pmu_ctrs[ctr_idx]; in riscv_pmu_incr_ctr_rv32() local
126 if (counter->mhpmcounter_val == max_val) { in riscv_pmu_incr_ctr_rv32()
127 if (counter->mhpmcounterh_val == max_val) { in riscv_pmu_incr_ctr_rv32()
128 counter->mhpmcounter_val = 0; in riscv_pmu_incr_ctr_rv32()
129 counter->mhpmcounterh_val = 0; in riscv_pmu_incr_ctr_rv32()
136 counter->mhpmcounterh_val++; in riscv_pmu_incr_ctr_rv32()
139 counter->mhpmcounter_val++; in riscv_pmu_incr_ctr_rv32()
148 PMUCTRState *counter = &env->pmu_ctrs[ctr_idx]; in riscv_pmu_incr_ctr_rv64() local
167 if (counter->mhpmcounter_val == max_val) { in riscv_pmu_incr_ctr_rv64()
168 counter->mhpmcounter_val = 0; in riscv_pmu_incr_ctr_rv64()
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/openbmc/u-boot/drivers/watchdog/
H A Darmada-37xx-wdt.c25 * We use Counter 1 as watchdog timer, and Counter 0 for re-triggering Counter 1
91 /* counter 1 is retriggered by forcing end count on counter 0 */ in a37xx_wdt_reset()
107 /* and then we start counter 1 by forcing end count on counter 0 */ in a37xx_wdt_expire_now()
134 /* we have to force end count on counter 0 to start counter 1 */ in a37xx_wdt_start()
169 * We use counter 1 as watchdog timer, therefore we only set bit in a37xx_wdt_probe()
170 * TIMER1_IS_WCHDOG_TIMER. Counter 0 is only used to force re-trigger on in a37xx_wdt_probe()
171 * counter 1. in a37xx_wdt_probe()
H A Dcdns_wdt.c19 u32 ccr; /* Counter Control Register offset - 0x4 */
39 /* Counter register access key */
42 /* Counter value divisor */
56 /* Counter maximum value */
72 * Counter Control register - This register controls how fast the timer runs
76 #define CDNS_WDT_CCR_CRV_MASK 0x00003FFC /* Counter reset value */
111 * The counter value is calculated according to the formula:
115 * to write to counter control register.
117 * Clears the contents of prescaler and counter reset value. Sets the
161 * Counter value divisor to obtain the value of in cdns_wdt_start()
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/openbmc/u-boot/arch/x86/include/asm/
H A Di8254.h19 #define PIT_CMD_CTR0 0x00 /* Select PIT counter 0 */
20 #define PIT_CMD_CTR1 0x40 /* Select PIT counter 1 */
21 #define PIT_CMD_CTR2 0x80 /* Select PIT counter 2 */
23 #define PIT_CMD_LATCH 0x00 /* Counter Latch Command */
24 #define PIT_CMD_LOW 0x10 /* Access counter bits 7-0 */
25 #define PIT_CMD_HIGH 0x20 /* Access counter bits 15-8 */
26 #define PIT_CMD_BOTH 0x30 /* Access counter bits 15-0 in two accesses */
H A Datomic.h8 typedef struct { volatile int counter; } atomic_t; member
25 return ACCESS_ONCE((v)->counter); in atomic_read()
37 v->counter = i; in atomic_set()
50 : "+m" (v->counter) in atomic_add()
64 : "+m" (v->counter) in atomic_sub()
77 : "+m" (v->counter)); in atomic_inc()
89 : "+m" (v->counter)); in atomic_dec()
/openbmc/telemetry/tests/src/
H A Dtest_unique_call.cpp16 uniqueCall1([this](auto context) { ++counter; }); in uniqueCallIncrementCounter()
22 ++counter; in uniqueCallWhileUniqueCallIsActiveIncrementCounter()
29 uint32_t counter = 0u; member in utils::TestUniqueCall
39 ASSERT_THAT(counter, Eq(3u)); in TEST_F()
49 ASSERT_THAT(counter, Eq(3u)); in TEST_F()
/openbmc/phosphor-fan-presence/docs/monitor/
H A Dmethod.md50 An up/down counter for determining when a fan's sensor should be marked
51 nonfunctional based on a `threshold` or functional when the counter = 0. Each
53 current target increments the counter by 1. Once the counter reaches the
55 feedback speed is within range, the counter is decremented by 1. Therefore the
59 nonfunctional fan sensor to become functional, where the counter must accumulate
60 enough times deemed within range to decrement the counter to 0. This checking
67 increment/decrement the counter. Defaults to 1s if not present.
/openbmc/openbmc/meta-arm/meta-arm-bsp/recipes-security/trusted-services/corstone1000/
H A D0012-Revert-Make-variable-index-usage-robust-with-redunda.patch45 - * Variable index counter is at the beginning, which is followed by metadata and
81 - * Variable index counter is at the beginning, which is followed by metadata and
97 - * Enough to fit the variable index counter and the metadata and constraint
120 - * Dump to now contains the variable index counter and metadata,
143 - /* Expect index to be dirty and dump to now contains only the variable index counter */
199 - /* There are no variables set in the index, only the counter is there */
204 - /* Counter of index A is 0 */
210 - /* Set max counter value */
216 - /* Counter of index B is max value */
222 - /* At next initialization of the store index A should be the latest index with counter value 0 */
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/openbmc/openbmc/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/
H A D0002-Platform-Corstone1000-Fix-NV-counter-writing.patch4 Subject: [PATCH 2/9] Platform: Corstone1000: Fix NV counter writing
6 The BL1 writes the PLAT_NV_COUNTER_BL1_0 NV counter directly without
11 priv_metadata->nv_counter[FWU_BL2_NV_COUNTER] to every NV counter.
46 + FWU_LOG_MSG("%s: couldn't read NV counter\n\r", __func__);
51 + FWU_LOG_MSG("%s: staged NV counter is smaller than current value\n\r", __func__);
54 - FWU_LOG_MSG("%s: updaing index = %u nv counter = %u->%u\n\r",
55 + FWU_LOG_MSG("%s: updating index = %u nv counter = %u->%u\n\r",
63 + FWU_LOG_MSG("%s: couldn't write NV counter\n\r", __func__);
/openbmc/qemu/scripts/
H A Du2f-setup-gen.py25 entropy: bytes, counter: int) -> None:
34 counter: The counter value.
51 # Counter
52 with open(f'{dirpath}/counter', 'w') as f:
53 f.write(f'{str(counter)}\n')
144 # Counter
145 counter = 0
148 write_setup_dir(dirpath, privkey_pem, certificate_pem, entropy, counter)
/openbmc/qemu/include/standard-headers/linux/
H A Dvmclock-abi.h6 * counter, etc.) and real time. It is designed to address the problem of
12 * counter will change within the tolerances of its specification (typically
17 * Second, there may be a step change in the value of the counter itself, as
34 * precise relationship of the CPU counter to real time, as calibrated by the
38 * counter being reliable and consistent across CPUs.
43 * actually messes with the apparent counter *period*. A linear smearing
44 * of 1 ms per second would effectively tweak the counter period by 1000PPM
84 * counter is disrupted, for example on live migration. This lets
86 * performed of the counter against external sources (NTP/PTP/etc.).
110 * In particular, a timestamp based on a counter reading taken
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