183d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2fea25720SGraeme Russ /* 3fea25720SGraeme Russ * (C) Copyright 2002 4fa82f871SAlbert ARIBAUD * Daniel Engström, Omicron Ceti AB, daniel@omicron.se. 5fea25720SGraeme Russ */ 6fea25720SGraeme Russ 7fea25720SGraeme Russ /* i8254.h Intel 8254 PIT registers */ 8fea25720SGraeme Russ 9fea25720SGraeme Russ #ifndef _ASMI386_I8254_H_ 100a2ea020SBin Meng #define _ASMI386_I8954_H_ 11fea25720SGraeme Russ 12fea25720SGraeme Russ #define PIT_T0 0x00 /* PIT channel 0 count/status */ 13fea25720SGraeme Russ #define PIT_T1 0x01 /* PIT channel 1 count/status */ 14fea25720SGraeme Russ #define PIT_T2 0x02 /* PIT channel 2 count/status */ 15fea25720SGraeme Russ #define PIT_COMMAND 0x03 /* PIT mode control, latch and read back */ 16fea25720SGraeme Russ 17fea25720SGraeme Russ /* PIT Command Register Bit Definitions */ 18fea25720SGraeme Russ 19fea25720SGraeme Russ #define PIT_CMD_CTR0 0x00 /* Select PIT counter 0 */ 20fea25720SGraeme Russ #define PIT_CMD_CTR1 0x40 /* Select PIT counter 1 */ 21fea25720SGraeme Russ #define PIT_CMD_CTR2 0x80 /* Select PIT counter 2 */ 22fea25720SGraeme Russ 23fea25720SGraeme Russ #define PIT_CMD_LATCH 0x00 /* Counter Latch Command */ 24fea25720SGraeme Russ #define PIT_CMD_LOW 0x10 /* Access counter bits 7-0 */ 25fea25720SGraeme Russ #define PIT_CMD_HIGH 0x20 /* Access counter bits 15-8 */ 26fea25720SGraeme Russ #define PIT_CMD_BOTH 0x30 /* Access counter bits 15-0 in two accesses */ 27fea25720SGraeme Russ 28fea25720SGraeme Russ #define PIT_CMD_MODE0 0x00 /* Select mode 0 */ 29fea25720SGraeme Russ #define PIT_CMD_MODE1 0x02 /* Select mode 1 */ 30fea25720SGraeme Russ #define PIT_CMD_MODE2 0x04 /* Select mode 2 */ 31fea25720SGraeme Russ #define PIT_CMD_MODE3 0x06 /* Select mode 3 */ 32fea25720SGraeme Russ #define PIT_CMD_MODE4 0x08 /* Select mode 4 */ 330a2ea020SBin Meng #define PIT_CMD_MODE5 0x0a /* Select mode 5 */ 34fea25720SGraeme Russ 3580de0495SBin Meng /* The clock frequency of the i8253/i8254 PIT */ 360a2ea020SBin Meng #define PIT_TICK_RATE 1193182 3780de0495SBin Meng 38*79a5be82SSimon Glass /** 39*79a5be82SSimon Glass * i8254_enable_beep() - Start a beep using the PCAT timer 40*79a5be82SSimon Glass * 41*79a5be82SSimon Glass * This starts beeping using the legacy i8254 timer. The beep may be silenced 42*79a5be82SSimon Glass * after a delay with i8254_disable_beep(). 43*79a5be82SSimon Glass * 44*79a5be82SSimon Glass * @frequency_hz: Frequency of beep in Hz 45*79a5be82SSimon Glass * @return 0 if OK, -EINVAL if frequency_hz is 0 46*79a5be82SSimon Glass */ 47*79a5be82SSimon Glass int i8254_enable_beep(uint frequency_hz); 48*79a5be82SSimon Glass 49*79a5be82SSimon Glass /** 50*79a5be82SSimon Glass * i8254_disable_beep() - Disable the bepper 51*79a5be82SSimon Glass * 52*79a5be82SSimon Glass * This stops any existing beep 53*79a5be82SSimon Glass */ 54*79a5be82SSimon Glass void i8254_disable_beep(void); 55*79a5be82SSimon Glass 560a2ea020SBin Meng #endif /* _ASMI386_I8954_H_ */ 57