Lines Matching full:counter
48 * to occur. A negative value indicates the counter will never overflow, or
49 * that the counter has otherwise arranged for the overflow bit to be set
259 /* ER: event counter read trap control */ in pmreg_access_xevcntr()
289 /* ER: event counter read trap control */ in pmreg_access_selr()
303 /* CR: cycle counter read trap control */ in pmreg_access_ccntr()
315 * Returns true if the counter (pass 31 for PMCCNTR) should count events using
318 static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter) in pmu_counter_enabled() argument
341 (counter < hpmn || counter == 31)) { in pmu_counter_enabled()
346 enabled = e && (env->cp15.c9_pmcnten & (1 << counter)); in pmu_counter_enabled()
349 if (el == 2 && (counter < hpmn || counter == 31)) { in pmu_counter_enabled()
356 if (counter == 31) { in pmu_counter_enabled()
358 * The cycle counter defaults to running. PMCR.DP says "disable in pmu_counter_enabled()
359 * the cycle counter when event counting is prohibited". in pmu_counter_enabled()
360 * Some MDCR bits disable the cycle counter specifically. in pmu_counter_enabled()
373 if (counter == 31) { in pmu_counter_enabled()
376 filter = env->cp15.c14_pmevtyper[counter]; in pmu_counter_enabled()
397 if (counter != 31) { in pmu_counter_enabled()
399 * If not checking PMCCNTR, ensure the counter is setup to an event we in pmu_counter_enabled()
421 * Return true if the clock divider is enabled and the cycle counter in pmccntr_clockdiv_enabled()
424 * (64-bit) cycle counter PMCR.D has no effect. in pmccntr_clockdiv_enabled()
429 static bool pmevcntr_is_64_bit(CPUARMState *env, int counter) in pmevcntr_is_64_bit() argument
431 /* Return true if the specified event counter is configured to be 64 bit */ in pmevcntr_is_64_bit()
433 /* This isn't intended to be used with the cycle counter */ in pmevcntr_is_64_bit()
434 assert(counter < 31); in pmevcntr_is_64_bit()
448 if (counter >= hpmn) { in pmevcntr_is_64_bit()
457 * enabling/disabling the counter or filtering, modifying the count itself,
458 * etc. can be done logically. This is essentially a no-op if the counter is
494 /* Calculate when the counter will next overflow */ in pmccntr_op_finish()
520 static void pmevcntr_op_start(CPUARMState *env, uint8_t counter) in pmevcntr_op_start() argument
523 uint16_t event = env->cp15.c14_pmevtyper[counter] & PMXEVTYPER_EVTCOUNT; in pmevcntr_op_start()
530 if (pmu_counter_enabled(env, counter)) { in pmevcntr_op_start()
531 uint64_t new_pmevcntr = count - env->cp15.c14_pmevcntr_delta[counter]; in pmevcntr_op_start()
532 uint64_t overflow_mask = pmevcntr_is_64_bit(env, counter) ? in pmevcntr_op_start()
535 if (env->cp15.c14_pmevcntr[counter] & ~new_pmevcntr & overflow_mask) { in pmevcntr_op_start()
536 env->cp15.c9_pmovsr |= (1 << counter); in pmevcntr_op_start()
539 env->cp15.c14_pmevcntr[counter] = new_pmevcntr; in pmevcntr_op_start()
541 env->cp15.c14_pmevcntr_delta[counter] = count; in pmevcntr_op_start()
544 static void pmevcntr_op_finish(CPUARMState *env, uint8_t counter) in pmevcntr_op_finish() argument
546 if (pmu_counter_enabled(env, counter)) { in pmevcntr_op_finish()
548 uint16_t event = env->cp15.c14_pmevtyper[counter] & PMXEVTYPER_EVTCOUNT; in pmevcntr_op_finish()
550 uint64_t delta = -(env->cp15.c14_pmevcntr[counter] + 1); in pmevcntr_op_finish()
553 if (!pmevcntr_is_64_bit(env, counter)) { in pmevcntr_op_finish()
569 env->cp15.c14_pmevcntr_delta[counter] -= in pmevcntr_op_finish()
570 env->cp15.c14_pmevcntr[counter]; in pmevcntr_op_finish()
607 * Update all the counter values based on the current underlying counts, in arm_pmu_timer_cb()
610 * counter may expire. in arm_pmu_timer_cb()
622 /* The counter has been reset */ in pmcr_write()
662 /* Increment a counter's count iff: */ in pmswinc_write()
663 if ((value & (1 << i)) && /* counter's bit is set */ in pmswinc_write()
664 /* counter is enabled and not filtered */ in pmswinc_write()
666 /* counter is SW_INCR */ in pmswinc_write()
787 uint64_t value, const uint8_t counter) in pmevtyper_write() argument
789 if (counter == 31) { in pmevtyper_write()
791 } else if (counter < pmu_num_counters(env)) { in pmevtyper_write()
792 pmevcntr_op_start(env, counter); in pmevtyper_write()
795 * If this counter's event type is changing, store the current in pmevtyper_write()
796 * underlying count for the new type in c14_pmevcntr_delta[counter] so in pmevtyper_write()
800 uint16_t old_event = env->cp15.c14_pmevtyper[counter] & in pmevtyper_write()
809 env->cp15.c14_pmevcntr_delta[counter] = count; in pmevtyper_write()
812 env->cp15.c14_pmevtyper[counter] = value & PMXEVTYPER_MASK; in pmevtyper_write()
813 pmevcntr_op_finish(env, counter); in pmevtyper_write()
823 const uint8_t counter) in pmevtyper_read() argument
825 if (counter == 31) { in pmevtyper_read()
827 } else if (counter < pmu_num_counters(env)) { in pmevtyper_read()
828 return env->cp15.c14_pmevtyper[counter]; in pmevtyper_read()
841 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); in pmevtyper_writefn() local
842 pmevtyper_write(env, ri, value, counter); in pmevtyper_writefn()
848 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); in pmevtyper_rawwrite() local
849 env->cp15.c14_pmevtyper[counter] = value; in pmevtyper_rawwrite()
856 * different counter type. Therefore, we need to set this value to the in pmevtyper_rawwrite()
857 * current count for the counter type we're writing so that pmu_op_finish in pmevtyper_rawwrite()
863 env->cp15.c14_pmevcntr_delta[counter] = in pmevtyper_rawwrite()
870 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); in pmevtyper_readfn() local
871 return pmevtyper_read(env, ri, counter); in pmevtyper_readfn()
886 uint64_t value, uint8_t counter) in pmevcntr_write() argument
892 if (counter < pmu_num_counters(env)) { in pmevcntr_write()
893 pmevcntr_op_start(env, counter); in pmevcntr_write()
894 env->cp15.c14_pmevcntr[counter] = value; in pmevcntr_write()
895 pmevcntr_op_finish(env, counter); in pmevcntr_write()
904 uint8_t counter) in pmevcntr_read() argument
906 if (counter < pmu_num_counters(env)) { in pmevcntr_read()
908 pmevcntr_op_start(env, counter); in pmevcntr_read()
909 ret = env->cp15.c14_pmevcntr[counter]; in pmevcntr_read()
910 pmevcntr_op_finish(env, counter); in pmevcntr_read()
928 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); in pmevcntr_writefn() local
929 pmevcntr_write(env, ri, value, counter); in pmevcntr_writefn()
934 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); in pmevcntr_readfn() local
935 return pmevcntr_read(env, ri, counter); in pmevcntr_readfn()
941 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); in pmevcntr_rawwrite() local
942 assert(counter < pmu_num_counters(env)); in pmevcntr_rawwrite()
943 env->cp15.c14_pmevcntr[counter] = value; in pmevcntr_rawwrite()
944 pmevcntr_write(env, ri, value, counter); in pmevcntr_rawwrite()
949 uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7); in pmevcntr_rawread() local
950 assert(counter < pmu_num_counters(env)); in pmevcntr_rawread()
951 return env->cp15.c14_pmevcntr[counter]; in pmevcntr_rawread()