xref: /openbmc/u-boot/arch/x86/include/asm/i8254.h (revision c507d306)
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2002
4  * Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
5  */
6 
7 /* i8254.h Intel 8254 PIT registers */
8 
9 #ifndef _ASMI386_I8254_H_
10 #define _ASMI386_I8954_H_
11 
12 #define PIT_T0		0x00	/* PIT channel 0 count/status */
13 #define PIT_T1		0x01	/* PIT channel 1 count/status */
14 #define PIT_T2		0x02	/* PIT channel 2 count/status */
15 #define PIT_COMMAND	0x03	/* PIT mode control, latch and read back */
16 
17 /* PIT Command Register Bit Definitions */
18 
19 #define PIT_CMD_CTR0	0x00	/* Select PIT counter 0 */
20 #define PIT_CMD_CTR1	0x40	/* Select PIT counter 1 */
21 #define PIT_CMD_CTR2	0x80	/* Select PIT counter 2 */
22 
23 #define PIT_CMD_LATCH	0x00	/* Counter Latch Command */
24 #define PIT_CMD_LOW	0x10	/* Access counter bits 7-0 */
25 #define PIT_CMD_HIGH	0x20	/* Access counter bits 15-8 */
26 #define PIT_CMD_BOTH	0x30	/* Access counter bits 15-0 in two accesses */
27 
28 #define PIT_CMD_MODE0	0x00	/* Select mode 0 */
29 #define PIT_CMD_MODE1	0x02	/* Select mode 1 */
30 #define PIT_CMD_MODE2	0x04	/* Select mode 2 */
31 #define PIT_CMD_MODE3	0x06	/* Select mode 3 */
32 #define PIT_CMD_MODE4	0x08	/* Select mode 4 */
33 #define PIT_CMD_MODE5	0x0a	/* Select mode 5 */
34 
35 /* The clock frequency of the i8253/i8254 PIT */
36 #define PIT_TICK_RATE	1193182
37 
38 /**
39  * i8254_enable_beep() - Start a beep using the PCAT timer
40  *
41  * This starts beeping using the legacy i8254 timer. The beep may be silenced
42  * after a delay with i8254_disable_beep().
43  *
44  * @frequency_hz: Frequency of beep in Hz
45  * @return 0 if OK, -EINVAL if frequency_hz is 0
46  */
47 int i8254_enable_beep(uint frequency_hz);
48 
49 /**
50  * i8254_disable_beep() - Disable the bepper
51  *
52  * This stops any existing beep
53  */
54 void i8254_disable_beep(void);
55 
56 #endif /* _ASMI386_I8954_H_ */
57