Lines Matching full:counter

19 	u32 ccr;	/* Counter Control Register offset - 0x4 */
39 /* Counter register access key */
42 /* Counter value divisor */
56 /* Counter maximum value */
72  * Counter Control register - This register controls how fast the timer runs
76 #define CDNS_WDT_CCR_CRV_MASK	0x00003FFC /* Counter reset value */
111  * The counter value is calculated according to the formula:
115  * to write to counter control register.
117  * Clears the contents of prescaler and counter reset value. Sets the
161 	 * Counter value divisor to obtain the value of  in cdns_wdt_start()
162 	 * counter reset to be written to control register.  in cdns_wdt_start()
174 	/* Write counter access key first to be able write to register */  in cdns_wdt_start()