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/openbmc/u-boot/doc/device-tree-bindings/clock/
H A Dst,stm32mp1.txt1 STMicroelectronics STM32MP1 clock tree initialization
4 The STM32MP clock tree initialization is based on device tree information
7 -------------------------------
8 RCC CLOCK = st,stm32mp1-rcc-clk
9 -------------------------------
11 The RCC IP is both a reset and a clock controller but this documentation only
12 describes the fields added for clock tree initialization which are not present
15 Please refer to ../mfd/st,stm32-rcc.txt for all the other properties common
20 - compatible: Should be "st,stm32mp1-rcc-clk"
22 - st,clksrc : The clock source in this order
[all …]
H A Dmicrochip,pic32-clock.txt1 * Microchip PIC32 Clock and Oscillator
3 Microchip PIC32 clock tree consists of few oscillators, PLLs,
5 to various controllers within SoC and also to off-chip.
7 PIC32 clock controller output is defined by indices as defined
10 [0] include/dt-bindings/clock/microchip,clock.h
13 - compatible: should be "microchip,pic32mzda_clk"
14 - reg: physical base address of the controller and length of memory mapped
16 - #clock-cells: should be 1.
18 Example: Clock controller node:
20 clock: clk@1f801200 {
[all …]
H A Dsnps,hsdk-cgu.txt1 * Synopsys HSDK clock generation unit
3 The Synopsys HSDK clock controller generates and supplies clock to various
8 - compatible: should be "snps,hsdk-cgu-clock"
9 - reg: the pair of physical base address and length of clock generation unit
11 - #clock-cells: should be 1.
13 Each clock is assigned an identifier and client nodes can use this identifier
14 to specify the clock which they consume. All available clocks are defined as
15 preprocessor macros in the dt-bindings/clock/snps,hsdk-cgu.h headers and can be
16 used in device tree sources.
18 Example: Clock controller node:
[all …]
H A Dst,stm32h7-rcc.txt1 STMicroelectronics STM32H7 Reset and Clock Controller
4 The RCC IP is both a reset and a clock controller.
6 Please refer to clock-bindings.txt for common clock controller binding usage.
10 - compatible: Should be:
11 "st,stm32h743-rcc"
13 - reg: should be register base and length as documented in the
16 - #reset-cells: 1, see below
18 - #clock-cells : from common clock binding; shall be set to 1
20 - clocks: External oscillator clock phandle
21 - high speed external clock signal (HSE)
[all …]
H A Drockchip,rk3288-cru.txt1 * Rockchip RK3288 Clock and Reset Unit
3 The RK3288 clock controller generates and supplies clock to various
9 - compatible: should be "rockchip,rk3288-cru"
10 - reg: physical base address of the controller and length of memory mapped
12 - #clock-cells: should be 1.
13 - #reset-cells: should be 1.
17 - rockchip,grf: phandle to the syscon managing the "general register files"
20 Each clock is assigned an identifier and client nodes can use this identifier
21 to specify the clock which they consume. All available clocks are defined as
22 preprocessor macros in the dt-bindings/clock/rk3288-cru.h headers and can be
[all …]
H A Drockchip,rk3188-cru.txt1 * Rockchip RK3188/RK3066 Clock and Reset Unit
3 The RK3188/RK3066 clock controller generates and supplies clock to various
9 - compatible: should be "rockchip,rk3188-cru", "rockchip,rk3188a-cru" or
10 "rockchip,rk3066a-cru"
11 - reg: physical base address of the controller and length of memory mapped
13 - #clock-cells: should be 1.
14 - #reset-cells: should be 1.
18 - rockchip,grf: phandle to the syscon managing the "general register files"
21 Each clock is assigned an identifier and client nodes can use this identifier
22 to specify the clock which they consume. All available clocks are defined as
[all …]
/openbmc/u-boot/include/
H A Dclk-uclass.h1 /* SPDX-License-Identifier: GPL-2.0+ */
18 * struct clk_ops - The functions that a clock driver must implement.
22 * of_xlate - Translate a client's device-tree (OF) clock specifier.
24 * The clock core calls this function as the first step in implementing
27 * If this function pointer is set to NULL, the clock core will use a
28 * default implementation, which assumes #clock-cells = <1>, and that
29 * the DT cell contains a simple integer clock ID.
31 * At present, the clock API solely supports device-tree. If this
35 * @clock: The clock struct to hold the translation result.
36 * @args: The clock specifier values from device tree.
[all …]
H A Dclk.h1 /* SPDX-License-Identifier: GPL-2.0+ */
15 * A clock is a hardware signal that oscillates autonomously at a specific
16 * frequency and duty cycle. Most hardware modules require one or more clock
17 * signal to drive their operation. Clock signals are typically generated
19 * clock provider. This API provides a standard means for drivers to enable and
22 * A driver that implements UCLASS_CLOCK is a clock provider. A provider will
24 * often has this capability. clk-uclass.h describes the interface which
25 * clock providers must implement.
27 * Clock consumers/clients are the HW modules driven by the clock signals. This
34 * struct clk - A handle to (allowing control of) a single clock.
[all …]
/openbmc/u-boot/drivers/clk/at91/
H A DKconfig2 bool "AT91 clock drivers"
6 This option is used to enable the AT91 clock driver.
7 The driver supports the AT91 clock generator, including
8 the oscillators and PLLs, such as main clock, slow clock,
9 PLLA, UTMI PLL. Clocks can also be a source clock of other
10 clocks a tree structure, such as master clock, usb device
11 clock, matrix clock and generic clock.
12 Devices can use a common clock API to request a particular
13 clock, enable it and get its rate.
16 bool "Support UTMI PLL Clock"
[all …]
/openbmc/u-boot/doc/device-tree-bindings/remoteproc/
H A Dk3-rproc.txt5 cannot be done directly from U-Boot. In order to load an image,
10 --------------------
11 - compatible: Shall be: "ti,am654-rproc"
12 - reg: base address of the remoteproc timer.
13 - power-domains: Should contain two sets of entries:
18 doc/device-tree-bindings/power/ti,sci-pm-domain.txt
19 - resets: Should contain a phandle to a reset controller node
22 doc/device-tree-bindings/reset/ti,sci-reset.txt
23 - ti,sci: Phandle to TI-SCI compatible System controller node.
24 - ti,sci-proc-id: Processor id as identified by TISCI
[all …]
/openbmc/u-boot/doc/
H A DREADME.fsl-hwconfig1 Freescale-specific 'hwconfig' options.
3 This file documents Freescale-specific key:value pairs for the 'hwconfig'
11 route either a 11.2896MHz or a 12.288MHz clock. The default is
13 will be programmed accordingly. Second, the clock-frequency property
14 in the codec node in the device tree will be updated to the correct
18 Select the 11.2896MHz clock
21 Select the 12.288MHz clock
28 - which controller mode to use
29 - which USB PHY to use
31 This is used by generic USB device-tree fixup function to update
/openbmc/qemu/hw/core/
H A Dsysbus-fdt.c2 * ARM Platform Bus device tree generation helpers
30 #include "hw/core/sysbus-fdt.h"
31 #include "qemu/error-report.h"
34 #include "hw/platform-bus.h"
35 #include "hw/vfio/vfio-platform.h"
36 #include "hw/vfio/vfio-calxeda-xgmac.h"
37 #include "hw/vfio/vfio-amd-xgbe.h"
38 #include "hw/vfio/vfio-region.h"
40 #include "hw/uefi/var-service-api.h"
48 void *fdt; /* device tree handle */
[all …]
/openbmc/telemetry/src/
H A Dreport_factory.cpp6 #include "utils/clock.hpp"
31 -> std::shared_ptr<interfaces::Metric> { in make()
39 std::make_unique<Clock>()); in make()
43 bus->get_io_context(), objServer, id, name, reportingType, in make()
46 std::make_unique<Clock>(), std::move(readings)); in make()
61 metric->dumpConfiguration(); in updateMetrics()
77 std::make_unique<Clock>())); in updateMetrics()
81 newMetrics.back()->initialize(); in updateMetrics()
89 metric->deinitialize(); in updateMetrics()
104 -> std::shared_ptr<interfaces::Sensor> { in getSensors()
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dexynos4x12.dtsi2 * Samsung's Exynos4x12 SoCs device tree source
12 * Exynos4x12 SoC. As device tree coverage for Exynos4x12 increases, additional
21 #include "exynos4x12-pinctrl.dtsi"
22 #include "exynos4x12-pinctrl-uboot.dtsi"
32 pd_isp: isp-power-domain@10023CA0 {
33 compatible = "samsung,exynos4210-pd";
37 clock: clock-controller@10030000 { label
38 compatible = "samsung,exynos4412-clock";
40 #clock-cells = <1>;
44 compatible = "samsung,exynos4412-mct";
[all …]
H A Dsalvator-x.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the Salvator-X board
5 * Copyright (C) 2015-2016 Renesas Electronics Corp.
8 #include "salvator-common.dtsi"
11 model = "Renesas Salvator-X board";
12 compatible = "renesas,salvator-x";
16 clock-frequency = <16666666>;
20 clock-frequency = <400000>;
22 versaclock5: clock-generator@6a {
25 #clock-cells = <1>;
[all …]
H A Dexynos4210.dtsi2 * Samsung's Exynos4210 SoC device tree source
4 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
6 * Copyright (c) 2010-2011 Linaro Ltd.
14 * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional
23 #include "exynos4210-pinctrl.dtsi"
24 #include "exynos4210-pinctrl-uboot.dtsi"
35 pd_lcd1: lcd1-power-domain@10023CA0 {
36 compatible = "samsung,exynos4210-pd";
40 gic: interrupt-controller@10490000 {
41 cpu-offset = <0x8000>;
[all …]
H A Ds900.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 // Device Tree Source for Actions Semi S900 SoC
8 /dts-v1/;
9 #include <dt-bindings/clock/s900_cmu.h>
13 #address-cells = <0x2>;
14 #size-cells = <0x2>;
17 compatible = "fixed-clock";
18 clock-frequency = <32768>;
19 #clock-cells = <0>;
23 compatible = "fixed-clock";
[all …]
/openbmc/u-boot/doc/device-tree-bindings/memory-controllers/
H A Dk3-am654-ddrss.txt15 --------------------
16 - compatible: Shall be: "ti,am654-ddrss"
17 - reg-names ss - Map the sub system wrapper logic region
18 ctl - Map the controller region
19 phy - Map the PHY region
20 - reg: Contains the register map per reg-names.
21 - power-domains: Should contain a phandle to a PM domain provider node
24 doc/device-tree-bindings/power/ti,sci-pm-domain.txt
25 - clocks: Must contain an entry for enabling DDR clock. Should
26 be defined as per the appropriate clock bindings consumer
[all …]
/openbmc/u-boot/drivers/clk/mediatek/
H A Dclk-mtk.c1 // SPDX-License-Identifier: GPL-2.0
3 * MediaTek common clock driver
10 #include <clk-uclass.h>
15 #include "clk-mtk.h"
28 /* scpsys clock off control */
51 return -ENODEV; in mtk_clk_find_parent_rate()
55 parent.dev = clk->dev; in mtk_clk_find_parent_rate()
66 while (mux->parent[index] != parent) in mtk_clk_mux_set_parent()
67 if (++index == mux->num_parents) in mtk_clk_mux_set_parent()
68 return -EINVAL; in mtk_clk_mux_set_parent()
[all …]
/openbmc/u-boot/doc/device-tree-bindings/net/
H A Dsnps,dwc-qos-ethernet.txt10 - compatible: One of:
11 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
12 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
13 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
15 - "snps,dwc-qos-ethernet-4.10"
17 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
19 - reg: Address and length of the register set for the device
20 - clocks: Phandle and clock specifiers for each entry in clock-names, in the
21 same order. See ../clock/clock-bindings.txt.
22 - clock-names: May contain any/all of the following depending on the IP
[all …]
/openbmc/u-boot/board/st/stm32mp1/
H A Dstm32mp1.c1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
10 #include <generic-phy.h>
39 const void *blob = gd->fdt_blob; in board_usb_init()
47 node = fdt_node_offset_by_compatible(blob, -1, "snps,dwc2"); in board_usb_init()
50 return -ENODEV; in board_usb_init()
54 debug("stm32 usbotg is disabled in the device tree\n"); in board_usb_init()
55 return -ENODEV; in board_usb_init()
58 /* Enable clock */ in board_usb_init()
60 "#clock-cells", 0, 0, &args); in board_usb_init()
[all …]
/openbmc/u-boot/doc/device-tree-bindings/cpu/
H A Dnios2.txt3 This binding specifies what properties available in the device tree
6 Users can use sopc2dts tool for generating device tree sources (dts) from a
11 - compatible: Compatible property value should be "altr,nios2-1.0" or
12 "altr,nios2-1.1".
13 - reg: Contains CPU index.
14 - clock-frequency: Contains the clock frequency for CPU, in Hz.
15 - dcache-line-size: Contains data cache line size.
16 - icache-line-size: Contains instruction line size.
17 - dcache-size: Contains data cache size.
18 - icache-size: Contains instruction cache size.
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-tegra/
H A Dclock.h1 /* SPDX-License-Identifier: GPL-2.0+ */
6 /* Tegra clock control functions */
25 * Note that no Tegra clock register actually uses all of bits 31:28 as
29 * register. As such, the U-Boot clock driver is currently a bit lazy, and
39 #include <asm/arch/clock-tables.h>
43 /* return the current oscillator clock frequency */
52 * @param id clock id
67 * @param clkid clock id
71 * @return 0 if ok, -1 on error (invalid clock id or no suitable divider)
77 * Read low-level parameters of a PLL.
[all …]
/openbmc/u-boot/doc/device-tree-bindings/spi/
H A Dspi-zynq-qspi.txt1 Xilinx Zynq QSPI controller Device Tree Bindings
2 -------------------------------------------------
5 - compatible : Should be "xlnx,zynq-qspi-1.0".
6 - reg : Physical base address and size of QSPI registers map.
7 - interrupts : Property with a value describing the interrupt
9 - interrupt-parent : Must be core interrupt controller
10 - clock-names : List of input clock names - "ref_clk", "pclk"
11 (See clock bindings for details).
12 - clocks : Clock phandles (see clock bindings for details).
15 - num-cs : Number of chip selects used.
[all …]
/openbmc/u-boot/board/synopsys/hsdk/
H A Dclk-lib.h1 /* SPDX-License-Identifier: GPL-2.0+ */
15 CLK_ON = BIT(2), /* enable clock */
16 CLK_OFF = BIT(3), /* disable clock */
23 * set clock rate from 'rate' argument / read clock to 'rate' argument /
24 * print clock rate. If CLK_MHZ flag set in clk_ctl_ops 'rate' is in MHz,
25 * otherwise - in Hz.
27 * This function expects "clk-fmeas" node in device tree:
29 * clk-fmeas {
31 * clock-names = "cpu-pll", "sys-pll";

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