1*e80dac0aSEugeniy Paltsev* Synopsys HSDK clock generation unit 2*e80dac0aSEugeniy Paltsev 3*e80dac0aSEugeniy PaltsevThe Synopsys HSDK clock controller generates and supplies clock to various 4*e80dac0aSEugeniy Paltsevcontrollers and peripherals within the SoC. 5*e80dac0aSEugeniy Paltsev 6*e80dac0aSEugeniy PaltsevRequired Properties: 7*e80dac0aSEugeniy Paltsev 8*e80dac0aSEugeniy Paltsev- compatible: should be "snps,hsdk-cgu-clock" 9*e80dac0aSEugeniy Paltsev- reg: the pair of physical base address and length of clock generation unit 10*e80dac0aSEugeniy Paltsev memory mapped region and creg arc core divider memory mapped region. 11*e80dac0aSEugeniy Paltsev- #clock-cells: should be 1. 12*e80dac0aSEugeniy Paltsev 13*e80dac0aSEugeniy PaltsevEach clock is assigned an identifier and client nodes can use this identifier 14*e80dac0aSEugeniy Paltsevto specify the clock which they consume. All available clocks are defined as 15*e80dac0aSEugeniy Paltsevpreprocessor macros in the dt-bindings/clock/snps,hsdk-cgu.h headers and can be 16*e80dac0aSEugeniy Paltsevused in device tree sources. 17*e80dac0aSEugeniy Paltsev 18*e80dac0aSEugeniy PaltsevExample: Clock controller node: 19*e80dac0aSEugeniy Paltsev 20*e80dac0aSEugeniy Paltsev cgu_clk: cgu-clk@f0000000 { 21*e80dac0aSEugeniy Paltsev compatible = "snps,hsdk-cgu-clock"; 22*e80dac0aSEugeniy Paltsev reg = <0xf0000000 0x1000>, <0xf00014B8 0x4>; 23*e80dac0aSEugeniy Paltsev #clock-cells = <1>; 24*e80dac0aSEugeniy Paltsev }; 25*e80dac0aSEugeniy Paltsev 26*e80dac0aSEugeniy PaltsevExample: UART controller node that consumes the clock generated by the clock 27*e80dac0aSEugeniy Paltsevcontroller: 28*e80dac0aSEugeniy Paltsev 29*e80dac0aSEugeniy Paltsev uart0: serial0@f0005000 { 30*e80dac0aSEugeniy Paltsev compatible = "snps,dw-apb-uart"; 31*e80dac0aSEugeniy Paltsev reg = <0xf0005000 0x1000>; 32*e80dac0aSEugeniy Paltsev reg-shift = <2>; 33*e80dac0aSEugeniy Paltsev reg-io-width = <4>; 34*e80dac0aSEugeniy Paltsev clocks = <&cgu_clk CLK_SYS_UART_REF>; 35*e80dac0aSEugeniy Paltsev }; 36