asm/arch-tegra/clock.h

1 /* SPDX-License-Identifier: GPL-2.0+ */
6 /* Tegra clock control functions */
25  * Note that no Tegra clock register actually uses all of bits 31:28 as
29  * register. As such, the U-Boot clock driver is currently a bit lazy, and
39 #include <asm/arch/clock-tables.h>
43 /* return the current oscillator clock frequency */
52  * @param id	clock id
67  * @param clkid	clock id
71  * @return 0 if ok, -1 on error (invalid clock id or no suitable divider)
77  * Read low-level parameters of a PLL.
79  * @param id	clock id to read (note: USB is not supported)
86  * @returns 0 if ok, -1 on error (invalid clock id)
92  * Enable a clock
94  * @param id	clock id
99  * Disable a clock
101  * @param id	clock id
106  * Set whether a clock is enabled or disabled.
108  * @param id		clock id
143  * @param cpu		cpu number (0 or 1 on Tegra2, 0-3 on Tegra3)
145  * @param reset		1 to assert reset, 0 to de-assert
150  * Set the source for a peripheral clock. This plus the divisor sets the
151  * clock rate. You need to look up the datasheet to see the meaning of the
154  * Warning: This function is only for use pre-relocation. Please use
158  * @param source	source clock (0, 1, 2 or 3)
167  * @param mux_bits	number of mux bits for the clock
168  * @param source	source clock (0-15 depending on mux_bits)
174  * Set the source and divisor for a peripheral clock. This sets the
175  * clock rate. You need to look up the datasheet to see the meaning of the
178  * Warning: This function is only for use pre-relocation. Please use
182  * @param source	source clock (0, 1, 2 or 3)
189  * Returns the current parent clock ID of a given peripheral. This can be
191  * specific knowledge of system-level clock tree structure.
194  * @return clock ID of the peripheral's current parent clock
199  * Start a peripheral PLL clock at the given rate. This also resets the
203  * @param parent	PLL id of required parent clock
204  * @param rate		Required clock rate in Hz
205  * @return rate selected in Hz, or -1U if something went wrong
211  * Returns the rate of a peripheral clock in Hz. Since the caller almost
212  * certainly knows the parent clock (having just set it) we require that
216  * @param parent	PLL id of parent clock (used to calculate rate, you
218  * @return clock rate of peripheral in Hz
224  * Adjust peripheral PLL clock to the given rate. This does not reset the
230  * @param parent	PLL id of required parent clock
231  * @param rate		Required clock rate in Hz
232  * @param extra_div	value for the second-stage divisor (NULL if one is
234  * @return rate selected in Hz, or -1U if something went wrong
240  * Returns the clock rate of a specified clock, in Hz.
242  * @param parent	PLL id of clock to check
243  * @return rate of clock in Hz
248  * Start up a UART using low-level calls
251  * function provides a way to set up a UART using low-level calls which
259  * Decode a peripheral ID from a device tree node.
262  * the second cell, which is the clock number / peripheral ID.
280  * @return 0 if ok, -1 on error
293 /* Returns a pointer to the clock source register for a peripheral */
301  * clock's register, the number of divider bits the clock has, and the SoC-
302  * specific clock type.
304  * This is an internal API between the core Tegra clock code and the SoC-
305  * specific clock code.
310  * @param type          Set to the SoC-specific clock type
311  * @return 0 on success, -1 on error
317  * Given a peripheral ID and clock source mux value, determine the clock_id
320  * This is an internal API between the core Tegra clock code and the SoC-
321  * specific clock code.
324  * @param source        raw clock source mux value
330  * Given a peripheral ID and the required source clock, this returns which
336  * @param source        PLL id of required parent clock
339  * @return mux value (0-4, or -1 if not found)
345  * Convert a device tree clock ID to our peripheral ID. They are mostly
346  * the same but we are very cautious so we check that a valid clock ID is
349  * @param clk_id        Clock ID according to tegra30 device tree binding
350  * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
355  * Set the output frequency you want for each PLL clock.
368  * @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot
381 /* SoC-specific TSC init */
386 /* Number of PLL-based clocks (i.e. not OSC, MCLK or 32KHz) */
387 #define CLOCK_ID_PLL_COUNT	(CLOCK_ID_COUNT - 3)
414  * Enable output clock for external peripherals
416  * @param clk_id	Clock ID to output (1, 2 or 3)
417  * @return 0 if OK. -ve on error