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/openbmc/qemu/include/hw/
H A Dqdev-clock.h2 * Device's clock input and output
4 * Copyright GreenSocs 2016-2020
11 * See the COPYING file in the top-level directory.
17 #include "hw/clock.h"
21 * @dev: the device to add an input clock to
22 * @name: the name of the clock (can't be NULL).
27 * @returns: a pointer to the newly added clock
29 * Add an input clock to device @dev as a clock named @name.
33 Clock *qdev_init_clock_in(DeviceState *dev, const char *name,
39 * @dev: the device to add an output clock to
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/openbmc/linux/include/linux/
H A Dclk-provider.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
14 * top-level framework. custom flags for dealing with hardware specifics
20 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
26 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
29 #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
31 /* parents need enable during gate/ungate, set rate and re-parent */
33 /* duty cycle call may be forwarded to the parent clock */
42 * struct clk_rate_request - Structure encoding the clk constraints that
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/openbmc/qemu/hw/core/
H A Dqdev-clock.c2 * Device's clock input and output
4 * Copyright GreenSocs 2016-2020
11 * See the COPYING file in the top-level directory.
15 #include "qemu/error-report.h"
16 #include "hw/qdev-clock.h"
17 #include "hw/qdev-core.h"
22 * Add a new clock in a device
24 static NamedClockList *qdev_init_clocklist(DeviceState *dev, const char *name, in qdev_init_clocklist() argument
25 bool output, Clock *clk) in qdev_init_clocklist()
30 * Clock must be added before realize() so that we can compute the in qdev_init_clocklist()
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/openbmc/linux/drivers/clk/zynqmp/
H A Dclkc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Zynq UltraScale+ MPSoC clock controller
5 * Copyright (C) 2016-2019 Xilinx
12 #include <linux/clk-provider.h>
19 #include "clk-zynqmp.h"
49 * struct clock_parent - Clock parent
50 * @name: Parent name
51 * @id: Parent clock ID
55 char name[MAX_NAME_LEN]; member
61 * struct zynqmp_clock - Clock
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H A Dclk-gate-zynqmp.c1 // SPDX-License-Identifier: GPL-2.0
3 * Zynq UltraScale+ MPSoC clock controller
5 * Copyright (C) 2016-2018 Xilinx
7 * Gated clock implementation
10 #include <linux/clk-provider.h>
12 #include "clk-zynqmp.h"
15 * struct zynqmp_clk_gate - gating clock
16 * @hw: handle between common and hardware-specific interfaces
17 * @flags: hardware-specific flags
18 * @clk_id: Id of clock
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/openbmc/linux/drivers/clk/samsung/
H A Dclk.h1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Common Clock Framework support for all Samsung platforms
13 #include <linux/clk-provider.h>
14 #include "clk-pll.h"
17 * struct samsung_clk_provider: information about clock provider
19 * @dev: clock provider device needed for runtime PM.
20 * @lock: maintains exclusion between callbacks for a given clock-provider.
21 * @clk_data: holds clock related data like clk_hw* and number of clocks.
32 * struct samsung_clock_alias: information about mux clock
33 * @id: platform specific id of the clock.
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/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dxgene.txt1 Device Tree Clock bindings for APM X-Gene
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
10 "apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
11 "apm,xgene-pmd-clock" - for a X-Gene PMD clock
12 "apm,xgene-device-clock" - for a X-Gene device clock
13 "apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock
14 "apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock
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/openbmc/linux/drivers/isdn/mISDN/
H A Dclock.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * A clock source registers using mISDN_register_clock:
8 * name = text string to name clock source
9 * priority = value to priorize clock sources (0 = default)
10 * ctl = callback function to enable/disable clock source
11 * priv = private pointer of clock source
12 * return = pointer to clock source structure;
17 * A clock source calls mISDN_clock_update with given samples elapsed, if
21 * A clock source unregisters using mISDN_unregister_clock.
23 * To get current clock, call mISDN_clock_get. The signed short value
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/openbmc/linux/drivers/clk/uniphier/
H A Dclk-uniphier-core.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include <linux/clk-provider.h>
13 #include "clk-uniphier.h"
19 switch (data->type) { in uniphier_clk_register()
21 return uniphier_clk_register_cpugear(dev, regmap, data->name, in uniphier_clk_register()
22 &data->data.cpugear); in uniphier_clk_register()
24 return uniphier_clk_register_fixed_factor(dev, data->name, in uniphier_clk_register()
25 &data->data.factor); in uniphier_clk_register()
27 return uniphier_clk_register_fixed_rate(dev, data->name, in uniphier_clk_register()
28 &data->data.rate); in uniphier_clk_register()
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/openbmc/linux/arch/arm/boot/dts/samsung/
H A Dexynos4412-odroid-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Common definition for Hardkernel's Exynos4412 based ODROID-X/X2/U2/U3 boards
7 #include <dt-bindings/sound/samsung-i2s.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/clock/maxim,max77686.h>
11 #include "exynos4412-ppmu-common.dtsi"
12 #include <dt-bindings/gpio/gpio.h>
13 #include "exynos-mfc-reserved-memory.dtsi"
22 stdout-path = &serial_1;
26 compatible = "samsung,secure-firmware";
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H A Dexynos4210-trats.dts1 // SPDX-License-Identifier: GPL-2.0
12 /dts-v1/;
14 #include <dt-bindings/gpio/gpio.h>
19 chassis-type = "handset";
37 stdout-path = "serial2:115200n8";
40 vemmc_reg: regulator-0 {
41 compatible = "regulator-fixed";
42 regulator-name = "VMEM_VDD_2.8V";
43 regulator-min-microvolt = <2800000>;
44 regulator-max-microvolt = <2800000>;
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H A Dexynos4210-i9100.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos4210 based Galaxy S2 (GT-I9100 version) device tree
11 /dts-v1/;
13 #include "exynos4412-ppmu-common.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/input/linux-event-codes.h>
19 model = "Samsung Galaxy S2 (GT-I9100)";
21 chassis-type = "handset";
35 stdout-path = "serial2:115200n8";
38 vemmc_reg: regulator-0 {
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H A Dexynos4210-universal_c210.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
12 /dts-v1/;
14 #include <dt-bindings/gpio/gpio.h>
19 chassis-type = "handset";
35 stdout-path = "serial2:115200n8";
39 fixed-rate-clocks {
41 compatible = "samsung,clock-xxti";
42 clock-frequency = <0>;
46 compatible = "samsung,clock-xusbxti";
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/openbmc/linux/drivers/clk/renesas/
H A Dclk-mstp.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car MSTP clocks
12 #include <linux/clk-provider.h>
26 * status register when enabling the clock.
32 * struct mstp_clock_group - MSTP gating clocks group
34 * @data: clock specifier translation for clocks in this group
38 * @width_8bit: registers are 8-bit, not 32-bit
51 * struct mstp_clock - MSTP gating clock
52 * @hw: handle between common and hardware-specific interfaces
67 return group->width_8bit ? readb(reg) : readl(reg); in cpg_mstp_read()
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/openbmc/linux/drivers/clk/
H A Dclk-fixed-factor.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
13 * DOC: basic fixed multiplier and divider clock that cannot gate
15 * Traits of this clock:
16 * prepare - clk_prepare only ensures that parents are prepared
17 * enable - clk_enable only ensures that parents are enabled
18 * rate - rate is fixed. clk->rate = parent->rate / div * mult
19 * parent - fixed parent. No clk_set_parent support
28 rate = (unsigned long long int)parent_rate * fix->mult; in clk_factor_recalc_rate()
29 do_div(rate, fix->div); in clk_factor_recalc_rate()
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/openbmc/linux/drivers/clk/ti/
H A Dadpll.c1 // SPDX-License-Identifier: GPL-2.0-only
5 #include <linux/clk-provider.h>
177 const char *name; in ti_adpll_clk_get_name() local
181 err = of_property_read_string_index(d->np, in ti_adpll_clk_get_name()
182 "clock-output-names", in ti_adpll_clk_get_name()
184 &name); in ti_adpll_clk_get_name()
188 name = devm_kasprintf(d->dev, GFP_KERNEL, "%08lx.adpll.%s", in ti_adpll_clk_get_name()
189 d->pa, postfix); in ti_adpll_clk_get_name()
192 return name; in ti_adpll_clk_get_name()
197 static int ti_adpll_setup_clock(struct ti_adpll_data *d, struct clk *clock, in ti_adpll_setup_clock() argument
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H A Dclk.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI clock support
7 * Tero Kristo <t-kristo@ti.com>
11 #include <linux/clk-provider.h>
23 #include "clock.h"
43 struct clk_iomap *io = clk_memmaps[reg->index]; in clk_memmap_writel()
45 if (reg->ptr) in clk_memmap_writel()
46 writel_relaxed(val, reg->ptr); in clk_memmap_writel()
47 else if (io->regmap) in clk_memmap_writel()
48 regmap_write(io->regmap, reg->offset, val); in clk_memmap_writel()
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/openbmc/qemu/hw/misc/
H A Dnpcm7xx_clk.c2 * Nuvoton NPCM7xx Clock Control Registers.
21 #include "hw/qdev-clock.h"
23 #include "qemu/error-report.h"
32 * The reference clock hz, and the SECCNT and CNTR25M registers in this module,
38 #define NPCM7XX_CLK_WDRCR_CA9C BIT(0) /* Cortex-A9 Cores */
81 * All are loaded on power-up reset. CLKENx and SWRSTR should also be loaded on
109 /* Clock converter functions */
111 #define TYPE_NPCM7XX_CLOCK_PLL "npcm7xx-clock-pll"
114 #define TYPE_NPCM7XX_CLOCK_SEL "npcm7xx-clock-sel"
117 #define TYPE_NPCM7XX_CLOCK_DIVIDER "npcm7xx-clock-divider"
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/openbmc/qemu/include/hw/misc/
H A Dnpcm7xx_clk.h2 * Nuvoton NPCM7xx Clock Control Registers.
20 #include "hw/clock.h"
29 #define NPCM7XX_WATCHDOG_RESET_GPIO_IN "npcm7xx-clk-watchdog-reset-gpio-in"
31 /* Maximum amount of clock inputs in a SEL module. */
86 * struct NPCM7xxClockPLLState - A PLL module in CLK module.
87 * @name: The name of the module.
89 * @clock_in: The input clock of this module.
90 * @clock_out: The output clock of this module.
96 const char *name; member
98 Clock *clock_in;
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/openbmc/linux/drivers/clk/bcm/
H A Dclk-bcm2835.c1 // SPDX-License-Identifier: GPL-2.0+
8 * DOC: BCM2835 CPRMAN (clock manager for the "audio" domain)
10 * The clock tree on the 2835 has several levels. There's a root
22 * skip layers of the tree (for example, the pixel clock comes
23 * directly from the PLLH PIX channel without using a CM_*CTL clock
27 #include <linux/clk-provider.h>
38 #include <dt-bindings/clock/bcm2835.h>
45 # define CM_DIV_FRAC_MASK GENMASK(CM_DIV_FRAC_BITS - 1, 0)
253 # define A2W_PLL_FRAC_MASK ((1 << A2W_PLL_FRAC_BITS) - 1)
301 * with an external parent's name. This array is in the order that
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H A Dclk-bcm63xx-gate.c1 // SPDX-License-Identifier: GPL-2.0
3 #include <linux/clk-provider.h>
8 #include <dt-bindings/clock/bcm3368-clock.h>
9 #include <dt-bindings/clock/bcm6318-clock.h>
10 #include <dt-bindings/clock/bcm6328-clock.h>
11 #include <dt-bindings/clock/bcm6358-clock.h>
12 #include <dt-bindings/clock/bcm6362-clock.h>
13 #include <dt-bindings/clock/bcm6368-clock.h>
14 #include <dt-bindings/clock/bcm63268-clock.h>
17 const char * const name; member
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H A Dclk-kona-setup.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include "clk-kona.h"
13 #define selector_clear_exists(sel) ((sel)->width = 0)
20 struct ccu_policy *ccu_policy = &ccu->policy; in ccu_data_offsets_valid()
23 limit = ccu->range - sizeof(u32); in ccu_data_offsets_valid()
26 if (ccu_policy->enable.offset > limit) { in ccu_data_offsets_valid()
29 ccu->name, ccu_policy->enable.offset, limit); in ccu_data_offsets_valid()
32 if (ccu_policy->control.offset > limit) { in ccu_data_offsets_valid()
35 ccu->name, ccu_policy->control.offset, limit); in ccu_data_offsets_valid()
45 struct peri_clk_data *peri = bcm_clk->u.peri; in clk_requires_trigger()
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/openbmc/linux/drivers/platform/x86/intel/int3472/
H A Dclk_and_regulator.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
16 * 82c0d13a-78c5-4244-9bb1-eb8b539a8d11
30 if (clk->ena_gpio) { in skl_int3472_enable_clk()
31 gpiod_set_value_cansleep(clk->ena_gpio, enable); in skl_int3472_enable_clk()
36 args[0].integer.value = clk->imgclk_index; in skl_int3472_enable_clk()
46 acpi_evaluate_dsm(acpi_device_handle(int3472->adev), &img_clk_guid, in skl_int3472_enable_clk()
71 * We're just turning a GPIO on to enable the clock, which operation in skl_int3472_clk_enable()
89 obj = skl_int3472_get_acpi_buffer(int3472->sensor, "SSDB"); in skl_int3472_get_clk_frequency()
93 if (obj->buffer.length < CIO2_SENSOR_SSDB_MCLKSPEED_OFFSET + sizeof(u32)) { in skl_int3472_get_clk_frequency()
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/openbmc/linux/tools/testing/selftests/vDSO/
H A Dvdso_test_correctness.c1 // SPDX-License-Identifier: GPL-2.0
3 * ldt_gdt.c - Test cases for LDT and GDT access
4 * Copyright (c) 2011-2015 Andrew Lutomirski
25 static const char **name; variable
46 /* max length of lines in /proc/self/maps - anything longer is skipped here */
82 char name[MAPS_LINE_LEN]; in vsyscall_getcpu() local
84 /* sscanf() is safe here as strlen(name) >= strlen(line) */ in vsyscall_getcpu()
85 if (sscanf(line, "%p-%p %c-%cp %*x %*x:%*x %*u %s", in vsyscall_getcpu()
86 &start, &end, &r, &x, name) != 5) in vsyscall_getcpu()
89 if (strcmp(name, "[vsyscall]")) in vsyscall_getcpu()
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/openbmc/linux/Documentation/devicetree/bindings/clock/ti/davinci/
H A Dpll.txt5 an multiplexers for various clock signals.
8 - compatible: shall be one of:
9 - "ti,da850-pll0" for PLL0 on DA850/OMAP-L138/AM18XX
10 - "ti,da850-pll1" for PLL1 on DA850/OMAP-L138/AM18XX
11 - reg: physical base address and size of the controller's register area.
12 - clocks: phandles corresponding to the clock names
13 - clock-names: names of the clock sources - depends on compatible string
14 - for "ti,da850-pll0", shall be "clksrc", "extclksrc"
15 - for "ti,da850-pll1", shall be "clksrc"
18 - ti,clkmode-square-wave: Indicates that the board is supplying a square
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