1ebafb63dSStephen Boyd /* SPDX-License-Identifier: GPL-2.0 */
2b2476490SMike Turquette /*
3b2476490SMike Turquette * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
4b2476490SMike Turquette * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
5b2476490SMike Turquette */
6b2476490SMike Turquette #ifndef __LINUX_CLK_PROVIDER_H
7b2476490SMike Turquette #define __LINUX_CLK_PROVIDER_H
8b2476490SMike Turquette
9355bb165SMaxime Ripard #include <linux/of.h>
10eb06d6bbSGeert Uytterhoeven #include <linux/of_clk.h>
11b2476490SMike Turquette
12b2476490SMike Turquette /*
13b2476490SMike Turquette * flags used across common struct clk. these flags should only affect the
14b2476490SMike Turquette * top-level framework. custom flags for dealing with hardware specifics
15b2476490SMike Turquette * belong in struct clk_foo
16a6059ab9SGeert Uytterhoeven *
17a6059ab9SGeert Uytterhoeven * Please update clk_flags[] in drivers/clk/clk.c when making changes here!
18b2476490SMike Turquette */
19b2476490SMike Turquette #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
20b2476490SMike Turquette #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
21b2476490SMike Turquette #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
22b2476490SMike Turquette #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
23b9610e74SStephen Boyd /* unused */
2490b6c5c7SStephen Boyd /* unused */
25a093bde2SUlf Hansson #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
26819c1de3SJames Hogan #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
275279fc40SBoris BREZILLON #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
28d8d91987SBartlomiej Zolnierkiewicz #define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */
292eb8c710SHeiko Stuebner #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
3032b9b109SLee Jones #define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */
31a4b3518dSDong Aisheng /* parents need enable during gate/ungate, set rate and re-parent */
32a4b3518dSDong Aisheng #define CLK_OPS_PARENT_ENABLE BIT(12)
339fba738aSJerome Brunet /* duty cycle call may be forwarded to the parent clock */
349fba738aSJerome Brunet #define CLK_DUTY_CYCLE_PARENT BIT(13)
35b2476490SMike Turquette
3661ae7656SStephen Boyd struct clk;
370197b3eaSSaravana Kannan struct clk_hw;
38035a61c3STomeu Vizoso struct clk_core;
39c646cbf1SAlex Elder struct dentry;
400197b3eaSSaravana Kannan
41b2476490SMike Turquette /**
420817b62cSBoris Brezillon * struct clk_rate_request - Structure encoding the clk constraints that
430817b62cSBoris Brezillon * a clock user might require.
440817b62cSBoris Brezillon *
45c35e84b0SMaxime Ripard * Should be initialized by calling clk_hw_init_rate_request().
46c35e84b0SMaxime Ripard *
47ef13f8b6SMaxime Ripard * @core: Pointer to the struct clk_core affected by this request
480817b62cSBoris Brezillon * @rate: Requested clock rate. This field will be adjusted by
490817b62cSBoris Brezillon * clock drivers according to hardware capabilities.
500817b62cSBoris Brezillon * @min_rate: Minimum rate imposed by clk users.
511971dfb7SMasahiro Yamada * @max_rate: Maximum rate imposed by clk users.
520817b62cSBoris Brezillon * @best_parent_rate: The best parent rate a parent can provide to fulfill the
530817b62cSBoris Brezillon * requested constraints.
540817b62cSBoris Brezillon * @best_parent_hw: The most appropriate parent clock that fulfills the
550817b62cSBoris Brezillon * requested constraints.
560817b62cSBoris Brezillon *
570817b62cSBoris Brezillon */
580817b62cSBoris Brezillon struct clk_rate_request {
59ef13f8b6SMaxime Ripard struct clk_core *core;
600817b62cSBoris Brezillon unsigned long rate;
610817b62cSBoris Brezillon unsigned long min_rate;
620817b62cSBoris Brezillon unsigned long max_rate;
630817b62cSBoris Brezillon unsigned long best_parent_rate;
640817b62cSBoris Brezillon struct clk_hw *best_parent_hw;
650817b62cSBoris Brezillon };
660817b62cSBoris Brezillon
67c35e84b0SMaxime Ripard void clk_hw_init_rate_request(const struct clk_hw *hw,
68c35e84b0SMaxime Ripard struct clk_rate_request *req,
69c35e84b0SMaxime Ripard unsigned long rate);
70262ca38fSMaxime Ripard void clk_hw_forward_rate_request(const struct clk_hw *core,
71262ca38fSMaxime Ripard const struct clk_rate_request *old_req,
72262ca38fSMaxime Ripard const struct clk_hw *parent,
73262ca38fSMaxime Ripard struct clk_rate_request *req,
74262ca38fSMaxime Ripard unsigned long parent_rate);
75c35e84b0SMaxime Ripard
760817b62cSBoris Brezillon /**
77823ef44aSRandy Dunlap * struct clk_duty - Structure encoding the duty cycle ratio of a clock
789fba738aSJerome Brunet *
799fba738aSJerome Brunet * @num: Numerator of the duty cycle ratio
809fba738aSJerome Brunet * @den: Denominator of the duty cycle ratio
819fba738aSJerome Brunet */
829fba738aSJerome Brunet struct clk_duty {
839fba738aSJerome Brunet unsigned int num;
849fba738aSJerome Brunet unsigned int den;
859fba738aSJerome Brunet };
869fba738aSJerome Brunet
879fba738aSJerome Brunet /**
88b2476490SMike Turquette * struct clk_ops - Callback operations for hardware clocks; these are to
89b2476490SMike Turquette * be provided by the clock implementation, and will be called by drivers
90b2476490SMike Turquette * through the clk_* api.
91b2476490SMike Turquette *
92b2476490SMike Turquette * @prepare: Prepare the clock for enabling. This must not return until
93b2476490SMike Turquette * the clock is fully prepared, and it's safe to call clk_enable.
94b2476490SMike Turquette * This callback is intended to allow clock implementations to
95b2476490SMike Turquette * do any initialisation that may sleep. Called with
96b2476490SMike Turquette * prepare_lock held.
97b2476490SMike Turquette *
98b2476490SMike Turquette * @unprepare: Release the clock from its prepared state. This will typically
99b2476490SMike Turquette * undo any work done in the @prepare callback. Called with
100b2476490SMike Turquette * prepare_lock held.
101b2476490SMike Turquette *
1023d6ee287SUlf Hansson * @is_prepared: Queries the hardware to determine if the clock is prepared.
1033d6ee287SUlf Hansson * This function is allowed to sleep. Optional, if this op is not
1043d6ee287SUlf Hansson * set then the prepare count will be used.
1053d6ee287SUlf Hansson *
1063cc8247fSUlf Hansson * @unprepare_unused: Unprepare the clock atomically. Only called from
1073cc8247fSUlf Hansson * clk_disable_unused for prepare clocks with special needs.
1083cc8247fSUlf Hansson * Called with prepare mutex held. This function may sleep.
1093cc8247fSUlf Hansson *
110b2476490SMike Turquette * @enable: Enable the clock atomically. This must not return until the
111b2476490SMike Turquette * clock is generating a valid clock signal, usable by consumer
112b2476490SMike Turquette * devices. Called with enable_lock held. This function must not
113b2476490SMike Turquette * sleep.
114b2476490SMike Turquette *
115b2476490SMike Turquette * @disable: Disable the clock atomically. Called with enable_lock held.
116b2476490SMike Turquette * This function must not sleep.
117b2476490SMike Turquette *
118119c7127SStephen Boyd * @is_enabled: Queries the hardware to determine if the clock is enabled.
119119c7127SStephen Boyd * This function must not sleep. Optional, if this op is not
120119c7127SStephen Boyd * set then the enable count will be used.
121119c7127SStephen Boyd *
1227c045a55SMike Turquette * @disable_unused: Disable the clock atomically. Only called from
1237c045a55SMike Turquette * clk_disable_unused for gate clocks with special needs.
1247c045a55SMike Turquette * Called with enable_lock held. This function must not
1257c045a55SMike Turquette * sleep.
1267c045a55SMike Turquette *
1278b95d1ceSRuss Dill * @save_context: Save the context of the clock in prepration for poweroff.
1288b95d1ceSRuss Dill *
1298b95d1ceSRuss Dill * @restore_context: Restore the context of the clock after a restoration
1308b95d1ceSRuss Dill * of power.
1318b95d1ceSRuss Dill *
132823ef44aSRandy Dunlap * @recalc_rate: Recalculate the rate of this clock, by querying hardware. The
133b2476490SMike Turquette * parent rate is an input parameter. It is up to the caller to
134f24a0b1cSMaxime Ripard * ensure that the prepare_mutex is held across this call. If the
135f24a0b1cSMaxime Ripard * driver cannot figure out a rate for this clock, it must return
136f24a0b1cSMaxime Ripard * 0. Returns the calculated rate. Optional, but recommended - if
137b2476490SMike Turquette * this op is not set then clock rate will be initialized to 0.
138b2476490SMike Turquette *
139b2476490SMike Turquette * @round_rate: Given a target rate as input, returns the closest rate actually
14054e73016SGeert Uytterhoeven * supported by the clock. The parent rate is an input/output
14154e73016SGeert Uytterhoeven * parameter.
142b2476490SMike Turquette *
14371472c0cSJames Hogan * @determine_rate: Given a target rate as input, returns the closest rate
14471472c0cSJames Hogan * actually supported by the clock, and optionally the parent clock
14571472c0cSJames Hogan * that should be used to provide the clock rate.
14671472c0cSJames Hogan *
14754e73016SGeert Uytterhoeven * @set_parent: Change the input source of this clock; for clocks with multiple
14854e73016SGeert Uytterhoeven * possible parents specify a new parent by passing in the index
14954e73016SGeert Uytterhoeven * as a u8 corresponding to the parent in either the .parent_names
15054e73016SGeert Uytterhoeven * or .parents arrays. This function in affect translates an
15154e73016SGeert Uytterhoeven * array index into the value programmed into the hardware.
15254e73016SGeert Uytterhoeven * Returns 0 on success, -EERROR otherwise.
15354e73016SGeert Uytterhoeven *
154b2476490SMike Turquette * @get_parent: Queries the hardware to determine the parent of a clock. The
155b2476490SMike Turquette * return value is a u8 which specifies the index corresponding to
156b2476490SMike Turquette * the parent clock. This index can be applied to either the
157b2476490SMike Turquette * .parent_names or .parents arrays. In short, this function
158b2476490SMike Turquette * translates the parent value read from hardware into an array
159b2476490SMike Turquette * index. Currently only called when the clock is initialized by
160b2476490SMike Turquette * __clk_init. This callback is mandatory for clocks with
161b2476490SMike Turquette * multiple parents. It is optional (and unnecessary) for clocks
162b2476490SMike Turquette * with 0 or 1 parents.
163b2476490SMike Turquette *
1641c0035d7SShawn Guo * @set_rate: Change the rate of this clock. The requested rate is specified
1651c0035d7SShawn Guo * by the second argument, which should typically be the return
1661c0035d7SShawn Guo * of .round_rate call. The third argument gives the parent rate
1671c0035d7SShawn Guo * which is likely helpful for most .set_rate implementation.
1681c0035d7SShawn Guo * Returns 0 on success, -EERROR otherwise.
169b2476490SMike Turquette *
1703fa2252bSStephen Boyd * @set_rate_and_parent: Change the rate and the parent of this clock. The
1713fa2252bSStephen Boyd * requested rate is specified by the second argument, which
1723fa2252bSStephen Boyd * should typically be the return of .round_rate call. The
1733fa2252bSStephen Boyd * third argument gives the parent rate which is likely helpful
1743fa2252bSStephen Boyd * for most .set_rate_and_parent implementation. The fourth
1753fa2252bSStephen Boyd * argument gives the parent index. This callback is optional (and
1763fa2252bSStephen Boyd * unnecessary) for clocks with 0 or 1 parents as well as
1773fa2252bSStephen Boyd * for clocks that can tolerate switching the rate and the parent
1783fa2252bSStephen Boyd * separately via calls to .set_parent and .set_rate.
1793fa2252bSStephen Boyd * Returns 0 on success, -EERROR otherwise.
1803fa2252bSStephen Boyd *
18154e73016SGeert Uytterhoeven * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy
18254e73016SGeert Uytterhoeven * is expressed in ppb (parts per billion). The parent accuracy is
18354e73016SGeert Uytterhoeven * an input parameter.
18454e73016SGeert Uytterhoeven * Returns the calculated accuracy. Optional - if this op is not
18554e73016SGeert Uytterhoeven * set then clock accuracy will be initialized to parent accuracy
18654e73016SGeert Uytterhoeven * or 0 (perfect clock) if clock has no parent.
18754e73016SGeert Uytterhoeven *
1889824cf73SMaxime Ripard * @get_phase: Queries the hardware to get the current phase of a clock.
1899824cf73SMaxime Ripard * Returned values are 0-359 degrees on success, negative
1909824cf73SMaxime Ripard * error codes on failure.
1919824cf73SMaxime Ripard *
192e59c5371SMike Turquette * @set_phase: Shift the phase this clock signal in degrees specified
193e59c5371SMike Turquette * by the second argument. Valid values for degrees are
194e59c5371SMike Turquette * 0-359. Return 0 on success, otherwise -EERROR.
195e59c5371SMike Turquette *
1969fba738aSJerome Brunet * @get_duty_cycle: Queries the hardware to get the current duty cycle ratio
1979fba738aSJerome Brunet * of a clock. Returned values denominator cannot be 0 and must be
1989fba738aSJerome Brunet * superior or equal to the numerator.
1999fba738aSJerome Brunet *
2009fba738aSJerome Brunet * @set_duty_cycle: Apply the duty cycle ratio to this clock signal specified by
2019fba738aSJerome Brunet * the numerator (2nd argurment) and denominator (3rd argument).
2029fba738aSJerome Brunet * Argument must be a valid ratio (denominator > 0
2039fba738aSJerome Brunet * and >= numerator) Return 0 on success, otherwise -EERROR.
2049fba738aSJerome Brunet *
20554e73016SGeert Uytterhoeven * @init: Perform platform-specific initialization magic.
2066c4411f1SRandy Dunlap * This is not used by any of the basic clock types.
20789d079dcSJerome Brunet * This callback exist for HW which needs to perform some
20889d079dcSJerome Brunet * initialisation magic for CCF to get an accurate view of the
20989d079dcSJerome Brunet * clock. It may also be used dynamic resource allocation is
21089d079dcSJerome Brunet * required. It shall not used to deal with clock parameters,
21189d079dcSJerome Brunet * such as rate or parents.
21289d079dcSJerome Brunet * Returns 0 on success, -EERROR otherwise.
21354e73016SGeert Uytterhoeven *
214f873744cSJerome Brunet * @terminate: Free any resource allocated by init.
215f873744cSJerome Brunet *
216c646cbf1SAlex Elder * @debug_init: Set up type-specific debugfs entries for this clock. This
217c646cbf1SAlex Elder * is called once, after the debugfs directory entry for this
218c646cbf1SAlex Elder * clock has been created. The dentry pointer representing that
219c646cbf1SAlex Elder * directory is provided as an argument. Called with
220c646cbf1SAlex Elder * prepare_lock held. Returns 0 on success, -EERROR otherwise.
221c646cbf1SAlex Elder *
2223fa2252bSStephen Boyd *
223b2476490SMike Turquette * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow
224b2476490SMike Turquette * implementations to split any work between atomic (enable) and sleepable
225b2476490SMike Turquette * (prepare) contexts. If enabling a clock requires code that might sleep,
226b2476490SMike Turquette * this must be done in clk_prepare. Clock enable code that will never be
2277ce3e8ccSStephen Boyd * called in a sleepable context may be implemented in clk_enable.
228b2476490SMike Turquette *
229b2476490SMike Turquette * Typically, drivers will call clk_prepare when a clock may be needed later
230b2476490SMike Turquette * (eg. when a device is opened), and clk_enable when the clock is actually
231b2476490SMike Turquette * required (eg. from an interrupt). Note that clk_prepare MUST have been
232b2476490SMike Turquette * called before clk_enable.
233b2476490SMike Turquette */
234b2476490SMike Turquette struct clk_ops {
235b2476490SMike Turquette int (*prepare)(struct clk_hw *hw);
236b2476490SMike Turquette void (*unprepare)(struct clk_hw *hw);
2373d6ee287SUlf Hansson int (*is_prepared)(struct clk_hw *hw);
2383cc8247fSUlf Hansson void (*unprepare_unused)(struct clk_hw *hw);
239b2476490SMike Turquette int (*enable)(struct clk_hw *hw);
240b2476490SMike Turquette void (*disable)(struct clk_hw *hw);
241b2476490SMike Turquette int (*is_enabled)(struct clk_hw *hw);
2427c045a55SMike Turquette void (*disable_unused)(struct clk_hw *hw);
2438b95d1ceSRuss Dill int (*save_context)(struct clk_hw *hw);
2448b95d1ceSRuss Dill void (*restore_context)(struct clk_hw *hw);
245b2476490SMike Turquette unsigned long (*recalc_rate)(struct clk_hw *hw,
246b2476490SMike Turquette unsigned long parent_rate);
24754e73016SGeert Uytterhoeven long (*round_rate)(struct clk_hw *hw, unsigned long rate,
24854e73016SGeert Uytterhoeven unsigned long *parent_rate);
2490817b62cSBoris Brezillon int (*determine_rate)(struct clk_hw *hw,
2500817b62cSBoris Brezillon struct clk_rate_request *req);
251b2476490SMike Turquette int (*set_parent)(struct clk_hw *hw, u8 index);
252b2476490SMike Turquette u8 (*get_parent)(struct clk_hw *hw);
25354e73016SGeert Uytterhoeven int (*set_rate)(struct clk_hw *hw, unsigned long rate,
25454e73016SGeert Uytterhoeven unsigned long parent_rate);
2553fa2252bSStephen Boyd int (*set_rate_and_parent)(struct clk_hw *hw,
2563fa2252bSStephen Boyd unsigned long rate,
2573fa2252bSStephen Boyd unsigned long parent_rate, u8 index);
2585279fc40SBoris BREZILLON unsigned long (*recalc_accuracy)(struct clk_hw *hw,
2595279fc40SBoris BREZILLON unsigned long parent_accuracy);
2609824cf73SMaxime Ripard int (*get_phase)(struct clk_hw *hw);
261e59c5371SMike Turquette int (*set_phase)(struct clk_hw *hw, int degrees);
2629fba738aSJerome Brunet int (*get_duty_cycle)(struct clk_hw *hw,
2639fba738aSJerome Brunet struct clk_duty *duty);
2649fba738aSJerome Brunet int (*set_duty_cycle)(struct clk_hw *hw,
2659fba738aSJerome Brunet struct clk_duty *duty);
26689d079dcSJerome Brunet int (*init)(struct clk_hw *hw);
267f873744cSJerome Brunet void (*terminate)(struct clk_hw *hw);
268d75d50c0SStephen Boyd void (*debug_init)(struct clk_hw *hw, struct dentry *dentry);
269b2476490SMike Turquette };
270b2476490SMike Turquette
2710197b3eaSSaravana Kannan /**
272fc0c209cSStephen Boyd * struct clk_parent_data - clk parent information
273fc0c209cSStephen Boyd * @hw: parent clk_hw pointer (used for clk providers with internal clks)
274fc0c209cSStephen Boyd * @fw_name: parent name local to provider registering clk
275fc0c209cSStephen Boyd * @name: globally unique parent name (used as a fallback)
276601b6e93SStephen Boyd * @index: parent index local to provider registering clk (if @fw_name absent)
277fc0c209cSStephen Boyd */
278fc0c209cSStephen Boyd struct clk_parent_data {
279fc0c209cSStephen Boyd const struct clk_hw *hw;
280fc0c209cSStephen Boyd const char *fw_name;
281fc0c209cSStephen Boyd const char *name;
282601b6e93SStephen Boyd int index;
283fc0c209cSStephen Boyd };
284fc0c209cSStephen Boyd
285fc0c209cSStephen Boyd /**
2860197b3eaSSaravana Kannan * struct clk_init_data - holds init data that's common to all clocks and is
2870197b3eaSSaravana Kannan * shared between the clock provider and the common clock framework.
2880197b3eaSSaravana Kannan *
2890197b3eaSSaravana Kannan * @name: clock name
2900197b3eaSSaravana Kannan * @ops: operations this clock supports
2910197b3eaSSaravana Kannan * @parent_names: array of string names for all possible parents
292fc0c209cSStephen Boyd * @parent_data: array of parent data for all possible parents (when some
293fc0c209cSStephen Boyd * parents are external to the clk controller)
294fc0c209cSStephen Boyd * @parent_hws: array of pointers to all possible parents (when all parents
295fc0c209cSStephen Boyd * are internal to the clk controller)
2960197b3eaSSaravana Kannan * @num_parents: number of possible parents
2970197b3eaSSaravana Kannan * @flags: framework-level hints and quirks
2980197b3eaSSaravana Kannan */
2990197b3eaSSaravana Kannan struct clk_init_data {
3000197b3eaSSaravana Kannan const char *name;
3010197b3eaSSaravana Kannan const struct clk_ops *ops;
302fc0c209cSStephen Boyd /* Only one of the following three should be assigned */
3032893c379SSascha Hauer const char * const *parent_names;
304fc0c209cSStephen Boyd const struct clk_parent_data *parent_data;
305fc0c209cSStephen Boyd const struct clk_hw **parent_hws;
3060197b3eaSSaravana Kannan u8 num_parents;
3070197b3eaSSaravana Kannan unsigned long flags;
3080197b3eaSSaravana Kannan };
3090197b3eaSSaravana Kannan
3100197b3eaSSaravana Kannan /**
3110197b3eaSSaravana Kannan * struct clk_hw - handle for traversing from a struct clk to its corresponding
3120197b3eaSSaravana Kannan * hardware-specific structure. struct clk_hw should be declared within struct
3130197b3eaSSaravana Kannan * clk_foo and then referenced by the struct clk instance that uses struct
3140197b3eaSSaravana Kannan * clk_foo's clk_ops
3150197b3eaSSaravana Kannan *
316035a61c3STomeu Vizoso * @core: pointer to the struct clk_core instance that points back to this
317035a61c3STomeu Vizoso * struct clk_hw instance
318035a61c3STomeu Vizoso *
319035a61c3STomeu Vizoso * @clk: pointer to the per-user struct clk instance that can be used to call
320035a61c3STomeu Vizoso * into the clk API
3210197b3eaSSaravana Kannan *
3220197b3eaSSaravana Kannan * @init: pointer to struct clk_init_data that contains the init data shared
3230214f33cSStephen Boyd * with the common clock framework. This pointer will be set to NULL once
3240214f33cSStephen Boyd * a clk_register() variant is called on this clk_hw pointer.
3250197b3eaSSaravana Kannan */
3260197b3eaSSaravana Kannan struct clk_hw {
327035a61c3STomeu Vizoso struct clk_core *core;
3280197b3eaSSaravana Kannan struct clk *clk;
329dc4cd941SMark Brown const struct clk_init_data *init;
3300197b3eaSSaravana Kannan };
3310197b3eaSSaravana Kannan
3329d9f78edSMike Turquette /*
3339d9f78edSMike Turquette * DOC: Basic clock implementations common to many platforms
3349d9f78edSMike Turquette *
3359d9f78edSMike Turquette * Each basic clock hardware type is comprised of a structure describing the
3369d9f78edSMike Turquette * clock hardware, implementations of the relevant callbacks in struct clk_ops,
3379d9f78edSMike Turquette * unique flags for that hardware type, a registration function and an
3389d9f78edSMike Turquette * alternative macro for static initialization
3399d9f78edSMike Turquette */
3409d9f78edSMike Turquette
3419d9f78edSMike Turquette /**
3429d9f78edSMike Turquette * struct clk_fixed_rate - fixed-rate clock
3439d9f78edSMike Turquette * @hw: handle between common and hardware-specific interfaces
3449d9f78edSMike Turquette * @fixed_rate: constant frequency of clock
34532205b75SStephen Boyd * @fixed_accuracy: constant accuracy of clock in ppb (parts per billion)
3462d34f09eSStephen Boyd * @flags: hardware specific flags
34758f0c4baSStephen Boyd *
34858f0c4baSStephen Boyd * Flags:
34958f0c4baSStephen Boyd * * CLK_FIXED_RATE_PARENT_ACCURACY - Use the accuracy of the parent clk
35058f0c4baSStephen Boyd * instead of what's set in @fixed_accuracy.
3519d9f78edSMike Turquette */
3529d9f78edSMike Turquette struct clk_fixed_rate {
3539d9f78edSMike Turquette struct clk_hw hw;
3549d9f78edSMike Turquette unsigned long fixed_rate;
3550903ea60SBoris BREZILLON unsigned long fixed_accuracy;
3562d34f09eSStephen Boyd unsigned long flags;
3579d9f78edSMike Turquette };
3589d9f78edSMike Turquette
35958f0c4baSStephen Boyd #define CLK_FIXED_RATE_PARENT_ACCURACY BIT(0)
3605fd9c05cSGeliang Tang
361bffad66eSShawn Guo extern const struct clk_ops clk_fixed_rate_ops;
3622d34f09eSStephen Boyd struct clk_hw *__clk_hw_register_fixed_rate(struct device *dev,
3632d34f09eSStephen Boyd struct device_node *np, const char *name,
3642d34f09eSStephen Boyd const char *parent_name, const struct clk_hw *parent_hw,
3652d34f09eSStephen Boyd const struct clk_parent_data *parent_data, unsigned long flags,
3662d34f09eSStephen Boyd unsigned long fixed_rate, unsigned long fixed_accuracy,
3671d7d2065SDmitry Baryshkov unsigned long clk_fixed_flags, bool devm);
3689d9f78edSMike Turquette struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
3699d9f78edSMike Turquette const char *parent_name, unsigned long flags,
3709d9f78edSMike Turquette unsigned long fixed_rate);
3712d34f09eSStephen Boyd /**
3722d34f09eSStephen Boyd * clk_hw_register_fixed_rate - register fixed-rate clock with the clock
3732d34f09eSStephen Boyd * framework
3742d34f09eSStephen Boyd * @dev: device that is registering this clock
3752d34f09eSStephen Boyd * @name: name of this clock
3762d34f09eSStephen Boyd * @parent_name: name of clock's parent
3772d34f09eSStephen Boyd * @flags: framework-specific flags
3782d34f09eSStephen Boyd * @fixed_rate: non-adjustable clock rate
3792d34f09eSStephen Boyd */
3802d34f09eSStephen Boyd #define clk_hw_register_fixed_rate(dev, name, parent_name, flags, fixed_rate) \
3812d34f09eSStephen Boyd __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), NULL, \
3821d7d2065SDmitry Baryshkov NULL, (flags), (fixed_rate), 0, 0, false)
3831d7d2065SDmitry Baryshkov
3841d7d2065SDmitry Baryshkov /**
3851d7d2065SDmitry Baryshkov * devm_clk_hw_register_fixed_rate - register fixed-rate clock with the clock
3861d7d2065SDmitry Baryshkov * framework
3871d7d2065SDmitry Baryshkov * @dev: device that is registering this clock
3881d7d2065SDmitry Baryshkov * @name: name of this clock
3891d7d2065SDmitry Baryshkov * @parent_name: name of clock's parent
3901d7d2065SDmitry Baryshkov * @flags: framework-specific flags
3911d7d2065SDmitry Baryshkov * @fixed_rate: non-adjustable clock rate
3921d7d2065SDmitry Baryshkov */
3931d7d2065SDmitry Baryshkov #define devm_clk_hw_register_fixed_rate(dev, name, parent_name, flags, fixed_rate) \
3941d7d2065SDmitry Baryshkov __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), NULL, \
3951d7d2065SDmitry Baryshkov NULL, (flags), (fixed_rate), 0, 0, true)
3962d34f09eSStephen Boyd /**
3972d34f09eSStephen Boyd * clk_hw_register_fixed_rate_parent_hw - register fixed-rate clock with
3982d34f09eSStephen Boyd * the clock framework
3992d34f09eSStephen Boyd * @dev: device that is registering this clock
4002d34f09eSStephen Boyd * @name: name of this clock
4012d34f09eSStephen Boyd * @parent_hw: pointer to parent clk
4022d34f09eSStephen Boyd * @flags: framework-specific flags
4032d34f09eSStephen Boyd * @fixed_rate: non-adjustable clock rate
4042d34f09eSStephen Boyd */
4052d34f09eSStephen Boyd #define clk_hw_register_fixed_rate_parent_hw(dev, name, parent_hw, flags, \
4062d34f09eSStephen Boyd fixed_rate) \
4072d34f09eSStephen Boyd __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw), \
4081d7d2065SDmitry Baryshkov NULL, (flags), (fixed_rate), 0, 0, false)
4092d34f09eSStephen Boyd /**
4102d34f09eSStephen Boyd * clk_hw_register_fixed_rate_parent_data - register fixed-rate clock with
4112d34f09eSStephen Boyd * the clock framework
4122d34f09eSStephen Boyd * @dev: device that is registering this clock
4132d34f09eSStephen Boyd * @name: name of this clock
4142d34f09eSStephen Boyd * @parent_data: parent clk data
4152d34f09eSStephen Boyd * @flags: framework-specific flags
4162d34f09eSStephen Boyd * @fixed_rate: non-adjustable clock rate
4172d34f09eSStephen Boyd */
418ebf51575SClaudiu Beznea #define clk_hw_register_fixed_rate_parent_data(dev, name, parent_data, flags, \
4192d34f09eSStephen Boyd fixed_rate) \
4202d34f09eSStephen Boyd __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \
4212d34f09eSStephen Boyd (parent_data), (flags), (fixed_rate), 0, \
4221d7d2065SDmitry Baryshkov 0, false)
4232d34f09eSStephen Boyd /**
4242d34f09eSStephen Boyd * clk_hw_register_fixed_rate_with_accuracy - register fixed-rate clock with
4252d34f09eSStephen Boyd * the clock framework
4262d34f09eSStephen Boyd * @dev: device that is registering this clock
4272d34f09eSStephen Boyd * @name: name of this clock
4282d34f09eSStephen Boyd * @parent_name: name of clock's parent
4292d34f09eSStephen Boyd * @flags: framework-specific flags
4302d34f09eSStephen Boyd * @fixed_rate: non-adjustable clock rate
4311f1bb96dSStephen Boyd * @fixed_accuracy: non-adjustable clock accuracy
4322d34f09eSStephen Boyd */
4332d34f09eSStephen Boyd #define clk_hw_register_fixed_rate_with_accuracy(dev, name, parent_name, \
4342d34f09eSStephen Boyd flags, fixed_rate, \
4352d34f09eSStephen Boyd fixed_accuracy) \
4362d34f09eSStephen Boyd __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), \
4372d34f09eSStephen Boyd NULL, NULL, (flags), (fixed_rate), \
4381d7d2065SDmitry Baryshkov (fixed_accuracy), 0, false)
4392d34f09eSStephen Boyd /**
4402d34f09eSStephen Boyd * clk_hw_register_fixed_rate_with_accuracy_parent_hw - register fixed-rate
4412d34f09eSStephen Boyd * clock with the clock framework
4422d34f09eSStephen Boyd * @dev: device that is registering this clock
4432d34f09eSStephen Boyd * @name: name of this clock
4442d34f09eSStephen Boyd * @parent_hw: pointer to parent clk
4452d34f09eSStephen Boyd * @flags: framework-specific flags
4462d34f09eSStephen Boyd * @fixed_rate: non-adjustable clock rate
4472d34f09eSStephen Boyd * @fixed_accuracy: non-adjustable clock accuracy
4482d34f09eSStephen Boyd */
4492d34f09eSStephen Boyd #define clk_hw_register_fixed_rate_with_accuracy_parent_hw(dev, name, \
4502d34f09eSStephen Boyd parent_hw, flags, fixed_rate, fixed_accuracy) \
451*f1da0b7aSThéo Lebrun __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw), \
452*f1da0b7aSThéo Lebrun NULL, (flags), (fixed_rate), \
4531d7d2065SDmitry Baryshkov (fixed_accuracy), 0, false)
4542d34f09eSStephen Boyd /**
4552d34f09eSStephen Boyd * clk_hw_register_fixed_rate_with_accuracy_parent_data - register fixed-rate
4562d34f09eSStephen Boyd * clock with the clock framework
4572d34f09eSStephen Boyd * @dev: device that is registering this clock
4582d34f09eSStephen Boyd * @name: name of this clock
459823ef44aSRandy Dunlap * @parent_data: name of clock's parent
4602d34f09eSStephen Boyd * @flags: framework-specific flags
4612d34f09eSStephen Boyd * @fixed_rate: non-adjustable clock rate
4622d34f09eSStephen Boyd * @fixed_accuracy: non-adjustable clock accuracy
4632d34f09eSStephen Boyd */
4642d34f09eSStephen Boyd #define clk_hw_register_fixed_rate_with_accuracy_parent_data(dev, name, \
4652d34f09eSStephen Boyd parent_data, flags, fixed_rate, fixed_accuracy) \
4662d34f09eSStephen Boyd __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \
4672d34f09eSStephen Boyd (parent_data), NULL, (flags), \
4681d7d2065SDmitry Baryshkov (fixed_rate), (fixed_accuracy), 0, false)
469f5290d8eSDmitry Baryshkov /**
470f5290d8eSDmitry Baryshkov * clk_hw_register_fixed_rate_parent_accuracy - register fixed-rate clock with
471f5290d8eSDmitry Baryshkov * the clock framework
472f5290d8eSDmitry Baryshkov * @dev: device that is registering this clock
473f5290d8eSDmitry Baryshkov * @name: name of this clock
474823ef44aSRandy Dunlap * @parent_data: name of clock's parent
475f5290d8eSDmitry Baryshkov * @flags: framework-specific flags
476f5290d8eSDmitry Baryshkov * @fixed_rate: non-adjustable clock rate
477f5290d8eSDmitry Baryshkov */
478f5290d8eSDmitry Baryshkov #define clk_hw_register_fixed_rate_parent_accuracy(dev, name, parent_data, \
479f5290d8eSDmitry Baryshkov flags, fixed_rate) \
480f5290d8eSDmitry Baryshkov __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \
481f5290d8eSDmitry Baryshkov (parent_data), (flags), (fixed_rate), 0, \
4821d7d2065SDmitry Baryshkov CLK_FIXED_RATE_PARENT_ACCURACY, false)
4832d34f09eSStephen Boyd
4840b225e41SMasahiro Yamada void clk_unregister_fixed_rate(struct clk *clk);
48552445637SMasahiro Yamada void clk_hw_unregister_fixed_rate(struct clk_hw *hw);
48626ef56beSStephen Boyd
487015ba402SGrant Likely void of_fixed_clk_setup(struct device_node *np);
488015ba402SGrant Likely
4899d9f78edSMike Turquette /**
4909d9f78edSMike Turquette * struct clk_gate - gating clock
4919d9f78edSMike Turquette *
4929d9f78edSMike Turquette * @hw: handle between common and hardware-specific interfaces
4939d9f78edSMike Turquette * @reg: register controlling gate
4949d9f78edSMike Turquette * @bit_idx: single bit controlling gate
4959d9f78edSMike Turquette * @flags: hardware-specific flags
4969d9f78edSMike Turquette * @lock: register lock
4979d9f78edSMike Turquette *
4989d9f78edSMike Turquette * Clock which can gate its output. Implements .enable & .disable
4999d9f78edSMike Turquette *
5009d9f78edSMike Turquette * Flags:
5011f73f31aSViresh Kumar * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
5029d9f78edSMike Turquette * enable the clock. Setting this flag does the opposite: setting the bit
5039d9f78edSMike Turquette * disable the clock and clearing it enables the clock
50404577994SHaojian Zhuang * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit
50504577994SHaojian Zhuang * of this register, and mask of gate bits are in higher 16-bit of this
50604577994SHaojian Zhuang * register. While setting the gate bits, higher 16-bit should also be
50704577994SHaojian Zhuang * updated to indicate changing gate bits.
508d1c8a501SJonas Gorski * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for
509d1c8a501SJonas Gorski * the gate register. Setting this flag makes the register accesses big
510d1c8a501SJonas Gorski * endian.
5119d9f78edSMike Turquette */
5129d9f78edSMike Turquette struct clk_gate {
5139d9f78edSMike Turquette struct clk_hw hw;
5149d9f78edSMike Turquette void __iomem *reg;
5159d9f78edSMike Turquette u8 bit_idx;
5169d9f78edSMike Turquette u8 flags;
5179d9f78edSMike Turquette spinlock_t *lock;
5189d9f78edSMike Turquette };
5199d9f78edSMike Turquette
5205fd9c05cSGeliang Tang #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
5215fd9c05cSGeliang Tang
5229d9f78edSMike Turquette #define CLK_GATE_SET_TO_DISABLE BIT(0)
52304577994SHaojian Zhuang #define CLK_GATE_HIWORD_MASK BIT(1)
524d1c8a501SJonas Gorski #define CLK_GATE_BIG_ENDIAN BIT(2)
5259d9f78edSMike Turquette
526bffad66eSShawn Guo extern const struct clk_ops clk_gate_ops;
527194efb6eSStephen Boyd struct clk_hw *__clk_hw_register_gate(struct device *dev,
528194efb6eSStephen Boyd struct device_node *np, const char *name,
529194efb6eSStephen Boyd const char *parent_name, const struct clk_hw *parent_hw,
530194efb6eSStephen Boyd const struct clk_parent_data *parent_data,
531194efb6eSStephen Boyd unsigned long flags,
532194efb6eSStephen Boyd void __iomem *reg, u8 bit_idx,
533194efb6eSStephen Boyd u8 clk_gate_flags, spinlock_t *lock);
534815f0e73SHoratiu Vultur struct clk_hw *__devm_clk_hw_register_gate(struct device *dev,
535815f0e73SHoratiu Vultur struct device_node *np, const char *name,
536815f0e73SHoratiu Vultur const char *parent_name, const struct clk_hw *parent_hw,
537815f0e73SHoratiu Vultur const struct clk_parent_data *parent_data,
538815f0e73SHoratiu Vultur unsigned long flags,
539815f0e73SHoratiu Vultur void __iomem *reg, u8 bit_idx,
540815f0e73SHoratiu Vultur u8 clk_gate_flags, spinlock_t *lock);
5419d9f78edSMike Turquette struct clk *clk_register_gate(struct device *dev, const char *name,
5429d9f78edSMike Turquette const char *parent_name, unsigned long flags,
5439d9f78edSMike Turquette void __iomem *reg, u8 bit_idx,
5449d9f78edSMike Turquette u8 clk_gate_flags, spinlock_t *lock);
545194efb6eSStephen Boyd /**
546194efb6eSStephen Boyd * clk_hw_register_gate - register a gate clock with the clock framework
547194efb6eSStephen Boyd * @dev: device that is registering this clock
548194efb6eSStephen Boyd * @name: name of this clock
549194efb6eSStephen Boyd * @parent_name: name of this clock's parent
550194efb6eSStephen Boyd * @flags: framework-specific flags for this clock
551194efb6eSStephen Boyd * @reg: register address to control gating of this clock
552194efb6eSStephen Boyd * @bit_idx: which bit in the register controls gating of this clock
553194efb6eSStephen Boyd * @clk_gate_flags: gate-specific flags for this clock
554194efb6eSStephen Boyd * @lock: shared register lock for this clock
555194efb6eSStephen Boyd */
556194efb6eSStephen Boyd #define clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx, \
557194efb6eSStephen Boyd clk_gate_flags, lock) \
558194efb6eSStephen Boyd __clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \
559194efb6eSStephen Boyd NULL, (flags), (reg), (bit_idx), \
560194efb6eSStephen Boyd (clk_gate_flags), (lock))
561194efb6eSStephen Boyd /**
562194efb6eSStephen Boyd * clk_hw_register_gate_parent_hw - register a gate clock with the clock
563194efb6eSStephen Boyd * framework
564194efb6eSStephen Boyd * @dev: device that is registering this clock
565194efb6eSStephen Boyd * @name: name of this clock
566194efb6eSStephen Boyd * @parent_hw: pointer to parent clk
567194efb6eSStephen Boyd * @flags: framework-specific flags for this clock
568194efb6eSStephen Boyd * @reg: register address to control gating of this clock
569194efb6eSStephen Boyd * @bit_idx: which bit in the register controls gating of this clock
570194efb6eSStephen Boyd * @clk_gate_flags: gate-specific flags for this clock
571194efb6eSStephen Boyd * @lock: shared register lock for this clock
572194efb6eSStephen Boyd */
5734e934301SStephen Boyd #define clk_hw_register_gate_parent_hw(dev, name, parent_hw, flags, reg, \
574194efb6eSStephen Boyd bit_idx, clk_gate_flags, lock) \
5754e934301SStephen Boyd __clk_hw_register_gate((dev), NULL, (name), NULL, (parent_hw), \
576194efb6eSStephen Boyd NULL, (flags), (reg), (bit_idx), \
577194efb6eSStephen Boyd (clk_gate_flags), (lock))
578194efb6eSStephen Boyd /**
579194efb6eSStephen Boyd * clk_hw_register_gate_parent_data - register a gate clock with the clock
580194efb6eSStephen Boyd * framework
581194efb6eSStephen Boyd * @dev: device that is registering this clock
582194efb6eSStephen Boyd * @name: name of this clock
583194efb6eSStephen Boyd * @parent_data: parent clk data
584194efb6eSStephen Boyd * @flags: framework-specific flags for this clock
585194efb6eSStephen Boyd * @reg: register address to control gating of this clock
586194efb6eSStephen Boyd * @bit_idx: which bit in the register controls gating of this clock
587194efb6eSStephen Boyd * @clk_gate_flags: gate-specific flags for this clock
588194efb6eSStephen Boyd * @lock: shared register lock for this clock
589194efb6eSStephen Boyd */
5904e934301SStephen Boyd #define clk_hw_register_gate_parent_data(dev, name, parent_data, flags, reg, \
591194efb6eSStephen Boyd bit_idx, clk_gate_flags, lock) \
5924e934301SStephen Boyd __clk_hw_register_gate((dev), NULL, (name), NULL, NULL, (parent_data), \
5934e934301SStephen Boyd (flags), (reg), (bit_idx), \
594194efb6eSStephen Boyd (clk_gate_flags), (lock))
595815f0e73SHoratiu Vultur /**
596815f0e73SHoratiu Vultur * devm_clk_hw_register_gate - register a gate clock with the clock framework
597815f0e73SHoratiu Vultur * @dev: device that is registering this clock
598815f0e73SHoratiu Vultur * @name: name of this clock
599815f0e73SHoratiu Vultur * @parent_name: name of this clock's parent
600815f0e73SHoratiu Vultur * @flags: framework-specific flags for this clock
601815f0e73SHoratiu Vultur * @reg: register address to control gating of this clock
602815f0e73SHoratiu Vultur * @bit_idx: which bit in the register controls gating of this clock
603815f0e73SHoratiu Vultur * @clk_gate_flags: gate-specific flags for this clock
604815f0e73SHoratiu Vultur * @lock: shared register lock for this clock
605815f0e73SHoratiu Vultur */
606815f0e73SHoratiu Vultur #define devm_clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx,\
607815f0e73SHoratiu Vultur clk_gate_flags, lock) \
608815f0e73SHoratiu Vultur __devm_clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \
609815f0e73SHoratiu Vultur NULL, (flags), (reg), (bit_idx), \
610815f0e73SHoratiu Vultur (clk_gate_flags), (lock))
611d54c1fd4SQin Jian /**
612d54c1fd4SQin Jian * devm_clk_hw_register_gate_parent_data - register a gate clock with the
613d54c1fd4SQin Jian * clock framework
614d54c1fd4SQin Jian * @dev: device that is registering this clock
615d54c1fd4SQin Jian * @name: name of this clock
616d54c1fd4SQin Jian * @parent_data: parent clk data
617d54c1fd4SQin Jian * @flags: framework-specific flags for this clock
618d54c1fd4SQin Jian * @reg: register address to control gating of this clock
619d54c1fd4SQin Jian * @bit_idx: which bit in the register controls gating of this clock
620d54c1fd4SQin Jian * @clk_gate_flags: gate-specific flags for this clock
621d54c1fd4SQin Jian * @lock: shared register lock for this clock
622d54c1fd4SQin Jian */
623d54c1fd4SQin Jian #define devm_clk_hw_register_gate_parent_data(dev, name, parent_data, flags, \
624d54c1fd4SQin Jian reg, bit_idx, clk_gate_flags, \
625d54c1fd4SQin Jian lock) \
626d54c1fd4SQin Jian __devm_clk_hw_register_gate((dev), NULL, (name), NULL, NULL, \
627d54c1fd4SQin Jian (parent_data), (flags), (reg), (bit_idx), \
628d54c1fd4SQin Jian (clk_gate_flags), (lock))
629d54c1fd4SQin Jian
6304e3c021fSKrzysztof Kozlowski void clk_unregister_gate(struct clk *clk);
631e270d8cbSStephen Boyd void clk_hw_unregister_gate(struct clk_hw *hw);
6320a9c869dSGabriel Fernandez int clk_gate_is_enabled(struct clk_hw *hw);
6339d9f78edSMike Turquette
634357c3f0aSRajendra Nayak struct clk_div_table {
635357c3f0aSRajendra Nayak unsigned int val;
636357c3f0aSRajendra Nayak unsigned int div;
637357c3f0aSRajendra Nayak };
638357c3f0aSRajendra Nayak
6399d9f78edSMike Turquette /**
6409d9f78edSMike Turquette * struct clk_divider - adjustable divider clock
6419d9f78edSMike Turquette *
6429d9f78edSMike Turquette * @hw: handle between common and hardware-specific interfaces
6439d9f78edSMike Turquette * @reg: register containing the divider
6449d9f78edSMike Turquette * @shift: shift to the divider bit field
6459d9f78edSMike Turquette * @width: width of the divider bit field
646357c3f0aSRajendra Nayak * @table: array of value/divider pairs, last entry should have div = 0
6479d9f78edSMike Turquette * @lock: register lock
6489d9f78edSMike Turquette *
6499d9f78edSMike Turquette * Clock with an adjustable divider affecting its output frequency. Implements
6509d9f78edSMike Turquette * .recalc_rate, .set_rate and .round_rate
6519d9f78edSMike Turquette *
652823ef44aSRandy Dunlap * @flags:
6539d9f78edSMike Turquette * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
6549d9f78edSMike Turquette * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is
6559d9f78edSMike Turquette * the raw value read from the register, with the value of zero considered
656056b2053SSoren Brinkmann * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set.
6579d9f78edSMike Turquette * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
6589d9f78edSMike Turquette * the hardware register
659056b2053SSoren Brinkmann * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have
660056b2053SSoren Brinkmann * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor.
661056b2053SSoren Brinkmann * Some hardware implementations gracefully handle this case and allow a
662056b2053SSoren Brinkmann * zero divisor by not modifying their input clock
663056b2053SSoren Brinkmann * (divide by one / bypass).
664d57dfe75SHaojian Zhuang * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit
665d57dfe75SHaojian Zhuang * of this register, and mask of divider bits are in higher 16-bit of this
666d57dfe75SHaojian Zhuang * register. While setting the divider bits, higher 16-bit should also be
667d57dfe75SHaojian Zhuang * updated to indicate changing divider bits.
668774b5143SMaxime COQUELIN * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded
669774b5143SMaxime COQUELIN * to the closest integer instead of the up one.
67079c6ab50SHeiko Stuebner * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should
67179c6ab50SHeiko Stuebner * not be changed by the clock framework.
672afe76c8fSJim Quinlan * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED
673afe76c8fSJim Quinlan * except when the value read from the register is zero, the divisor is
674afe76c8fSJim Quinlan * 2^width of the field.
675434d69faSJonas Gorski * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used
676434d69faSJonas Gorski * for the divider register. Setting this flag makes the register accesses
677434d69faSJonas Gorski * big endian.
6789d9f78edSMike Turquette */
6799d9f78edSMike Turquette struct clk_divider {
6809d9f78edSMike Turquette struct clk_hw hw;
6819d9f78edSMike Turquette void __iomem *reg;
6829d9f78edSMike Turquette u8 shift;
6839d9f78edSMike Turquette u8 width;
6849d9f78edSMike Turquette u8 flags;
685357c3f0aSRajendra Nayak const struct clk_div_table *table;
6869d9f78edSMike Turquette spinlock_t *lock;
6879d9f78edSMike Turquette };
6889d9f78edSMike Turquette
689e6d3cc7bSJerome Brunet #define clk_div_mask(width) ((1 << (width)) - 1)
6905fd9c05cSGeliang Tang #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
6915fd9c05cSGeliang Tang
6929d9f78edSMike Turquette #define CLK_DIVIDER_ONE_BASED BIT(0)
6939d9f78edSMike Turquette #define CLK_DIVIDER_POWER_OF_TWO BIT(1)
694056b2053SSoren Brinkmann #define CLK_DIVIDER_ALLOW_ZERO BIT(2)
695d57dfe75SHaojian Zhuang #define CLK_DIVIDER_HIWORD_MASK BIT(3)
696774b5143SMaxime COQUELIN #define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
69779c6ab50SHeiko Stuebner #define CLK_DIVIDER_READ_ONLY BIT(5)
698afe76c8fSJim Quinlan #define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
699434d69faSJonas Gorski #define CLK_DIVIDER_BIG_ENDIAN BIT(7)
7009d9f78edSMike Turquette
701bffad66eSShawn Guo extern const struct clk_ops clk_divider_ops;
70250359819SHeiko Stuebner extern const struct clk_ops clk_divider_ro_ops;
703bca9690bSStephen Boyd
704bca9690bSStephen Boyd unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate,
705bca9690bSStephen Boyd unsigned int val, const struct clk_div_table *table,
70612a26c29SJerome Brunet unsigned long flags, unsigned long width);
70722833a91SMaxime Ripard long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
70822833a91SMaxime Ripard unsigned long rate, unsigned long *prate,
70922833a91SMaxime Ripard const struct clk_div_table *table,
710bca9690bSStephen Boyd u8 width, unsigned long flags);
711b15ee490SJerome Brunet long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
712b15ee490SJerome Brunet unsigned long rate, unsigned long *prate,
713b15ee490SJerome Brunet const struct clk_div_table *table, u8 width,
714b15ee490SJerome Brunet unsigned long flags, unsigned int val);
715bbd7a6ccSMartin Blumenstingl int divider_determine_rate(struct clk_hw *hw, struct clk_rate_request *req,
716bbd7a6ccSMartin Blumenstingl const struct clk_div_table *table, u8 width,
717bbd7a6ccSMartin Blumenstingl unsigned long flags);
718bbd7a6ccSMartin Blumenstingl int divider_ro_determine_rate(struct clk_hw *hw, struct clk_rate_request *req,
719bbd7a6ccSMartin Blumenstingl const struct clk_div_table *table, u8 width,
720bbd7a6ccSMartin Blumenstingl unsigned long flags, unsigned int val);
721bca9690bSStephen Boyd int divider_get_val(unsigned long rate, unsigned long parent_rate,
722bca9690bSStephen Boyd const struct clk_div_table *table, u8 width,
723bca9690bSStephen Boyd unsigned long flags);
724bca9690bSStephen Boyd
725ff258817SStephen Boyd struct clk_hw *__clk_hw_register_divider(struct device *dev,
726ff258817SStephen Boyd struct device_node *np, const char *name,
727ff258817SStephen Boyd const char *parent_name, const struct clk_hw *parent_hw,
728ff258817SStephen Boyd const struct clk_parent_data *parent_data, unsigned long flags,
729ff258817SStephen Boyd void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags,
730ff258817SStephen Boyd const struct clk_div_table *table, spinlock_t *lock);
73126792699SMichael Walle struct clk_hw *__devm_clk_hw_register_divider(struct device *dev,
73226792699SMichael Walle struct device_node *np, const char *name,
73326792699SMichael Walle const char *parent_name, const struct clk_hw *parent_hw,
73426792699SMichael Walle const struct clk_parent_data *parent_data, unsigned long flags,
73526792699SMichael Walle void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags,
73626792699SMichael Walle const struct clk_div_table *table, spinlock_t *lock);
737357c3f0aSRajendra Nayak struct clk *clk_register_divider_table(struct device *dev, const char *name,
738357c3f0aSRajendra Nayak const char *parent_name, unsigned long flags,
739357c3f0aSRajendra Nayak void __iomem *reg, u8 shift, u8 width,
740357c3f0aSRajendra Nayak u8 clk_divider_flags, const struct clk_div_table *table,
741357c3f0aSRajendra Nayak spinlock_t *lock);
742ff258817SStephen Boyd /**
743ff258817SStephen Boyd * clk_register_divider - register a divider clock with the clock framework
744ff258817SStephen Boyd * @dev: device registering this clock
745ff258817SStephen Boyd * @name: name of this clock
746ff258817SStephen Boyd * @parent_name: name of clock's parent
747ff258817SStephen Boyd * @flags: framework-specific flags
748ff258817SStephen Boyd * @reg: register address to adjust divider
749ff258817SStephen Boyd * @shift: number of bits to shift the bitfield
750ff258817SStephen Boyd * @width: width of the bitfield
751ff258817SStephen Boyd * @clk_divider_flags: divider-specific flags for this clock
752ff258817SStephen Boyd * @lock: shared register lock for this clock
753ff258817SStephen Boyd */
754ff258817SStephen Boyd #define clk_register_divider(dev, name, parent_name, flags, reg, shift, width, \
755ff258817SStephen Boyd clk_divider_flags, lock) \
756ff258817SStephen Boyd clk_register_divider_table((dev), (name), (parent_name), (flags), \
757ff258817SStephen Boyd (reg), (shift), (width), \
758ff258817SStephen Boyd (clk_divider_flags), NULL, (lock))
759ff258817SStephen Boyd /**
760ff258817SStephen Boyd * clk_hw_register_divider - register a divider clock with the clock framework
761ff258817SStephen Boyd * @dev: device registering this clock
762ff258817SStephen Boyd * @name: name of this clock
763ff258817SStephen Boyd * @parent_name: name of clock's parent
764ff258817SStephen Boyd * @flags: framework-specific flags
765ff258817SStephen Boyd * @reg: register address to adjust divider
766ff258817SStephen Boyd * @shift: number of bits to shift the bitfield
767ff258817SStephen Boyd * @width: width of the bitfield
768ff258817SStephen Boyd * @clk_divider_flags: divider-specific flags for this clock
769ff258817SStephen Boyd * @lock: shared register lock for this clock
770ff258817SStephen Boyd */
771ff258817SStephen Boyd #define clk_hw_register_divider(dev, name, parent_name, flags, reg, shift, \
772ff258817SStephen Boyd width, clk_divider_flags, lock) \
773ff258817SStephen Boyd __clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \
774ff258817SStephen Boyd NULL, (flags), (reg), (shift), (width), \
775ff258817SStephen Boyd (clk_divider_flags), NULL, (lock))
776ff258817SStephen Boyd /**
777ff258817SStephen Boyd * clk_hw_register_divider_parent_hw - register a divider clock with the clock
778ff258817SStephen Boyd * framework
779ff258817SStephen Boyd * @dev: device registering this clock
780ff258817SStephen Boyd * @name: name of this clock
781ff258817SStephen Boyd * @parent_hw: pointer to parent clk
782ff258817SStephen Boyd * @flags: framework-specific flags
783ff258817SStephen Boyd * @reg: register address to adjust divider
784ff258817SStephen Boyd * @shift: number of bits to shift the bitfield
785ff258817SStephen Boyd * @width: width of the bitfield
786ff258817SStephen Boyd * @clk_divider_flags: divider-specific flags for this clock
787ff258817SStephen Boyd * @lock: shared register lock for this clock
788ff258817SStephen Boyd */
789ff258817SStephen Boyd #define clk_hw_register_divider_parent_hw(dev, name, parent_hw, flags, reg, \
790ff258817SStephen Boyd shift, width, clk_divider_flags, \
791ff258817SStephen Boyd lock) \
792ff258817SStephen Boyd __clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw), \
793ff258817SStephen Boyd NULL, (flags), (reg), (shift), (width), \
794ff258817SStephen Boyd (clk_divider_flags), NULL, (lock))
795ff258817SStephen Boyd /**
796ff258817SStephen Boyd * clk_hw_register_divider_parent_data - register a divider clock with the clock
797ff258817SStephen Boyd * framework
798ff258817SStephen Boyd * @dev: device registering this clock
799ff258817SStephen Boyd * @name: name of this clock
800ff258817SStephen Boyd * @parent_data: parent clk data
801ff258817SStephen Boyd * @flags: framework-specific flags
802ff258817SStephen Boyd * @reg: register address to adjust divider
803ff258817SStephen Boyd * @shift: number of bits to shift the bitfield
804ff258817SStephen Boyd * @width: width of the bitfield
805ff258817SStephen Boyd * @clk_divider_flags: divider-specific flags for this clock
806ff258817SStephen Boyd * @lock: shared register lock for this clock
807ff258817SStephen Boyd */
808ff258817SStephen Boyd #define clk_hw_register_divider_parent_data(dev, name, parent_data, flags, \
809ff258817SStephen Boyd reg, shift, width, \
810ff258817SStephen Boyd clk_divider_flags, lock) \
811ff258817SStephen Boyd __clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \
812ff258817SStephen Boyd (parent_data), (flags), (reg), (shift), \
813ff258817SStephen Boyd (width), (clk_divider_flags), NULL, (lock))
814ff258817SStephen Boyd /**
815ff258817SStephen Boyd * clk_hw_register_divider_table - register a table based divider clock with
816ff258817SStephen Boyd * the clock framework
817ff258817SStephen Boyd * @dev: device registering this clock
818ff258817SStephen Boyd * @name: name of this clock
819ff258817SStephen Boyd * @parent_name: name of clock's parent
820ff258817SStephen Boyd * @flags: framework-specific flags
821ff258817SStephen Boyd * @reg: register address to adjust divider
822ff258817SStephen Boyd * @shift: number of bits to shift the bitfield
823ff258817SStephen Boyd * @width: width of the bitfield
824ff258817SStephen Boyd * @clk_divider_flags: divider-specific flags for this clock
825ff258817SStephen Boyd * @table: array of divider/value pairs ending with a div set to 0
826ff258817SStephen Boyd * @lock: shared register lock for this clock
827ff258817SStephen Boyd */
828ff258817SStephen Boyd #define clk_hw_register_divider_table(dev, name, parent_name, flags, reg, \
829ff258817SStephen Boyd shift, width, clk_divider_flags, table, \
830ff258817SStephen Boyd lock) \
831ff258817SStephen Boyd __clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \
832ff258817SStephen Boyd NULL, (flags), (reg), (shift), (width), \
833ff258817SStephen Boyd (clk_divider_flags), (table), (lock))
834ff258817SStephen Boyd /**
835ff258817SStephen Boyd * clk_hw_register_divider_table_parent_hw - register a table based divider
836ff258817SStephen Boyd * clock with the clock framework
837ff258817SStephen Boyd * @dev: device registering this clock
838ff258817SStephen Boyd * @name: name of this clock
839ff258817SStephen Boyd * @parent_hw: pointer to parent clk
840ff258817SStephen Boyd * @flags: framework-specific flags
841ff258817SStephen Boyd * @reg: register address to adjust divider
842ff258817SStephen Boyd * @shift: number of bits to shift the bitfield
843ff258817SStephen Boyd * @width: width of the bitfield
844ff258817SStephen Boyd * @clk_divider_flags: divider-specific flags for this clock
845ff258817SStephen Boyd * @table: array of divider/value pairs ending with a div set to 0
846ff258817SStephen Boyd * @lock: shared register lock for this clock
847ff258817SStephen Boyd */
848ff258817SStephen Boyd #define clk_hw_register_divider_table_parent_hw(dev, name, parent_hw, flags, \
849ff258817SStephen Boyd reg, shift, width, \
850ff258817SStephen Boyd clk_divider_flags, table, \
851ff258817SStephen Boyd lock) \
852ff258817SStephen Boyd __clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw), \
853ff258817SStephen Boyd NULL, (flags), (reg), (shift), (width), \
854ff258817SStephen Boyd (clk_divider_flags), (table), (lock))
855ff258817SStephen Boyd /**
856ff258817SStephen Boyd * clk_hw_register_divider_table_parent_data - register a table based divider
857ff258817SStephen Boyd * clock with the clock framework
858ff258817SStephen Boyd * @dev: device registering this clock
859ff258817SStephen Boyd * @name: name of this clock
860ff258817SStephen Boyd * @parent_data: parent clk data
861ff258817SStephen Boyd * @flags: framework-specific flags
862ff258817SStephen Boyd * @reg: register address to adjust divider
863ff258817SStephen Boyd * @shift: number of bits to shift the bitfield
864ff258817SStephen Boyd * @width: width of the bitfield
865ff258817SStephen Boyd * @clk_divider_flags: divider-specific flags for this clock
866ff258817SStephen Boyd * @table: array of divider/value pairs ending with a div set to 0
867ff258817SStephen Boyd * @lock: shared register lock for this clock
868ff258817SStephen Boyd */
869ff258817SStephen Boyd #define clk_hw_register_divider_table_parent_data(dev, name, parent_data, \
870ff258817SStephen Boyd flags, reg, shift, width, \
871ff258817SStephen Boyd clk_divider_flags, table, \
872ff258817SStephen Boyd lock) \
873ff258817SStephen Boyd __clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \
874ff258817SStephen Boyd (parent_data), (flags), (reg), (shift), \
875ff258817SStephen Boyd (width), (clk_divider_flags), (table), \
876ff258817SStephen Boyd (lock))
87726792699SMichael Walle /**
878f4b43ac0SDmitry Baryshkov * devm_clk_hw_register_divider - register a divider clock with the clock framework
879f4b43ac0SDmitry Baryshkov * @dev: device registering this clock
880f4b43ac0SDmitry Baryshkov * @name: name of this clock
881f4b43ac0SDmitry Baryshkov * @parent_name: name of clock's parent
882f4b43ac0SDmitry Baryshkov * @flags: framework-specific flags
883f4b43ac0SDmitry Baryshkov * @reg: register address to adjust divider
884f4b43ac0SDmitry Baryshkov * @shift: number of bits to shift the bitfield
885f4b43ac0SDmitry Baryshkov * @width: width of the bitfield
886f4b43ac0SDmitry Baryshkov * @clk_divider_flags: divider-specific flags for this clock
887f4b43ac0SDmitry Baryshkov * @lock: shared register lock for this clock
888f4b43ac0SDmitry Baryshkov */
889f4b43ac0SDmitry Baryshkov #define devm_clk_hw_register_divider(dev, name, parent_name, flags, reg, shift, \
890f4b43ac0SDmitry Baryshkov width, clk_divider_flags, lock) \
891f4b43ac0SDmitry Baryshkov __devm_clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \
892f4b43ac0SDmitry Baryshkov NULL, (flags), (reg), (shift), (width), \
893f4b43ac0SDmitry Baryshkov (clk_divider_flags), NULL, (lock))
894f4b43ac0SDmitry Baryshkov /**
895909fcb19SMarijn Suijten * devm_clk_hw_register_divider_parent_hw - register a divider clock with the clock framework
896909fcb19SMarijn Suijten * @dev: device registering this clock
897909fcb19SMarijn Suijten * @name: name of this clock
898909fcb19SMarijn Suijten * @parent_hw: pointer to parent clk
899909fcb19SMarijn Suijten * @flags: framework-specific flags
900909fcb19SMarijn Suijten * @reg: register address to adjust divider
901909fcb19SMarijn Suijten * @shift: number of bits to shift the bitfield
902909fcb19SMarijn Suijten * @width: width of the bitfield
903909fcb19SMarijn Suijten * @clk_divider_flags: divider-specific flags for this clock
904909fcb19SMarijn Suijten * @lock: shared register lock for this clock
905909fcb19SMarijn Suijten */
906909fcb19SMarijn Suijten #define devm_clk_hw_register_divider_parent_hw(dev, name, parent_hw, flags, \
907909fcb19SMarijn Suijten reg, shift, width, \
908909fcb19SMarijn Suijten clk_divider_flags, lock) \
909909fcb19SMarijn Suijten __devm_clk_hw_register_divider((dev), NULL, (name), NULL, \
910909fcb19SMarijn Suijten (parent_hw), NULL, (flags), (reg), \
911909fcb19SMarijn Suijten (shift), (width), (clk_divider_flags), \
912909fcb19SMarijn Suijten NULL, (lock))
913909fcb19SMarijn Suijten /**
91426792699SMichael Walle * devm_clk_hw_register_divider_table - register a table based divider clock
91526792699SMichael Walle * with the clock framework (devres variant)
91626792699SMichael Walle * @dev: device registering this clock
91726792699SMichael Walle * @name: name of this clock
91826792699SMichael Walle * @parent_name: name of clock's parent
91926792699SMichael Walle * @flags: framework-specific flags
92026792699SMichael Walle * @reg: register address to adjust divider
92126792699SMichael Walle * @shift: number of bits to shift the bitfield
92226792699SMichael Walle * @width: width of the bitfield
92326792699SMichael Walle * @clk_divider_flags: divider-specific flags for this clock
92426792699SMichael Walle * @table: array of divider/value pairs ending with a div set to 0
92526792699SMichael Walle * @lock: shared register lock for this clock
92626792699SMichael Walle */
92726792699SMichael Walle #define devm_clk_hw_register_divider_table(dev, name, parent_name, flags, \
92826792699SMichael Walle reg, shift, width, \
92926792699SMichael Walle clk_divider_flags, table, lock) \
93026792699SMichael Walle __devm_clk_hw_register_divider((dev), NULL, (name), (parent_name), \
93126792699SMichael Walle NULL, NULL, (flags), (reg), (shift), \
93226792699SMichael Walle (width), (clk_divider_flags), (table), \
93326792699SMichael Walle (lock))
934ff258817SStephen Boyd
9354e3c021fSKrzysztof Kozlowski void clk_unregister_divider(struct clk *clk);
936eb7d264fSStephen Boyd void clk_hw_unregister_divider(struct clk_hw *hw);
9379d9f78edSMike Turquette
9389d9f78edSMike Turquette /**
9399d9f78edSMike Turquette * struct clk_mux - multiplexer clock
9409d9f78edSMike Turquette *
9419d9f78edSMike Turquette * @hw: handle between common and hardware-specific interfaces
9429d9f78edSMike Turquette * @reg: register controlling multiplexer
943fe3f338fSJerome Brunet * @table: array of register values corresponding to the parent index
9449d9f78edSMike Turquette * @shift: shift to multiplexer bit field
945fe3f338fSJerome Brunet * @mask: mask of mutliplexer bit field
9463566d40cSJames Hogan * @flags: hardware-specific flags
9479d9f78edSMike Turquette * @lock: register lock
9489d9f78edSMike Turquette *
9499d9f78edSMike Turquette * Clock with multiple selectable parents. Implements .get_parent, .set_parent
9509d9f78edSMike Turquette * and .recalc_rate
9519d9f78edSMike Turquette *
9529d9f78edSMike Turquette * Flags:
9539d9f78edSMike Turquette * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
9541f73f31aSViresh Kumar * CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
955ba492e90SHaojian Zhuang * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this
956ba492e90SHaojian Zhuang * register, and mask of mux bits are in higher 16-bit of this register.
957ba492e90SHaojian Zhuang * While setting the mux bits, higher 16-bit should also be updated to
958ba492e90SHaojian Zhuang * indicate changing mux bits.
95931f6e870SStephen Boyd * CLK_MUX_READ_ONLY - The mux registers can't be written, only read in the
96031f6e870SStephen Boyd * .get_parent clk_op.
96115a02c1fSStephen Boyd * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired
96215a02c1fSStephen Boyd * frequency.
9633a727519SJonas Gorski * CLK_MUX_BIG_ENDIAN - By default little endian register accesses are used for
9643a727519SJonas Gorski * the mux register. Setting this flag makes the register accesses big
9653a727519SJonas Gorski * endian.
9669d9f78edSMike Turquette */
9679d9f78edSMike Turquette struct clk_mux {
9689d9f78edSMike Turquette struct clk_hw hw;
9699d9f78edSMike Turquette void __iomem *reg;
970891b7023SJonathan Neuschäfer const u32 *table;
971ce4f3313SPeter De Schrijver u32 mask;
9729d9f78edSMike Turquette u8 shift;
9739d9f78edSMike Turquette u8 flags;
9749d9f78edSMike Turquette spinlock_t *lock;
9759d9f78edSMike Turquette };
9769d9f78edSMike Turquette
9775fd9c05cSGeliang Tang #define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
9785fd9c05cSGeliang Tang
9799d9f78edSMike Turquette #define CLK_MUX_INDEX_ONE BIT(0)
9809d9f78edSMike Turquette #define CLK_MUX_INDEX_BIT BIT(1)
981ba492e90SHaojian Zhuang #define CLK_MUX_HIWORD_MASK BIT(2)
98215a02c1fSStephen Boyd #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */
98315a02c1fSStephen Boyd #define CLK_MUX_ROUND_CLOSEST BIT(4)
9843a727519SJonas Gorski #define CLK_MUX_BIG_ENDIAN BIT(5)
9859d9f78edSMike Turquette
986bffad66eSShawn Guo extern const struct clk_ops clk_mux_ops;
987c57acd14STomasz Figa extern const struct clk_ops clk_mux_ro_ops;
988ce4f3313SPeter De Schrijver
9899611b3aaSStephen Boyd struct clk_hw *__clk_hw_register_mux(struct device *dev, struct device_node *np,
9909611b3aaSStephen Boyd const char *name, u8 num_parents,
9919611b3aaSStephen Boyd const char * const *parent_names,
9929611b3aaSStephen Boyd const struct clk_hw **parent_hws,
9939611b3aaSStephen Boyd const struct clk_parent_data *parent_data,
9949611b3aaSStephen Boyd unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
995891b7023SJonathan Neuschäfer u8 clk_mux_flags, const u32 *table, spinlock_t *lock);
996b3084079SDmitry Baryshkov struct clk_hw *__devm_clk_hw_register_mux(struct device *dev, struct device_node *np,
997b3084079SDmitry Baryshkov const char *name, u8 num_parents,
998b3084079SDmitry Baryshkov const char * const *parent_names,
999b3084079SDmitry Baryshkov const struct clk_hw **parent_hws,
1000b3084079SDmitry Baryshkov const struct clk_parent_data *parent_data,
1001b3084079SDmitry Baryshkov unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
1002891b7023SJonathan Neuschäfer u8 clk_mux_flags, const u32 *table, spinlock_t *lock);
1003ce4f3313SPeter De Schrijver struct clk *clk_register_mux_table(struct device *dev, const char *name,
10042893c379SSascha Hauer const char * const *parent_names, u8 num_parents,
10059611b3aaSStephen Boyd unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
1006891b7023SJonathan Neuschäfer u8 clk_mux_flags, const u32 *table, spinlock_t *lock);
10079611b3aaSStephen Boyd
10089611b3aaSStephen Boyd #define clk_register_mux(dev, name, parent_names, num_parents, flags, reg, \
10099611b3aaSStephen Boyd shift, width, clk_mux_flags, lock) \
10109611b3aaSStephen Boyd clk_register_mux_table((dev), (name), (parent_names), (num_parents), \
10119611b3aaSStephen Boyd (flags), (reg), (shift), BIT((width)) - 1, \
10129611b3aaSStephen Boyd (clk_mux_flags), NULL, (lock))
10139611b3aaSStephen Boyd #define clk_hw_register_mux_table(dev, name, parent_names, num_parents, \
10149611b3aaSStephen Boyd flags, reg, shift, mask, clk_mux_flags, \
10159611b3aaSStephen Boyd table, lock) \
10169611b3aaSStephen Boyd __clk_hw_register_mux((dev), NULL, (name), (num_parents), \
10179611b3aaSStephen Boyd (parent_names), NULL, NULL, (flags), (reg), \
10189611b3aaSStephen Boyd (shift), (mask), (clk_mux_flags), (table), \
10199611b3aaSStephen Boyd (lock))
1020f5290d8eSDmitry Baryshkov #define clk_hw_register_mux_table_parent_data(dev, name, parent_data, \
1021f5290d8eSDmitry Baryshkov num_parents, flags, reg, shift, mask, \
1022f5290d8eSDmitry Baryshkov clk_mux_flags, table, lock) \
1023f5290d8eSDmitry Baryshkov __clk_hw_register_mux((dev), NULL, (name), (num_parents), \
1024f5290d8eSDmitry Baryshkov NULL, NULL, (parent_data), (flags), (reg), \
1025f5290d8eSDmitry Baryshkov (shift), (mask), (clk_mux_flags), (table), \
1026f5290d8eSDmitry Baryshkov (lock))
10279611b3aaSStephen Boyd #define clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \
10289611b3aaSStephen Boyd shift, width, clk_mux_flags, lock) \
10299611b3aaSStephen Boyd __clk_hw_register_mux((dev), NULL, (name), (num_parents), \
10309611b3aaSStephen Boyd (parent_names), NULL, NULL, (flags), (reg), \
10319611b3aaSStephen Boyd (shift), BIT((width)) - 1, (clk_mux_flags), \
10329611b3aaSStephen Boyd NULL, (lock))
10339611b3aaSStephen Boyd #define clk_hw_register_mux_hws(dev, name, parent_hws, num_parents, flags, \
10349611b3aaSStephen Boyd reg, shift, width, clk_mux_flags, lock) \
10359611b3aaSStephen Boyd __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \
10369611b3aaSStephen Boyd (parent_hws), NULL, (flags), (reg), (shift), \
10379611b3aaSStephen Boyd BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
10389611b3aaSStephen Boyd #define clk_hw_register_mux_parent_data(dev, name, parent_data, num_parents, \
10399611b3aaSStephen Boyd flags, reg, shift, width, \
10409611b3aaSStephen Boyd clk_mux_flags, lock) \
10419611b3aaSStephen Boyd __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, \
10429611b3aaSStephen Boyd (parent_data), (flags), (reg), (shift), \
10439611b3aaSStephen Boyd BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
1044d7915651SChristian Marangi #define clk_hw_register_mux_parent_data_table(dev, name, parent_data, \
1045d7915651SChristian Marangi num_parents, flags, reg, shift, \
1046d7915651SChristian Marangi width, clk_mux_flags, table, \
1047d7915651SChristian Marangi lock) \
1048d7915651SChristian Marangi __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, \
1049d7915651SChristian Marangi (parent_data), (flags), (reg), (shift), \
1050d7915651SChristian Marangi BIT((width)) - 1, (clk_mux_flags), table, (lock))
1051b3084079SDmitry Baryshkov #define devm_clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \
1052b3084079SDmitry Baryshkov shift, width, clk_mux_flags, lock) \
1053b3084079SDmitry Baryshkov __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), \
1054b3084079SDmitry Baryshkov (parent_names), NULL, NULL, (flags), (reg), \
1055b3084079SDmitry Baryshkov (shift), BIT((width)) - 1, (clk_mux_flags), \
1056b3084079SDmitry Baryshkov NULL, (lock))
1057df63af17SMarijn Suijten #define devm_clk_hw_register_mux_parent_hws(dev, name, parent_hws, \
1058df63af17SMarijn Suijten num_parents, flags, reg, shift, \
1059df63af17SMarijn Suijten width, clk_mux_flags, lock) \
1060df63af17SMarijn Suijten __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \
1061df63af17SMarijn Suijten (parent_hws), NULL, (flags), (reg), \
1062df63af17SMarijn Suijten (shift), BIT((width)) - 1, \
1063df63af17SMarijn Suijten (clk_mux_flags), NULL, (lock))
1064d7915651SChristian Marangi #define devm_clk_hw_register_mux_parent_data_table(dev, name, parent_data, \
1065d7915651SChristian Marangi num_parents, flags, reg, shift, \
1066d7915651SChristian Marangi width, clk_mux_flags, table, \
1067d7915651SChristian Marangi lock) \
1068d7915651SChristian Marangi __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \
1069d7915651SChristian Marangi NULL, (parent_data), (flags), (reg), (shift), \
1070d7915651SChristian Marangi BIT((width)) - 1, (clk_mux_flags), table, (lock))
1071ce4f3313SPeter De Schrijver
1072891b7023SJonathan Neuschäfer int clk_mux_val_to_index(struct clk_hw *hw, const u32 *table, unsigned int flags,
107377deb66dSJerome Brunet unsigned int val);
1074891b7023SJonathan Neuschäfer unsigned int clk_mux_index_to_val(const u32 *table, unsigned int flags, u8 index);
107577deb66dSJerome Brunet
10764e3c021fSKrzysztof Kozlowski void clk_unregister_mux(struct clk *clk);
1077264b3171SStephen Boyd void clk_hw_unregister_mux(struct clk_hw *hw);
10784e3c021fSKrzysztof Kozlowski
107979b16641SGregory CLEMENT void of_fixed_factor_clk_setup(struct device_node *node);
108079b16641SGregory CLEMENT
1081b2476490SMike Turquette /**
1082f0948f59SSascha Hauer * struct clk_fixed_factor - fixed multiplier and divider clock
1083f0948f59SSascha Hauer *
1084f0948f59SSascha Hauer * @hw: handle between common and hardware-specific interfaces
1085f0948f59SSascha Hauer * @mult: multiplier
1086f0948f59SSascha Hauer * @div: divider
1087f0948f59SSascha Hauer *
1088f0948f59SSascha Hauer * Clock with a fixed multiplier and divider. The output frequency is the
1089f0948f59SSascha Hauer * parent clock rate divided by div and multiplied by mult.
1090f0948f59SSascha Hauer * Implements .recalc_rate, .set_rate and .round_rate
1091f0948f59SSascha Hauer */
1092f0948f59SSascha Hauer
1093f0948f59SSascha Hauer struct clk_fixed_factor {
1094f0948f59SSascha Hauer struct clk_hw hw;
1095f0948f59SSascha Hauer unsigned int mult;
1096f0948f59SSascha Hauer unsigned int div;
1097f0948f59SSascha Hauer };
1098f0948f59SSascha Hauer
10995fd9c05cSGeliang Tang #define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw)
11005fd9c05cSGeliang Tang
11013037e9eaSDaniel Thompson extern const struct clk_ops clk_fixed_factor_ops;
1102f0948f59SSascha Hauer struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
1103f0948f59SSascha Hauer const char *parent_name, unsigned long flags,
1104f0948f59SSascha Hauer unsigned int mult, unsigned int div);
1105cbf9591fSMasahiro Yamada void clk_unregister_fixed_factor(struct clk *clk);
11060759ac8aSStephen Boyd struct clk_hw *clk_hw_register_fixed_factor(struct device *dev,
11070759ac8aSStephen Boyd const char *name, const char *parent_name, unsigned long flags,
11080759ac8aSStephen Boyd unsigned int mult, unsigned int div);
11090759ac8aSStephen Boyd void clk_hw_unregister_fixed_factor(struct clk_hw *hw);
11100b9266d2SDaniel Palmer struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev,
11110b9266d2SDaniel Palmer const char *name, const char *parent_name, unsigned long flags,
11120b9266d2SDaniel Palmer unsigned int mult, unsigned int div);
11130c125f87SMarek Vasut struct clk_hw *devm_clk_hw_register_fixed_factor_index(struct device *dev,
11140c125f87SMarek Vasut const char *name, unsigned int index, unsigned long flags,
11150c125f87SMarek Vasut unsigned int mult, unsigned int div);
11166ebd5247SMarijn Suijten
11176ebd5247SMarijn Suijten struct clk_hw *devm_clk_hw_register_fixed_factor_parent_hw(struct device *dev,
11186ebd5247SMarijn Suijten const char *name, const struct clk_hw *parent_hw,
11196ebd5247SMarijn Suijten unsigned long flags, unsigned int mult, unsigned int div);
11206ebd5247SMarijn Suijten
11216ebd5247SMarijn Suijten struct clk_hw *clk_hw_register_fixed_factor_parent_hw(struct device *dev,
11226ebd5247SMarijn Suijten const char *name, const struct clk_hw *parent_hw,
11236ebd5247SMarijn Suijten unsigned long flags, unsigned int mult, unsigned int div);
1124e2d0e90fSHeikki Krogerus /**
1125e2d0e90fSHeikki Krogerus * struct clk_fractional_divider - adjustable fractional divider clock
1126e2d0e90fSHeikki Krogerus *
1127e2d0e90fSHeikki Krogerus * @hw: handle between common and hardware-specific interfaces
1128e2d0e90fSHeikki Krogerus * @reg: register containing the divider
1129e2d0e90fSHeikki Krogerus * @mshift: shift to the numerator bit field
1130e2d0e90fSHeikki Krogerus * @mwidth: width of the numerator bit field
1131e2d0e90fSHeikki Krogerus * @nshift: shift to the denominator bit field
1132e2d0e90fSHeikki Krogerus * @nwidth: width of the denominator bit field
1133823ef44aSRandy Dunlap * @approximation: clk driver's callback for calculating the divider clock
1134e2d0e90fSHeikki Krogerus * @lock: register lock
1135e2d0e90fSHeikki Krogerus *
1136e2d0e90fSHeikki Krogerus * Clock with adjustable fractional divider affecting its output frequency.
1137e983da27SA.s. Dong *
1138823ef44aSRandy Dunlap * @flags:
1139e983da27SA.s. Dong * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator
1140e983da27SA.s. Dong * is the value read from the register. If CLK_FRAC_DIVIDER_ZERO_BASED
1141e983da27SA.s. Dong * is set then the numerator and denominator are both the value read
1142e983da27SA.s. Dong * plus one.
114358a2b4c9SJonas Gorski * CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are
114458a2b4c9SJonas Gorski * used for the divider register. Setting this flag makes the register
114558a2b4c9SJonas Gorski * accesses big endian.
114682f53f9eSAndy Shevchenko * CLK_FRAC_DIVIDER_POWER_OF_TWO_PS - By default the resulting fraction might
114782f53f9eSAndy Shevchenko * be saturated and the caller will get quite far from the good enough
114882f53f9eSAndy Shevchenko * approximation. Instead the caller may require, by setting this flag,
114982f53f9eSAndy Shevchenko * to shift left by a few bits in case, when the asked one is quite small
115082f53f9eSAndy Shevchenko * to satisfy the desired range of denominator. It assumes that on the
115182f53f9eSAndy Shevchenko * caller's side the power-of-two capable prescaler exists.
1152e2d0e90fSHeikki Krogerus */
1153e2d0e90fSHeikki Krogerus struct clk_fractional_divider {
1154e2d0e90fSHeikki Krogerus struct clk_hw hw;
1155e2d0e90fSHeikki Krogerus void __iomem *reg;
1156e2d0e90fSHeikki Krogerus u8 mshift;
1157934e2536SAndy Shevchenko u8 mwidth;
1158e2d0e90fSHeikki Krogerus u8 nshift;
1159934e2536SAndy Shevchenko u8 nwidth;
1160e2d0e90fSHeikki Krogerus u8 flags;
1161ec52e462SElaine Zhang void (*approximation)(struct clk_hw *hw,
1162ec52e462SElaine Zhang unsigned long rate, unsigned long *parent_rate,
1163ec52e462SElaine Zhang unsigned long *m, unsigned long *n);
1164e2d0e90fSHeikki Krogerus spinlock_t *lock;
1165e2d0e90fSHeikki Krogerus };
1166e2d0e90fSHeikki Krogerus
11675fd9c05cSGeliang Tang #define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw)
11685fd9c05cSGeliang Tang
1169e983da27SA.s. Dong #define CLK_FRAC_DIVIDER_ZERO_BASED BIT(0)
117058a2b4c9SJonas Gorski #define CLK_FRAC_DIVIDER_BIG_ENDIAN BIT(1)
117182f53f9eSAndy Shevchenko #define CLK_FRAC_DIVIDER_POWER_OF_TWO_PS BIT(2)
1172e983da27SA.s. Dong
1173e2d0e90fSHeikki Krogerus struct clk *clk_register_fractional_divider(struct device *dev,
1174e2d0e90fSHeikki Krogerus const char *name, const char *parent_name, unsigned long flags,
1175e2d0e90fSHeikki Krogerus void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
1176e2d0e90fSHeikki Krogerus u8 clk_divider_flags, spinlock_t *lock);
117739b44cffSStephen Boyd struct clk_hw *clk_hw_register_fractional_divider(struct device *dev,
117839b44cffSStephen Boyd const char *name, const char *parent_name, unsigned long flags,
117939b44cffSStephen Boyd void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
118039b44cffSStephen Boyd u8 clk_divider_flags, spinlock_t *lock);
118139b44cffSStephen Boyd void clk_hw_unregister_fractional_divider(struct clk_hw *hw);
1182e2d0e90fSHeikki Krogerus
1183f2e0a532SMaxime Ripard /**
1184f2e0a532SMaxime Ripard * struct clk_multiplier - adjustable multiplier clock
1185f2e0a532SMaxime Ripard *
1186f2e0a532SMaxime Ripard * @hw: handle between common and hardware-specific interfaces
1187f2e0a532SMaxime Ripard * @reg: register containing the multiplier
1188f2e0a532SMaxime Ripard * @shift: shift to the multiplier bit field
1189f2e0a532SMaxime Ripard * @width: width of the multiplier bit field
1190f2e0a532SMaxime Ripard * @lock: register lock
1191f2e0a532SMaxime Ripard *
1192f2e0a532SMaxime Ripard * Clock with an adjustable multiplier affecting its output frequency.
1193f2e0a532SMaxime Ripard * Implements .recalc_rate, .set_rate and .round_rate
1194f2e0a532SMaxime Ripard *
1195823ef44aSRandy Dunlap * @flags:
1196f2e0a532SMaxime Ripard * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read
1197f2e0a532SMaxime Ripard * from the register, with 0 being a valid value effectively
1198f2e0a532SMaxime Ripard * zeroing the output clock rate. If CLK_MULTIPLIER_ZERO_BYPASS is
1199f2e0a532SMaxime Ripard * set, then a null multiplier will be considered as a bypass,
1200f2e0a532SMaxime Ripard * leaving the parent rate unmodified.
1201f2e0a532SMaxime Ripard * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be
1202f2e0a532SMaxime Ripard * rounded to the closest integer instead of the down one.
12039427b71aSJonas Gorski * CLK_MULTIPLIER_BIG_ENDIAN - By default little endian register accesses are
12049427b71aSJonas Gorski * used for the multiplier register. Setting this flag makes the register
12059427b71aSJonas Gorski * accesses big endian.
1206f2e0a532SMaxime Ripard */
1207f2e0a532SMaxime Ripard struct clk_multiplier {
1208f2e0a532SMaxime Ripard struct clk_hw hw;
1209f2e0a532SMaxime Ripard void __iomem *reg;
1210f2e0a532SMaxime Ripard u8 shift;
1211f2e0a532SMaxime Ripard u8 width;
1212f2e0a532SMaxime Ripard u8 flags;
1213f2e0a532SMaxime Ripard spinlock_t *lock;
1214f2e0a532SMaxime Ripard };
1215f2e0a532SMaxime Ripard
12165fd9c05cSGeliang Tang #define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw)
12175fd9c05cSGeliang Tang
1218f2e0a532SMaxime Ripard #define CLK_MULTIPLIER_ZERO_BYPASS BIT(0)
1219f2e0a532SMaxime Ripard #define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1)
12209427b71aSJonas Gorski #define CLK_MULTIPLIER_BIG_ENDIAN BIT(2)
1221f2e0a532SMaxime Ripard
1222f2e0a532SMaxime Ripard extern const struct clk_ops clk_multiplier_ops;
1223f2e0a532SMaxime Ripard
1224ece70094SPrashant Gaikwad /***
1225ece70094SPrashant Gaikwad * struct clk_composite - aggregate clock of mux, divider and gate clocks
1226ece70094SPrashant Gaikwad *
1227ece70094SPrashant Gaikwad * @hw: handle between common and hardware-specific interfaces
1228d3a1c7beSMike Turquette * @mux_hw: handle between composite and hardware-specific mux clock
1229d3a1c7beSMike Turquette * @rate_hw: handle between composite and hardware-specific rate clock
1230d3a1c7beSMike Turquette * @gate_hw: handle between composite and hardware-specific gate clock
1231ece70094SPrashant Gaikwad * @mux_ops: clock ops for mux
1232d3a1c7beSMike Turquette * @rate_ops: clock ops for rate
1233ece70094SPrashant Gaikwad * @gate_ops: clock ops for gate
1234ece70094SPrashant Gaikwad */
1235ece70094SPrashant Gaikwad struct clk_composite {
1236ece70094SPrashant Gaikwad struct clk_hw hw;
1237ece70094SPrashant Gaikwad struct clk_ops ops;
1238ece70094SPrashant Gaikwad
1239ece70094SPrashant Gaikwad struct clk_hw *mux_hw;
1240d3a1c7beSMike Turquette struct clk_hw *rate_hw;
1241ece70094SPrashant Gaikwad struct clk_hw *gate_hw;
1242ece70094SPrashant Gaikwad
1243ece70094SPrashant Gaikwad const struct clk_ops *mux_ops;
1244d3a1c7beSMike Turquette const struct clk_ops *rate_ops;
1245ece70094SPrashant Gaikwad const struct clk_ops *gate_ops;
1246ece70094SPrashant Gaikwad };
1247ece70094SPrashant Gaikwad
12485fd9c05cSGeliang Tang #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
12495fd9c05cSGeliang Tang
1250ece70094SPrashant Gaikwad struct clk *clk_register_composite(struct device *dev, const char *name,
12512893c379SSascha Hauer const char * const *parent_names, int num_parents,
1252ece70094SPrashant Gaikwad struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1253d3a1c7beSMike Turquette struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1254ece70094SPrashant Gaikwad struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1255ece70094SPrashant Gaikwad unsigned long flags);
125673ef6572SMichael Walle struct clk *clk_register_composite_pdata(struct device *dev, const char *name,
125773ef6572SMichael Walle const struct clk_parent_data *parent_data, int num_parents,
125873ef6572SMichael Walle struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
125973ef6572SMichael Walle struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
126073ef6572SMichael Walle struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
126173ef6572SMichael Walle unsigned long flags);
126292a39d90SMaxime Ripard void clk_unregister_composite(struct clk *clk);
126349cb392dSStephen Boyd struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name,
126449cb392dSStephen Boyd const char * const *parent_names, int num_parents,
126549cb392dSStephen Boyd struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
126649cb392dSStephen Boyd struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
126749cb392dSStephen Boyd struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
126849cb392dSStephen Boyd unsigned long flags);
126973ef6572SMichael Walle struct clk_hw *clk_hw_register_composite_pdata(struct device *dev,
127073ef6572SMichael Walle const char *name,
127173ef6572SMichael Walle const struct clk_parent_data *parent_data, int num_parents,
127273ef6572SMichael Walle struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
127373ef6572SMichael Walle struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
127473ef6572SMichael Walle struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
127573ef6572SMichael Walle unsigned long flags);
12760eba7707SMichael Walle struct clk_hw *devm_clk_hw_register_composite_pdata(struct device *dev,
12770eba7707SMichael Walle const char *name, const struct clk_parent_data *parent_data,
12780eba7707SMichael Walle int num_parents,
12790eba7707SMichael Walle struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
12800eba7707SMichael Walle struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
12810eba7707SMichael Walle struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
12820eba7707SMichael Walle unsigned long flags);
128349cb392dSStephen Boyd void clk_hw_unregister_composite(struct clk_hw *hw);
1284ece70094SPrashant Gaikwad
12850197b3eaSSaravana Kannan struct clk *clk_register(struct device *dev, struct clk_hw *hw);
128646c8773aSStephen Boyd struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw);
1287b2476490SMike Turquette
12884143804cSStephen Boyd int __must_check clk_hw_register(struct device *dev, struct clk_hw *hw);
12894143804cSStephen Boyd int __must_check devm_clk_hw_register(struct device *dev, struct clk_hw *hw);
129089a5ddccSStephen Boyd int __must_check of_clk_hw_register(struct device_node *node, struct clk_hw *hw);
12914143804cSStephen Boyd
12921df5c939SMark Brown void clk_unregister(struct clk *clk);
12931df5c939SMark Brown
12944143804cSStephen Boyd void clk_hw_unregister(struct clk_hw *hw);
12954143804cSStephen Boyd
1296b2476490SMike Turquette /* helper functions */
1297b76281cbSGeert Uytterhoeven const char *__clk_get_name(const struct clk *clk);
1298e7df6f6eSStephen Boyd const char *clk_hw_get_name(const struct clk_hw *hw);
12991df37992SStephen Rothwell #ifdef CONFIG_COMMON_CLK
1300b2476490SMike Turquette struct clk_hw *__clk_get_hw(struct clk *clk);
13011df37992SStephen Rothwell #else
__clk_get_hw(struct clk * clk)13021df37992SStephen Rothwell static inline struct clk_hw *__clk_get_hw(struct clk *clk)
13031df37992SStephen Rothwell {
13041df37992SStephen Rothwell return (struct clk_hw *)clk;
13051df37992SStephen Rothwell }
13061df37992SStephen Rothwell #endif
130730d6f8c1SJerome Brunet
130830d6f8c1SJerome Brunet struct clk *clk_hw_get_clk(struct clk_hw *hw, const char *con_id);
130930d6f8c1SJerome Brunet struct clk *devm_clk_hw_get_clk(struct device *dev, struct clk_hw *hw,
131030d6f8c1SJerome Brunet const char *con_id);
131130d6f8c1SJerome Brunet
1312e7df6f6eSStephen Boyd unsigned int clk_hw_get_num_parents(const struct clk_hw *hw);
1313e7df6f6eSStephen Boyd struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw);
1314e7df6f6eSStephen Boyd struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw,
13151a9c069cSStephen Boyd unsigned int index);
1316d9b86cc4SSowjanya Komatineni int clk_hw_get_parent_index(struct clk_hw *hw);
13173567894bSNeil Armstrong int clk_hw_set_parent(struct clk_hw *hw, struct clk_hw *new_parent);
131893874681SLinus Torvalds unsigned int __clk_get_enable_count(struct clk *clk);
1319e7df6f6eSStephen Boyd unsigned long clk_hw_get_rate(const struct clk_hw *hw);
1320e7df6f6eSStephen Boyd unsigned long clk_hw_get_flags(const struct clk_hw *hw);
1321d13501a2SKatsuhiro Suzuki #define clk_hw_can_set_rate_parent(hw) \
1322d13501a2SKatsuhiro Suzuki (clk_hw_get_flags((hw)) & CLK_SET_RATE_PARENT)
1323d13501a2SKatsuhiro Suzuki
1324e7df6f6eSStephen Boyd bool clk_hw_is_prepared(const struct clk_hw *hw);
1325e55a839aSJerome Brunet bool clk_hw_rate_is_protected(const struct clk_hw *hw);
1326be68bf88SJoachim Eastwood bool clk_hw_is_enabled(const struct clk_hw *hw);
13272ac6b1f5SStephen Boyd bool __clk_is_enabled(struct clk *clk);
1328b2476490SMike Turquette struct clk *__clk_lookup(const char *name);
13290817b62cSBoris Brezillon int __clk_mux_determine_rate(struct clk_hw *hw,
13300817b62cSBoris Brezillon struct clk_rate_request *req);
13310817b62cSBoris Brezillon int __clk_determine_rate(struct clk_hw *core, struct clk_rate_request *req);
13320817b62cSBoris Brezillon int __clk_mux_determine_rate_closest(struct clk_hw *hw,
13330817b62cSBoris Brezillon struct clk_rate_request *req);
13344ad69b80SJerome Brunet int clk_mux_determine_rate_flags(struct clk_hw *hw,
13354ad69b80SJerome Brunet struct clk_rate_request *req,
13364ad69b80SJerome Brunet unsigned long flags);
133733b70fbcSStephen Boyd int clk_hw_determine_rate_no_reparent(struct clk_hw *hw,
133833b70fbcSStephen Boyd struct clk_rate_request *req);
133942c86547STomeu Vizoso void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent);
134025399325SMaxime Ripard void clk_hw_get_rate_range(struct clk_hw *hw, unsigned long *min_rate,
134125399325SMaxime Ripard unsigned long *max_rate);
13429783c0d9SStephen Boyd void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate,
13439783c0d9SStephen Boyd unsigned long max_rate);
1344b2476490SMike Turquette
__clk_hw_set_clk(struct clk_hw * dst,struct clk_hw * src)13452e65d8bfSJavier Martinez Canillas static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src)
13462e65d8bfSJavier Martinez Canillas {
13472e65d8bfSJavier Martinez Canillas dst->clk = src->clk;
13482e65d8bfSJavier Martinez Canillas dst->core = src->core;
13492e65d8bfSJavier Martinez Canillas }
13502e65d8bfSJavier Martinez Canillas
divider_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate,const struct clk_div_table * table,u8 width,unsigned long flags)135122833a91SMaxime Ripard static inline long divider_round_rate(struct clk_hw *hw, unsigned long rate,
135222833a91SMaxime Ripard unsigned long *prate,
135322833a91SMaxime Ripard const struct clk_div_table *table,
135422833a91SMaxime Ripard u8 width, unsigned long flags)
135522833a91SMaxime Ripard {
135622833a91SMaxime Ripard return divider_round_rate_parent(hw, clk_hw_get_parent(hw),
135722833a91SMaxime Ripard rate, prate, table, width, flags);
135822833a91SMaxime Ripard }
135922833a91SMaxime Ripard
divider_ro_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate,const struct clk_div_table * table,u8 width,unsigned long flags,unsigned int val)1360b15ee490SJerome Brunet static inline long divider_ro_round_rate(struct clk_hw *hw, unsigned long rate,
1361b15ee490SJerome Brunet unsigned long *prate,
1362b15ee490SJerome Brunet const struct clk_div_table *table,
1363b15ee490SJerome Brunet u8 width, unsigned long flags,
1364b15ee490SJerome Brunet unsigned int val)
1365b15ee490SJerome Brunet {
1366b15ee490SJerome Brunet return divider_ro_round_rate_parent(hw, clk_hw_get_parent(hw),
1367b15ee490SJerome Brunet rate, prate, table, width, flags,
1368b15ee490SJerome Brunet val);
1369b15ee490SJerome Brunet }
1370b15ee490SJerome Brunet
1371b2476490SMike Turquette /*
1372b2476490SMike Turquette * FIXME clock api without lock protection
1373b2476490SMike Turquette */
13741a9c069cSStephen Boyd unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate);
1375b2476490SMike Turquette
13760b151debSSebastian Hesselbarth struct clk_onecell_data {
13770b151debSSebastian Hesselbarth struct clk **clks;
13780b151debSSebastian Hesselbarth unsigned int clk_num;
13790b151debSSebastian Hesselbarth };
13800b151debSSebastian Hesselbarth
13810861e5b8SStephen Boyd struct clk_hw_onecell_data {
13825963f19cSMasahiro Yamada unsigned int num;
1383f316cdffSKees Cook struct clk_hw *hws[] __counted_by(num);
13840861e5b8SStephen Boyd };
13850861e5b8SStephen Boyd
1386c28cd1f3SSaravana Kannan #define CLK_OF_DECLARE(name, compat, fn) \
13875cf9d015SNathan Chancellor static void __init __##name##_of_clk_init_declare(struct device_node *np) \
1388c28cd1f3SSaravana Kannan { \
1389c28cd1f3SSaravana Kannan fn(np); \
1390c28cd1f3SSaravana Kannan fwnode_dev_initialized(of_fwnode_handle(np), true); \
1391c28cd1f3SSaravana Kannan } \
13925cf9d015SNathan Chancellor OF_DECLARE_1(clk, name, compat, __##name##_of_clk_init_declare)
13930b151debSSebastian Hesselbarth
1394c7296c51SRicardo Ribalda Delgado /*
1395c7296c51SRicardo Ribalda Delgado * Use this macro when you have a driver that requires two initialization
1396c7296c51SRicardo Ribalda Delgado * routines, one at of_clk_init(), and one at platform device probe
1397c7296c51SRicardo Ribalda Delgado */
1398c7296c51SRicardo Ribalda Delgado #define CLK_OF_DECLARE_DRIVER(name, compat, fn) \
1399339e1e54SShawn Guo static void __init name##_of_clk_init_driver(struct device_node *np) \
1400c7296c51SRicardo Ribalda Delgado { \
1401c7296c51SRicardo Ribalda Delgado of_node_clear_flag(np, OF_POPULATED); \
1402c7296c51SRicardo Ribalda Delgado fn(np); \
1403c7296c51SRicardo Ribalda Delgado } \
1404c7296c51SRicardo Ribalda Delgado OF_DECLARE_1(clk, name, compat, name##_of_clk_init_driver)
1405c7296c51SRicardo Ribalda Delgado
14061ded879eSChunyan Zhang #define CLK_HW_INIT(_name, _parent, _ops, _flags) \
14071ded879eSChunyan Zhang (&(struct clk_init_data) { \
14081ded879eSChunyan Zhang .flags = _flags, \
14091ded879eSChunyan Zhang .name = _name, \
14101ded879eSChunyan Zhang .parent_names = (const char *[]) { _parent }, \
14111ded879eSChunyan Zhang .num_parents = 1, \
14121ded879eSChunyan Zhang .ops = _ops, \
14131ded879eSChunyan Zhang })
14141ded879eSChunyan Zhang
141599600fd4SChen-Yu Tsai #define CLK_HW_INIT_HW(_name, _parent, _ops, _flags) \
141699600fd4SChen-Yu Tsai (&(struct clk_init_data) { \
141799600fd4SChen-Yu Tsai .flags = _flags, \
141899600fd4SChen-Yu Tsai .name = _name, \
141999600fd4SChen-Yu Tsai .parent_hws = (const struct clk_hw*[]) { _parent }, \
142099600fd4SChen-Yu Tsai .num_parents = 1, \
142199600fd4SChen-Yu Tsai .ops = _ops, \
142299600fd4SChen-Yu Tsai })
142399600fd4SChen-Yu Tsai
142499600fd4SChen-Yu Tsai /*
142599600fd4SChen-Yu Tsai * This macro is intended for drivers to be able to share the otherwise
142699600fd4SChen-Yu Tsai * individual struct clk_hw[] compound literals created by the compiler
142799600fd4SChen-Yu Tsai * when using CLK_HW_INIT_HW. It does NOT support multiple parents.
142899600fd4SChen-Yu Tsai */
142999600fd4SChen-Yu Tsai #define CLK_HW_INIT_HWS(_name, _parent, _ops, _flags) \
143099600fd4SChen-Yu Tsai (&(struct clk_init_data) { \
143199600fd4SChen-Yu Tsai .flags = _flags, \
143299600fd4SChen-Yu Tsai .name = _name, \
143399600fd4SChen-Yu Tsai .parent_hws = _parent, \
143499600fd4SChen-Yu Tsai .num_parents = 1, \
143599600fd4SChen-Yu Tsai .ops = _ops, \
143699600fd4SChen-Yu Tsai })
143799600fd4SChen-Yu Tsai
14382d6b4f33SChen-Yu Tsai #define CLK_HW_INIT_FW_NAME(_name, _parent, _ops, _flags) \
14392d6b4f33SChen-Yu Tsai (&(struct clk_init_data) { \
14402d6b4f33SChen-Yu Tsai .flags = _flags, \
14412d6b4f33SChen-Yu Tsai .name = _name, \
14422d6b4f33SChen-Yu Tsai .parent_data = (const struct clk_parent_data[]) { \
14432d6b4f33SChen-Yu Tsai { .fw_name = _parent }, \
14442d6b4f33SChen-Yu Tsai }, \
14452d6b4f33SChen-Yu Tsai .num_parents = 1, \
14462d6b4f33SChen-Yu Tsai .ops = _ops, \
14472d6b4f33SChen-Yu Tsai })
14482d6b4f33SChen-Yu Tsai
14491ded879eSChunyan Zhang #define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \
14501ded879eSChunyan Zhang (&(struct clk_init_data) { \
14511ded879eSChunyan Zhang .flags = _flags, \
14521ded879eSChunyan Zhang .name = _name, \
14531ded879eSChunyan Zhang .parent_names = _parents, \
14541ded879eSChunyan Zhang .num_parents = ARRAY_SIZE(_parents), \
14551ded879eSChunyan Zhang .ops = _ops, \
14561ded879eSChunyan Zhang })
14571ded879eSChunyan Zhang
145899600fd4SChen-Yu Tsai #define CLK_HW_INIT_PARENTS_HW(_name, _parents, _ops, _flags) \
145999600fd4SChen-Yu Tsai (&(struct clk_init_data) { \
146099600fd4SChen-Yu Tsai .flags = _flags, \
146199600fd4SChen-Yu Tsai .name = _name, \
146299600fd4SChen-Yu Tsai .parent_hws = _parents, \
146399600fd4SChen-Yu Tsai .num_parents = ARRAY_SIZE(_parents), \
146499600fd4SChen-Yu Tsai .ops = _ops, \
146599600fd4SChen-Yu Tsai })
146699600fd4SChen-Yu Tsai
146713933109SChen-Yu Tsai #define CLK_HW_INIT_PARENTS_DATA(_name, _parents, _ops, _flags) \
146813933109SChen-Yu Tsai (&(struct clk_init_data) { \
146913933109SChen-Yu Tsai .flags = _flags, \
147013933109SChen-Yu Tsai .name = _name, \
147113933109SChen-Yu Tsai .parent_data = _parents, \
147213933109SChen-Yu Tsai .num_parents = ARRAY_SIZE(_parents), \
147313933109SChen-Yu Tsai .ops = _ops, \
147413933109SChen-Yu Tsai })
147513933109SChen-Yu Tsai
14761ded879eSChunyan Zhang #define CLK_HW_INIT_NO_PARENT(_name, _ops, _flags) \
14771ded879eSChunyan Zhang (&(struct clk_init_data) { \
14781ded879eSChunyan Zhang .flags = _flags, \
14791ded879eSChunyan Zhang .name = _name, \
14801ded879eSChunyan Zhang .parent_names = NULL, \
14811ded879eSChunyan Zhang .num_parents = 0, \
14821ded879eSChunyan Zhang .ops = _ops, \
14831ded879eSChunyan Zhang })
14841ded879eSChunyan Zhang
14851ded879eSChunyan Zhang #define CLK_FIXED_FACTOR(_struct, _name, _parent, \
14861ded879eSChunyan Zhang _div, _mult, _flags) \
14871ded879eSChunyan Zhang struct clk_fixed_factor _struct = { \
14881ded879eSChunyan Zhang .div = _div, \
14891ded879eSChunyan Zhang .mult = _mult, \
14901ded879eSChunyan Zhang .hw.init = CLK_HW_INIT(_name, \
14911ded879eSChunyan Zhang _parent, \
14921ded879eSChunyan Zhang &clk_fixed_factor_ops, \
14931ded879eSChunyan Zhang _flags), \
14941ded879eSChunyan Zhang }
14951ded879eSChunyan Zhang
1496d7b15114SChen-Yu Tsai #define CLK_FIXED_FACTOR_HW(_struct, _name, _parent, \
1497d7b15114SChen-Yu Tsai _div, _mult, _flags) \
1498d7b15114SChen-Yu Tsai struct clk_fixed_factor _struct = { \
1499d7b15114SChen-Yu Tsai .div = _div, \
1500d7b15114SChen-Yu Tsai .mult = _mult, \
1501d7b15114SChen-Yu Tsai .hw.init = CLK_HW_INIT_HW(_name, \
1502d7b15114SChen-Yu Tsai _parent, \
1503d7b15114SChen-Yu Tsai &clk_fixed_factor_ops, \
1504d7b15114SChen-Yu Tsai _flags), \
1505d7b15114SChen-Yu Tsai }
1506d7b15114SChen-Yu Tsai
15071bef004eSChen-Yu Tsai /*
15081bef004eSChen-Yu Tsai * This macro allows the driver to reuse the _parent array for multiple
15091bef004eSChen-Yu Tsai * fixed factor clk declarations.
15101bef004eSChen-Yu Tsai */
15111bef004eSChen-Yu Tsai #define CLK_FIXED_FACTOR_HWS(_struct, _name, _parent, \
15121bef004eSChen-Yu Tsai _div, _mult, _flags) \
15131bef004eSChen-Yu Tsai struct clk_fixed_factor _struct = { \
15141bef004eSChen-Yu Tsai .div = _div, \
15151bef004eSChen-Yu Tsai .mult = _mult, \
15161bef004eSChen-Yu Tsai .hw.init = CLK_HW_INIT_HWS(_name, \
15171bef004eSChen-Yu Tsai _parent, \
15181bef004eSChen-Yu Tsai &clk_fixed_factor_ops, \
15191bef004eSChen-Yu Tsai _flags), \
15201bef004eSChen-Yu Tsai }
15211bef004eSChen-Yu Tsai
15228b13a48bSChen-Yu Tsai #define CLK_FIXED_FACTOR_FW_NAME(_struct, _name, _parent, \
15238b13a48bSChen-Yu Tsai _div, _mult, _flags) \
15248b13a48bSChen-Yu Tsai struct clk_fixed_factor _struct = { \
15258b13a48bSChen-Yu Tsai .div = _div, \
15268b13a48bSChen-Yu Tsai .mult = _mult, \
15278b13a48bSChen-Yu Tsai .hw.init = CLK_HW_INIT_FW_NAME(_name, \
15288b13a48bSChen-Yu Tsai _parent, \
15298b13a48bSChen-Yu Tsai &clk_fixed_factor_ops, \
15308b13a48bSChen-Yu Tsai _flags), \
15318b13a48bSChen-Yu Tsai }
15328b13a48bSChen-Yu Tsai
15330b151debSSebastian Hesselbarth #ifdef CONFIG_OF
1534766e6a4eSGrant Likely int of_clk_add_provider(struct device_node *np,
1535766e6a4eSGrant Likely struct clk *(*clk_src_get)(struct of_phandle_args *args,
1536766e6a4eSGrant Likely void *data),
1537766e6a4eSGrant Likely void *data);
15380861e5b8SStephen Boyd int of_clk_add_hw_provider(struct device_node *np,
15390861e5b8SStephen Boyd struct clk_hw *(*get)(struct of_phandle_args *clkspec,
15400861e5b8SStephen Boyd void *data),
15410861e5b8SStephen Boyd void *data);
1542aa795c41SStephen Boyd int devm_of_clk_add_hw_provider(struct device *dev,
1543aa795c41SStephen Boyd struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1544aa795c41SStephen Boyd void *data),
1545aa795c41SStephen Boyd void *data);
1546766e6a4eSGrant Likely void of_clk_del_provider(struct device_node *np);
15471c8934b4SAndy Shevchenko
1548766e6a4eSGrant Likely struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
1549766e6a4eSGrant Likely void *data);
15500861e5b8SStephen Boyd struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec,
15510861e5b8SStephen Boyd void *data);
1552494bfec9SShawn Guo struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data);
15530861e5b8SStephen Boyd struct clk_hw *of_clk_hw_onecell_get(struct of_phandle_args *clkspec,
15540861e5b8SStephen Boyd void *data);
15552e61dfb3SDinh Nguyen int of_clk_parent_fill(struct device_node *np, const char **parents,
15562e61dfb3SDinh Nguyen unsigned int size);
1557d56f8994SLee Jones int of_clk_detect_critical(struct device_node *np, int index,
1558d56f8994SLee Jones unsigned long *flags);
1559766e6a4eSGrant Likely
15600b151debSSebastian Hesselbarth #else /* !CONFIG_OF */
1561f2f6c255SPrashant Gaikwad
of_clk_add_provider(struct device_node * np,struct clk * (* clk_src_get)(struct of_phandle_args * args,void * data),void * data)15620b151debSSebastian Hesselbarth static inline int of_clk_add_provider(struct device_node *np,
15630b151debSSebastian Hesselbarth struct clk *(*clk_src_get)(struct of_phandle_args *args,
15640b151debSSebastian Hesselbarth void *data),
15650b151debSSebastian Hesselbarth void *data)
15660b151debSSebastian Hesselbarth {
15670b151debSSebastian Hesselbarth return 0;
15680b151debSSebastian Hesselbarth }
of_clk_add_hw_provider(struct device_node * np,struct clk_hw * (* get)(struct of_phandle_args * clkspec,void * data),void * data)15690861e5b8SStephen Boyd static inline int of_clk_add_hw_provider(struct device_node *np,
15700861e5b8SStephen Boyd struct clk_hw *(*get)(struct of_phandle_args *clkspec,
15710861e5b8SStephen Boyd void *data),
15720861e5b8SStephen Boyd void *data)
15730861e5b8SStephen Boyd {
15740861e5b8SStephen Boyd return 0;
15750861e5b8SStephen Boyd }
devm_of_clk_add_hw_provider(struct device * dev,struct clk_hw * (* get)(struct of_phandle_args * clkspec,void * data),void * data)1576aa795c41SStephen Boyd static inline int devm_of_clk_add_hw_provider(struct device *dev,
1577aa795c41SStephen Boyd struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1578aa795c41SStephen Boyd void *data),
1579aa795c41SStephen Boyd void *data)
1580aa795c41SStephen Boyd {
1581aa795c41SStephen Boyd return 0;
1582aa795c41SStephen Boyd }
of_clk_del_provider(struct device_node * np)158320dd882aSGeert Uytterhoeven static inline void of_clk_del_provider(struct device_node *np) {}
15841c8934b4SAndy Shevchenko
of_clk_src_simple_get(struct of_phandle_args * clkspec,void * data)15850b151debSSebastian Hesselbarth static inline struct clk *of_clk_src_simple_get(
15860b151debSSebastian Hesselbarth struct of_phandle_args *clkspec, void *data)
15870b151debSSebastian Hesselbarth {
15880b151debSSebastian Hesselbarth return ERR_PTR(-ENOENT);
15890b151debSSebastian Hesselbarth }
15900861e5b8SStephen Boyd static inline struct clk_hw *
of_clk_hw_simple_get(struct of_phandle_args * clkspec,void * data)15910861e5b8SStephen Boyd of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data)
15920861e5b8SStephen Boyd {
15930861e5b8SStephen Boyd return ERR_PTR(-ENOENT);
15940861e5b8SStephen Boyd }
of_clk_src_onecell_get(struct of_phandle_args * clkspec,void * data)15950b151debSSebastian Hesselbarth static inline struct clk *of_clk_src_onecell_get(
15960b151debSSebastian Hesselbarth struct of_phandle_args *clkspec, void *data)
15970b151debSSebastian Hesselbarth {
15980b151debSSebastian Hesselbarth return ERR_PTR(-ENOENT);
15990b151debSSebastian Hesselbarth }
16000861e5b8SStephen Boyd static inline struct clk_hw *
of_clk_hw_onecell_get(struct of_phandle_args * clkspec,void * data)16010861e5b8SStephen Boyd of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data)
16020861e5b8SStephen Boyd {
16030861e5b8SStephen Boyd return ERR_PTR(-ENOENT);
16040861e5b8SStephen Boyd }
of_clk_parent_fill(struct device_node * np,const char ** parents,unsigned int size)1605679c51cfSStephen Boyd static inline int of_clk_parent_fill(struct device_node *np,
1606679c51cfSStephen Boyd const char **parents, unsigned int size)
1607679c51cfSStephen Boyd {
1608679c51cfSStephen Boyd return 0;
1609679c51cfSStephen Boyd }
of_clk_detect_critical(struct device_node * np,int index,unsigned long * flags)1610d56f8994SLee Jones static inline int of_clk_detect_critical(struct device_node *np, int index,
1611d56f8994SLee Jones unsigned long *flags)
1612d56f8994SLee Jones {
1613d56f8994SLee Jones return 0;
1614d56f8994SLee Jones }
16150b151debSSebastian Hesselbarth #endif /* CONFIG_OF */
1616aa514ce3SGerhard Sittig
161743536548SKeerthy void clk_gate_restore_context(struct clk_hw *hw);
161843536548SKeerthy
1619b2476490SMike Turquette #endif /* CLK_PROVIDER_H */
1620