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/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dmediatek,smi-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/memory-controllers/mediatek,smi-common.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Yong Wu <yong.wu@mediatek.com>
17 which generation the SoCs use:
18 generation 1: mt2701 and mt7623.
19 generation 2: mt2712, mt6779, mt8167, mt8173, mt8183, mt8186, mt8188, mt8192 and mt8195.
21 There's slight differences between the two SMI, for generation 2, the
23 for generation 1, the register is at smi ao base(smi always on register
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dimx7ulp-scg-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx7ulp-scg-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX7ULP System Clock Generation (SCG) modules Clock Controller
10 - A.s. Dong <aisheng.dong@nxp.com>
13 i.MX7ULP Clock functions are under joint control of the System
14 Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
18 and A7 domain. Except for a few clock sources shared between two
19 domains, such as the System Oscillator clock, the Slow IRC (SIRC),
[all …]
H A Dimx8ulp-cgc-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx8ulp-cgc-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8ULP Clock Generation & Control(CGC) Module
10 - Jacky Bai <ping.bai@nxp.com>
13 On i.MX8ULP, The clock sources generation, distribution and management is
20 - fsl,imx8ulp-cgc1
21 - fsl,imx8ulp-cgc2
26 '#clock-cells':
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H A Dlpc1850-cgu.txt1 * NXP LPC1850 Clock Generation Unit (CGU)
4 peripheral blocks of the LPC18xx. Each independent clock is called
5 a base clock and itself is one of the inputs to the two Clock
9 The CGU selects the inputs to the clock generators from multiple
10 clock sources, controls the clock generation, and routes the outputs
11 of the clock generators through the clock source bus to the output
12 stages. Each output stage provides an independent clock source and
15 - Above text taken from NXP LPC1850 User Manual.
18 This binding uses the common clock binding:
19 Documentation/devicetree/bindings/clock/clock-bindings.txt
[all …]
H A Dimx8ulp-pcc-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx8ulp-pcc-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8ULP Peripheral Clock Controller(PCC) Module
10 - Jacky Bai <ping.bai@nxp.com>
13 On i.MX8ULP, The clock sources generation, distribution and management is
15 software reset, clock selection, optional division and clock gating mode
21 - fsl,imx8ulp-pcc3
22 - fsl,imx8ulp-pcc4
[all …]
H A Dintel,cgu-lgm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/intel,cgu-lgm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Intel Lightning Mountain SoC's Clock Controller(CGU)
10 - Rahul Tanwar <rahul.tanwar@linux.intel.com>
13 Lightning Mountain(LGM) SoC's Clock Generation Unit(CGU) driver provides
17 Please refer to include/dt-bindings/clock/intel,lgm-clk.h header file, it
23 const: intel,cgu-lgm
28 '#clock-cells':
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H A Dapple,nco.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/apple,nco.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Martin Povišer <povik+lin@cutebit.org>
14 such as the t8103 (M1) is a programmable clock generator performing
15 fractional division of a high frequency input clock.
18 generation of audio bitclocks.
23 - enum:
24 - apple,t6000-nco
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H A Dimx7ulp-pcc-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx7ulp-pcc-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX7ULP Peripheral Clock Control (PCC) modules Clock Controller
10 - A.s. Dong <aisheng.dong@nxp.com>
13 i.MX7ULP Clock functions are under joint control of the System
14 Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
18 and A7 domain. Except for a few clock sources shared between two
19 domains, such as the System Oscillator clock, the Slow IRC (SIRC),
[all …]
H A Drenesas,5p35023.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,5p35023.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas 5p35023 VersaClock 3 programmable I2C clock generator
10 - Biju Das <biju.das.jz@bp.renesas.com>
13 The 5P35023 is a VersaClock programmable clock generator and
14 is designed for low-power, consumer, and high-performance PCI
25 boots. Any configuration not supported by the common clock framework
29 …renesas.com/us/en/products/clocks-timing/clock-generation/programmable-clocks/5p35023-versaclock-3…
[all …]
/openbmc/linux/Documentation/devicetree/bindings/iommu/
H A Dmediatek,iommu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Yong Wu <yong.wu@mediatek.com>
14 this M4U have two generations of HW architecture. Generation one uses flat
15 pagetable, and only supports 4K size page mapping. Generation two uses the
16 ARM Short-Descriptor translation table format for address translation.
24 +--------+
26 gals0-rx gals1-rx (Global Async Local Sync rx)
29 gals0-tx gals1-tx (Global Async Local Sync tx)
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/openbmc/u-boot/doc/device-tree-bindings/clock/
H A Dsnps,hsdk-cgu.txt1 * Synopsys HSDK clock generation unit
3 The Synopsys HSDK clock controller generates and supplies clock to various
8 - compatible: should be "snps,hsdk-cgu-clock"
9 - reg: the pair of physical base address and length of clock generation unit
11 - #clock-cells: should be 1.
13 Each clock is assigned an identifier and client nodes can use this identifier
14 to specify the clock which they consume. All available clocks are defined as
15 preprocessor macros in the dt-bindings/clock/snps,hsdk-cgu.h headers and can be
18 Example: Clock controller node:
20 cgu_clk: cgu-clk@f0000000 {
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/openbmc/linux/Documentation/networking/dsa/
H A Dsja1105.rst8 The NXP SJA1105 is a family of 10 SPI-managed automotive switches:
10 - SJA1105E: First generation, no TTEthernet
11 - SJA1105T: First generation, TTEthernet
12 - SJA1105P: Second generation, no TTEthernet, no SGMII
13 - SJA1105Q: Second generation, TTEthernet, no SGMII
14 - SJA1105R: Second generation, no TTEthernet, SGMII
15 - SJA1105S: Second generation, TTEthernet, SGMII
16 - SJA1110A: Third generation, TTEthernet, SGMII, integrated 100base-T1 and
17 100base-TX PHYs
18 - SJA1110B: Third generation, TTEthernet, SGMII, 100base-T1, 100base-TX
[all …]
/openbmc/linux/drivers/net/dsa/mv88e6xxx/
H A Dptp.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
33 /* Offset 0x01: Timestamp Clock Period (ps) */
36 /* Offset 0x02/0x03: Trigger Generation Amount */
40 /* Offset 0x04: Clock Compensation */
46 /* Offset 0x06: Ingress Rate Limiter Clock Generation Amount */
70 /* Offset 0x10/0x11: Trig Generation Time */
160 return -1; in mv88e6xxx_hwtstamp_work()
/openbmc/linux/drivers/clk/mmp/
H A Dclk-apbc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * mmp APB clock operation source file
17 /* Common APB clock register bit definitions */
18 #define APBC_APBCLK (1 << 0) /* APB Bus Clock Enable */
19 #define APBC_FNCLK (1 << 1) /* Functional Clock Enable */
20 #define APBC_RST (1 << 2) /* Reset Generation */
21 #define APBC_POWER (1 << 7) /* Reset Generation */
39 * It may share same register as MUX clock, in clk_apbc_prepare()
42 if (apbc->lock) in clk_apbc_prepare()
43 spin_lock_irqsave(apbc->lock, flags); in clk_apbc_prepare()
[all …]
/openbmc/u-boot/drivers/timer/
H A Dstm32_timer.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
19 /* Event Generation Register register */
56 struct stm32_timer_regs *regs = priv->base; in stm32_timer_get_count()
58 *count = readl(&regs->cnt); in stm32_timer_get_count()
75 return -EINVAL; in stm32_timer_probe()
77 priv->base = (struct stm32_timer_regs *)addr; in stm32_timer_probe()
85 dev_err(dev, "failed to enable clock\n"); in stm32_timer_probe()
89 regs = priv->base; in stm32_timer_probe()
92 clrbits_le32(&regs->cr1, CR1_CEN); in stm32_timer_probe()
[all …]
/openbmc/linux/sound/firewire/tascam/
H A Dtascam-stream.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * tascam-stream.c - a part of driver for TASCAM FireWire series
23 err = snd_fw_transaction(tscm->unit, TCODE_READ_QUADLET_REQUEST, in get_clock()
33 // In intermediate state after changing clock status. in get_clock()
39 return -EAGAIN; in get_clock()
45 enum snd_tscm_clock clock) in set_clock() argument
70 return -EAGAIN; in set_clock()
74 if (clock != INT_MAX) { in set_clock()
76 data |= clock + 1; in set_clock()
81 err = snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST, in set_clock()
[all …]
/openbmc/linux/sound/firewire/digi00x/
H A Ddigi00x-stream.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * digi00x-stream.c - a part of driver for Digidesign Digi 002/003 family
5 * Copyright (c) 2014-2015 Takashi Sakamoto
36 err = snd_fw_transaction(dg00x->unit, TCODE_READ_QUADLET_REQUEST, in snd_dg00x_stream_get_local_rate()
46 err = -EIO; in snd_dg00x_stream_get_local_rate()
61 return -EINVAL; in snd_dg00x_stream_set_local_rate()
64 return snd_fw_transaction(dg00x->unit, TCODE_WRITE_QUADLET_REQUEST, in snd_dg00x_stream_set_local_rate()
70 enum snd_dg00x_clock *clock) in snd_dg00x_stream_get_clock() argument
75 err = snd_fw_transaction(dg00x->unit, TCODE_READ_QUADLET_REQUEST, in snd_dg00x_stream_get_clock()
81 *clock = be32_to_cpu(reg) & 0x0f; in snd_dg00x_stream_get_clock()
[all …]
/openbmc/linux/sound/firewire/fireface/
H A Dff-protocol-latter.c1 // SPDX-License-Identifier: GPL-2.0
2 // ff-protocol-latter.c - a part of driver for RME Fireface series
20 // 0x0f000000: effective rate of sampling clock
21 // 0x00f00000: detected rate of word clock on BNC interface
24 // 0x00000e00: effective source of sampling clock
27 // 0x00000600: Word clock on BNC interface
32 // 0x00000040: Synchronized to word clock on BNC interface
36 // 0x00000004: Lock word clock on BNC interface
41 // 0xf0000000: effective rate of sampling clock
42 // 0x0f000000: detected rate of ADAT-B on 2nd optical interface
[all …]
/openbmc/linux/drivers/clk/x86/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
6 bool "Clock driver for Lightning Mountain(LGM) platform"
8 Clock Generation Unit(CGU) driver for MaxLinear's x86 based
/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Dnxp,tpm-timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/nxp,tpm-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dong Aisheng <aisheng.dong@nxp.com>
14 and the generation of PWM signals to control electric motor and power
16 are clocked by an asynchronous clock that can remain enabled in low
23 - const: fsl,imx7ulp-tpm
24 - items:
25 - const: fsl,imx8ulp-tpm
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-armada100/
H A Darmada100.h1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
14 /* Common APB clock register bit definitions */
15 #define APBC_APBCLK (1<<0) /* APB Bus Clock Enable */
16 #define APBC_FNCLK (1<<1) /* Functional Clock Enable */
17 #define APBC_RST (1<<2) /* Reset Generation */
18 /* Functional Clock Selection Mask */
21 /* Fast Ethernet Controller Clock register definition */
25 /* SSP2 Clock Control */
29 /* USB Clock/reset control bits */
/openbmc/linux/Documentation/mm/
H A Dmultigen_lru.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Multi-Gen LRU
6 The multi-gen LRU is an alternative LRU implementation that optimizes
14 ----------
20 * Simple self-correcting heuristics
23 implementations. In the multi-gen LRU, each generation represents a
25 (time-based) common frame of reference and therefore help make better
41 choices; thus self-correction is necessary.
43 The benefits of simple self-correcting heuristics are self-evident.
45 attainable. Specifically, pages in the same generation can be
[all …]
/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Drenesas,usb3-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/renesas,usb3-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car generation 3 USB 3.0 PHY
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
15 - enum:
16 - renesas,r8a774a1-usb3-phy # RZ/G2M
17 - renesas,r8a774b1-usb3-phy # RZ/G2N
18 - renesas,r8a774e1-usb3-phy # RZ/G2H
[all …]
/openbmc/linux/Documentation/devicetree/bindings/rtc/
H A Drtc-omap.txt1 TI Real Time Clock
4 - compatible:
5 - "ti,da830-rtc" - for RTC IP used similar to that on DA8xx SoC family.
6 - "ti,am3352-rtc" - for RTC IP used similar to that on AM335x SoC family.
7 This RTC IP has special WAKE-EN Register to enable
8 Wakeup generation for event Alarm. It can also be
11 - "ti,am4372-rtc" - for RTC IP used similar to that on AM437X SoC family.
12 - reg: Address range of rtc register set
13 - interrupts: rtc timer, alarm interrupts in order
16 - system-power-controller: whether the rtc is controlling the system power
[all …]
/openbmc/u-boot/include/
H A Dstm32_rcc.h1 /* SPDX-License-Identifier: GPL-2.0+ */
60 u32 cr; /* RCC clock control */
62 u32 cfgr; /* RCC clock configuration */
63 u32 cir; /* RCC clock interrupt */
71 u32 ahb1enr; /* RCC AHB1 peripheral clock enable */
72 u32 ahb2enr; /* RCC AHB2 peripheral clock enable */
73 u32 ahb3enr; /* RCC AHB3 peripheral clock enable */
75 u32 apb1enr; /* RCC APB1 peripheral clock enable */
76 u32 apb2enr; /* RCC APB2 peripheral clock enable */
86 u32 csr; /* RCC clock control & status */
[all …]

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