drivers/timer/stm32_timer.c

1 // SPDX-License-Identifier: GPL-2.0+
3  * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
19 /* Event Generation Register register  */
56 	struct stm32_timer_regs *regs = priv->base;  in stm32_timer_get_count()
58 	*count = readl(&regs->cnt);  in stm32_timer_get_count()
75 		return -EINVAL;  in stm32_timer_probe()
77 	priv->base = (struct stm32_timer_regs *)addr;  in stm32_timer_probe()
85 		dev_err(dev, "failed to enable clock\n");  in stm32_timer_probe()
89 	regs = priv->base;  in stm32_timer_probe()
92 	clrbits_le32(&regs->cr1, CR1_CEN);  in stm32_timer_probe()
94 	/* get timer clock */  in stm32_timer_probe()
98 	psc = (rate / CONFIG_SYS_HZ_CLOCK) - 1;  in stm32_timer_probe()
99 	writel(psc, &regs->psc);  in stm32_timer_probe()
102 	uc_priv->clock_rate = CONFIG_SYS_HZ_CLOCK;  in stm32_timer_probe()
104 	/* Configure timer for auto-reload */  in stm32_timer_probe()
105 	setbits_le32(&regs->cr1, CR1_ARPE);  in stm32_timer_probe()
108 	writel(GPT_FREE_RUNNING, &regs->arr);  in stm32_timer_probe()
111 	setbits_le32(&regs->cr1, CR1_CEN);  in stm32_timer_probe()
113 	/* Update generation */  in stm32_timer_probe()
114 	setbits_le32(&regs->egr, EGR_UG);  in stm32_timer_probe()
124 	{ .compatible = "st,stm32-timer" },