147592097SVladimir Oltean========================= 247592097SVladimir OlteanNXP SJA1105 switch driver 347592097SVladimir Oltean========================= 447592097SVladimir Oltean 547592097SVladimir OlteanOverview 647592097SVladimir Oltean======== 747592097SVladimir Oltean 844531076SVladimir OlteanThe NXP SJA1105 is a family of 10 SPI-managed automotive switches: 947592097SVladimir Oltean 1047592097SVladimir Oltean- SJA1105E: First generation, no TTEthernet 1147592097SVladimir Oltean- SJA1105T: First generation, TTEthernet 1247592097SVladimir Oltean- SJA1105P: Second generation, no TTEthernet, no SGMII 1347592097SVladimir Oltean- SJA1105Q: Second generation, TTEthernet, no SGMII 1447592097SVladimir Oltean- SJA1105R: Second generation, no TTEthernet, SGMII 1547592097SVladimir Oltean- SJA1105S: Second generation, TTEthernet, SGMII 1644531076SVladimir Oltean- SJA1110A: Third generation, TTEthernet, SGMII, integrated 100base-T1 and 1744531076SVladimir Oltean 100base-TX PHYs 1844531076SVladimir Oltean- SJA1110B: Third generation, TTEthernet, SGMII, 100base-T1, 100base-TX 1944531076SVladimir Oltean- SJA1110C: Third generation, TTEthernet, SGMII, 100base-T1, 100base-TX 2044531076SVladimir Oltean- SJA1110D: Third generation, TTEthernet, SGMII, 100base-T1 2147592097SVladimir Oltean 2247592097SVladimir OlteanBeing automotive parts, their configuration interface is geared towards 2347592097SVladimir Olteanset-and-forget use, with minimal dynamic interaction at runtime. They 2447592097SVladimir Olteanrequire a static configuration to be composed by software and packed 2547592097SVladimir Olteanwith CRC and table headers, and sent over SPI. 2647592097SVladimir Oltean 2747592097SVladimir OlteanThe static configuration is composed of several configuration tables. Each 2847592097SVladimir Olteantable takes a number of entries. Some configuration tables can be (partially) 2947592097SVladimir Olteanreconfigured at runtime, some not. Some tables are mandatory, some not: 3047592097SVladimir Oltean 3147592097SVladimir Oltean============================= ================== ============================= 3247592097SVladimir OlteanTable Mandatory Reconfigurable 3347592097SVladimir Oltean============================= ================== ============================= 3447592097SVladimir OlteanSchedule no no 3547592097SVladimir OlteanSchedule entry points if Scheduling no 3647592097SVladimir OlteanVL Lookup no no 3747592097SVladimir OlteanVL Policing if VL Lookup no 3847592097SVladimir OlteanVL Forwarding if VL Lookup no 3947592097SVladimir OlteanL2 Lookup no no 4047592097SVladimir OlteanL2 Policing yes no 4147592097SVladimir OlteanVLAN Lookup yes yes 4247592097SVladimir OlteanL2 Forwarding yes partially (fully on P/Q/R/S) 4347592097SVladimir OlteanMAC Config yes partially (fully on P/Q/R/S) 4447592097SVladimir OlteanSchedule Params if Scheduling no 4547592097SVladimir OlteanSchedule Entry Points Params if Scheduling no 4647592097SVladimir OlteanVL Forwarding Params if VL Forwarding no 4747592097SVladimir OlteanL2 Lookup Params no partially (fully on P/Q/R/S) 4847592097SVladimir OlteanL2 Forwarding Params yes no 4947592097SVladimir OlteanClock Sync Params no no 5047592097SVladimir OlteanAVB Params no no 5147592097SVladimir OlteanGeneral Params yes partially 5247592097SVladimir OlteanRetagging no yes 5347592097SVladimir OlteanxMII Params yes no 5447592097SVladimir OlteanSGMII no yes 5547592097SVladimir Oltean============================= ================== ============================= 5647592097SVladimir Oltean 5747592097SVladimir Oltean 5847592097SVladimir OlteanAlso the configuration is write-only (software cannot read it back from the 5947592097SVladimir Olteanswitch except for very few exceptions). 6047592097SVladimir Oltean 6147592097SVladimir OlteanThe driver creates a static configuration at probe time, and keeps it at 6247592097SVladimir Olteanall times in memory, as a shadow for the hardware state. When required to 6347592097SVladimir Olteanchange a hardware setting, the static configuration is also updated. 6447592097SVladimir OlteanIf that changed setting can be transmitted to the switch through the dynamic 6547592097SVladimir Olteanreconfiguration interface, it is; otherwise the switch is reset and 6647592097SVladimir Olteanreprogrammed with the updated static configuration. 6747592097SVladimir Oltean 6847592097SVladimir OlteanSwitching features 6947592097SVladimir Oltean================== 7047592097SVladimir Oltean 7147592097SVladimir OlteanThe driver supports the configuration of L2 forwarding rules in hardware for 7247592097SVladimir Olteanport bridging. The forwarding, broadcast and flooding domain between ports can 7347592097SVladimir Olteanbe restricted through two methods: either at the L2 forwarding level (isolate 7447592097SVladimir Olteanone bridge's ports from another's) or at the VLAN port membership level 7547592097SVladimir Oltean(isolate ports within the same bridge). The final forwarding decision taken by 7647592097SVladimir Olteanthe hardware is a logical AND of these two sets of rules. 7747592097SVladimir Oltean 7847592097SVladimir OlteanThe hardware tags all traffic internally with a port-based VLAN (pvid), or it 7947592097SVladimir Olteandecodes the VLAN information from the 802.1Q tag. Advanced VLAN classification 8047592097SVladimir Olteanis not possible. Once attributed a VLAN tag, frames are checked against the 8147592097SVladimir Olteanport's membership rules and dropped at ingress if they don't match any VLAN. 8247592097SVladimir OlteanThis behavior is available when switch ports are enslaved to a bridge with 8347592097SVladimir Oltean``vlan_filtering 1``. 8447592097SVladimir Oltean 8547592097SVladimir OlteanNormally the hardware is not configurable with respect to VLAN awareness, but 8647592097SVladimir Olteanby changing what TPID the switch searches 802.1Q tags for, the semantics of a 8747592097SVladimir Olteanbridge with ``vlan_filtering 0`` can be kept (accept all traffic, tagged or 8847592097SVladimir Olteanuntagged), and therefore this mode is also supported. 8947592097SVladimir Oltean 9047592097SVladimir OlteanSegregating the switch ports in multiple bridges is supported (e.g. 2 + 2), but 9147592097SVladimir Olteanall bridges should have the same level of VLAN awareness (either both have 925702d94bSVladimir Oltean``vlan_filtering`` 0, or both 1). 9347592097SVladimir Oltean 940a58d471SVladimir OlteanTopology and loop detection through STP is supported. 950a58d471SVladimir Oltean 967c95afa4SVladimir OlteanOffloads 977c95afa4SVladimir Oltean======== 987c95afa4SVladimir Oltean 997c95afa4SVladimir OlteanTime-aware scheduling 1007c95afa4SVladimir Oltean--------------------- 1017c95afa4SVladimir Oltean 1027c95afa4SVladimir OlteanThe switch supports a variation of the enhancements for scheduled traffic 1037c95afa4SVladimir Olteanspecified in IEEE 802.1Q-2018 (formerly 802.1Qbv). This means it can be used to 1047c95afa4SVladimir Olteanensure deterministic latency for priority traffic that is sent in-band with its 1057c95afa4SVladimir Olteangate-open event in the network schedule. 1067c95afa4SVladimir Oltean 1077c95afa4SVladimir OlteanThis capability can be managed through the tc-taprio offload ('flags 2'). The 1087c95afa4SVladimir Olteandifference compared to the software implementation of taprio is that the latter 1097c95afa4SVladimir Olteanwould only be able to shape traffic originated from the CPU, but not 1107c95afa4SVladimir Olteanautonomously forwarded flows. 1117c95afa4SVladimir Oltean 1127c95afa4SVladimir OlteanThe device has 8 traffic classes, and maps incoming frames to one of them based 1137c95afa4SVladimir Olteanon the VLAN PCP bits (if no VLAN is present, the port-based default is used). 1147c95afa4SVladimir OlteanAs described in the previous sections, depending on the value of 1157c95afa4SVladimir Oltean``vlan_filtering``, the EtherType recognized by the switch as being VLAN can 1167c95afa4SVladimir Olteaneither be the typical 0x8100 or a custom value used internally by the driver 1177c95afa4SVladimir Olteanfor tagging. Therefore, the switch ignores the VLAN PCP if used in standalone 1187c95afa4SVladimir Olteanor bridge mode with ``vlan_filtering=0``, as it will not recognize the 0x8100 1197c95afa4SVladimir OlteanEtherType. In these modes, injecting into a particular TX queue can only be 1207c95afa4SVladimir Olteandone by the DSA net devices, which populate the PCP field of the tagging header 1217c95afa4SVladimir Olteanon egress. Using ``vlan_filtering=1``, the behavior is the other way around: 1227c95afa4SVladimir Olteanoffloaded flows can be steered to TX queues based on the VLAN PCP, but the DSA 1237c95afa4SVladimir Olteannet devices are no longer able to do that. To inject frames into a hardware TX 1247c95afa4SVladimir Olteanqueue with VLAN awareness active, it is necessary to create a VLAN 1257c95afa4SVladimir Olteansub-interface on the DSA master port, and send normal (0x8100) VLAN-tagged 1267c95afa4SVladimir Olteantowards the switch, with the VLAN PCP bits set appropriately. 1277c95afa4SVladimir Oltean 1287c95afa4SVladimir OlteanManagement traffic (having DMAC 01-80-C2-xx-xx-xx or 01-19-1B-xx-xx-xx) is the 1297c95afa4SVladimir Olteannotable exception: the switch always treats it with a fixed priority and 1307c95afa4SVladimir Olteandisregards any VLAN PCP bits even if present. The traffic class for management 1317c95afa4SVladimir Olteantraffic has a value of 7 (highest priority) at the moment, which is not 1327c95afa4SVladimir Olteanconfigurable in the driver. 1337c95afa4SVladimir Oltean 1347c95afa4SVladimir OlteanBelow is an example of configuring a 500 us cyclic schedule on egress port 1357c95afa4SVladimir Oltean``swp5``. The traffic class gate for management traffic (7) is open for 100 us, 1367c95afa4SVladimir Olteanand the gates for all other traffic classes are open for 400 us:: 1377c95afa4SVladimir Oltean 1387c95afa4SVladimir Oltean #!/bin/bash 1397c95afa4SVladimir Oltean 1407c95afa4SVladimir Oltean set -e -u -o pipefail 1417c95afa4SVladimir Oltean 1427c95afa4SVladimir Oltean NSEC_PER_SEC="1000000000" 1437c95afa4SVladimir Oltean 1447c95afa4SVladimir Oltean gatemask() { 1457c95afa4SVladimir Oltean local tc_list="$1" 1467c95afa4SVladimir Oltean local mask=0 1477c95afa4SVladimir Oltean 1487c95afa4SVladimir Oltean for tc in ${tc_list}; do 1497c95afa4SVladimir Oltean mask=$((${mask} | (1 << ${tc}))) 1507c95afa4SVladimir Oltean done 1517c95afa4SVladimir Oltean 1527c95afa4SVladimir Oltean printf "%02x" ${mask} 1537c95afa4SVladimir Oltean } 1547c95afa4SVladimir Oltean 1557c95afa4SVladimir Oltean if ! systemctl is-active --quiet ptp4l; then 1567c95afa4SVladimir Oltean echo "Please start the ptp4l service" 1577c95afa4SVladimir Oltean exit 1587c95afa4SVladimir Oltean fi 1597c95afa4SVladimir Oltean 1607c95afa4SVladimir Oltean now=$(phc_ctl /dev/ptp1 get | gawk '/clock time is/ { print $5; }') 1617c95afa4SVladimir Oltean # Phase-align the base time to the start of the next second. 1627c95afa4SVladimir Oltean sec=$(echo "${now}" | gawk -F. '{ print $1; }') 1637c95afa4SVladimir Oltean base_time="$(((${sec} + 1) * ${NSEC_PER_SEC}))" 1647c95afa4SVladimir Oltean 1657c95afa4SVladimir Oltean tc qdisc add dev swp5 parent root handle 100 taprio \ 1667c95afa4SVladimir Oltean num_tc 8 \ 1677c95afa4SVladimir Oltean map 0 1 2 3 5 6 7 \ 1687c95afa4SVladimir Oltean queues 1@0 1@1 1@2 1@3 1@4 1@5 1@6 1@7 \ 1697c95afa4SVladimir Oltean base-time ${base_time} \ 1707c95afa4SVladimir Oltean sched-entry S $(gatemask 7) 100000 \ 1717c95afa4SVladimir Oltean sched-entry S $(gatemask "0 1 2 3 4 5 6") 400000 \ 1727c95afa4SVladimir Oltean flags 2 1737c95afa4SVladimir Oltean 1747c95afa4SVladimir OlteanIt is possible to apply the tc-taprio offload on multiple egress ports. There 1757c95afa4SVladimir Olteanare hardware restrictions related to the fact that no gate event may trigger 1767c95afa4SVladimir Olteansimultaneously on two ports. The driver checks the consistency of the schedules 1777c95afa4SVladimir Olteanagainst this restriction and errors out when appropriate. Schedule analysis is 1787c95afa4SVladimir Olteanneeded to avoid this, which is outside the scope of the document. 1797c95afa4SVladimir Oltean 18047cfa3afSVladimir OlteanRouting actions (redirect, trap, drop) 18147cfa3afSVladimir Oltean-------------------------------------- 18247cfa3afSVladimir Oltean 18347cfa3afSVladimir OlteanThe switch is able to offload flow-based redirection of packets to a set of 18447cfa3afSVladimir Olteandestination ports specified by the user. Internally, this is implemented by 18547cfa3afSVladimir Olteanmaking use of Virtual Links, a TTEthernet concept. 18647cfa3afSVladimir Oltean 18747cfa3afSVladimir OlteanThe driver supports 2 types of keys for Virtual Links: 18847cfa3afSVladimir Oltean 18947cfa3afSVladimir Oltean- VLAN-aware virtual links: these match on destination MAC address, VLAN ID and 19047cfa3afSVladimir Oltean VLAN PCP. 19147cfa3afSVladimir Oltean- VLAN-unaware virtual links: these match on destination MAC address only. 19247cfa3afSVladimir Oltean 19347cfa3afSVladimir OlteanThe VLAN awareness state of the bridge (vlan_filtering) cannot be changed while 19447cfa3afSVladimir Olteanthere are virtual link rules installed. 19547cfa3afSVladimir Oltean 19647cfa3afSVladimir OlteanComposing multiple actions inside the same rule is supported. When only routing 19747cfa3afSVladimir Olteanactions are requested, the driver creates a "non-critical" virtual link. When 19847cfa3afSVladimir Olteanthe action list also contains tc-gate (more details below), the virtual link 19947cfa3afSVladimir Olteanbecomes "time-critical" (draws frame buffers from a reserved memory partition, 20047cfa3afSVladimir Olteanetc). 20147cfa3afSVladimir Oltean 20247cfa3afSVladimir OlteanThe 3 routing actions that are supported are "trap", "drop" and "redirect". 20347cfa3afSVladimir Oltean 20447cfa3afSVladimir OlteanExample 1: send frames received on swp2 with a DA of 42:be:24:9b:76:20 to the 20547cfa3afSVladimir OlteanCPU and to swp3. This type of key (DA only) when the port's VLAN awareness 20647cfa3afSVladimir Olteanstate is off:: 20747cfa3afSVladimir Oltean 20847cfa3afSVladimir Oltean tc qdisc add dev swp2 clsact 20947cfa3afSVladimir Oltean tc filter add dev swp2 ingress flower skip_sw dst_mac 42:be:24:9b:76:20 \ 21047cfa3afSVladimir Oltean action mirred egress redirect dev swp3 \ 21147cfa3afSVladimir Oltean action trap 21247cfa3afSVladimir Oltean 21347cfa3afSVladimir OlteanExample 2: drop frames received on swp2 with a DA of 42:be:24:9b:76:20, a VID 21447cfa3afSVladimir Olteanof 100 and a PCP of 0:: 21547cfa3afSVladimir Oltean 21647cfa3afSVladimir Oltean tc filter add dev swp2 ingress protocol 802.1Q flower skip_sw \ 21747cfa3afSVladimir Oltean dst_mac 42:be:24:9b:76:20 vlan_id 100 vlan_prio 0 action drop 21847cfa3afSVladimir Oltean 21947cfa3afSVladimir OlteanTime-based ingress policing 22047cfa3afSVladimir Oltean--------------------------- 22147cfa3afSVladimir Oltean 22247cfa3afSVladimir OlteanThe TTEthernet hardware abilities of the switch can be constrained to act 22347cfa3afSVladimir Olteansimilarly to the Per-Stream Filtering and Policing (PSFP) clause specified in 22447cfa3afSVladimir OlteanIEEE 802.1Q-2018 (formerly 802.1Qci). This means it can be used to perform 22547cfa3afSVladimir Olteantight timing-based admission control for up to 1024 flows (identified by a 22647cfa3afSVladimir Olteantuple composed of destination MAC address, VLAN ID and VLAN PCP). Packets which 22747cfa3afSVladimir Olteanare received outside their expected reception window are dropped. 22847cfa3afSVladimir Oltean 22947cfa3afSVladimir OlteanThis capability can be managed through the offload of the tc-gate action. As 23047cfa3afSVladimir Olteanrouting actions are intrinsic to virtual links in TTEthernet (which performs 23147cfa3afSVladimir Olteanexplicit routing of time-critical traffic and does not leave that in the hands 23247cfa3afSVladimir Olteanof the FDB, flooding etc), the tc-gate action may never appear alone when 23347cfa3afSVladimir Olteanasking sja1105 to offload it. One (or more) redirect or trap actions must also 23447cfa3afSVladimir Olteanfollow along. 23547cfa3afSVladimir Oltean 23647cfa3afSVladimir OlteanExample: create a tc-taprio schedule that is phase-aligned with a tc-gate 23747cfa3afSVladimir Olteanschedule (the clocks must be synchronized by a 1588 application stack, which is 23847cfa3afSVladimir Olteanoutside the scope of this document). No packet delivered by the sender will be 23947cfa3afSVladimir Olteandropped. Note that the reception window is larger than the transmission window 24047cfa3afSVladimir Oltean(and much more so, in this example) to compensate for the packet propagation 24147cfa3afSVladimir Olteandelay of the link (which can be determined by the 1588 application stack). 24247cfa3afSVladimir Oltean 24347cfa3afSVladimir OlteanReceiver (sja1105):: 24447cfa3afSVladimir Oltean 24547cfa3afSVladimir Oltean tc qdisc add dev swp2 clsact 24647cfa3afSVladimir Oltean now=$(phc_ctl /dev/ptp1 get | awk '/clock time is/ {print $5}') && \ 24747cfa3afSVladimir Oltean sec=$(echo $now | awk -F. '{print $1}') && \ 24847cfa3afSVladimir Oltean base_time="$(((sec + 2) * 1000000000))" && \ 24947cfa3afSVladimir Oltean echo "base time ${base_time}" 25047cfa3afSVladimir Oltean tc filter add dev swp2 ingress flower skip_sw \ 25147cfa3afSVladimir Oltean dst_mac 42:be:24:9b:76:20 \ 25247cfa3afSVladimir Oltean action gate base-time ${base_time} \ 25347cfa3afSVladimir Oltean sched-entry OPEN 60000 -1 -1 \ 25447cfa3afSVladimir Oltean sched-entry CLOSE 40000 -1 -1 \ 25547cfa3afSVladimir Oltean action trap 25647cfa3afSVladimir Oltean 25747cfa3afSVladimir OlteanSender:: 25847cfa3afSVladimir Oltean 25947cfa3afSVladimir Oltean now=$(phc_ctl /dev/ptp0 get | awk '/clock time is/ {print $5}') && \ 26047cfa3afSVladimir Oltean sec=$(echo $now | awk -F. '{print $1}') && \ 26147cfa3afSVladimir Oltean base_time="$(((sec + 2) * 1000000000))" && \ 26247cfa3afSVladimir Oltean echo "base time ${base_time}" 26347cfa3afSVladimir Oltean tc qdisc add dev eno0 parent root taprio \ 26447cfa3afSVladimir Oltean num_tc 8 \ 26547cfa3afSVladimir Oltean map 0 1 2 3 4 5 6 7 \ 26647cfa3afSVladimir Oltean queues 1@0 1@1 1@2 1@3 1@4 1@5 1@6 1@7 \ 26747cfa3afSVladimir Oltean base-time ${base_time} \ 26847cfa3afSVladimir Oltean sched-entry S 01 50000 \ 26947cfa3afSVladimir Oltean sched-entry S 00 50000 \ 27047cfa3afSVladimir Oltean flags 2 27147cfa3afSVladimir Oltean 27247cfa3afSVladimir OlteanThe engine used to schedule the ingress gate operations is the same that the 27347cfa3afSVladimir Olteanone used for the tc-taprio offload. Therefore, the restrictions regarding the 27447cfa3afSVladimir Olteanfact that no two gate actions (either tc-gate or tc-taprio gates) may fire at 27547cfa3afSVladimir Olteanthe same time (during the same 200 ns slot) still apply. 27647cfa3afSVladimir Oltean 27747cfa3afSVladimir OlteanTo come in handy, it is possible to share time-triggered virtual links across 27847cfa3afSVladimir Olteanmore than 1 ingress port, via flow blocks. In this case, the restriction of 27947cfa3afSVladimir Olteanfiring at the same time does not apply because there is a single schedule in 28047cfa3afSVladimir Olteanthe system, that of the shared virtual link:: 28147cfa3afSVladimir Oltean 28247cfa3afSVladimir Oltean tc qdisc add dev swp2 ingress_block 1 clsact 28347cfa3afSVladimir Oltean tc qdisc add dev swp3 ingress_block 1 clsact 28447cfa3afSVladimir Oltean tc filter add block 1 flower skip_sw dst_mac 42:be:24:9b:76:20 \ 28547cfa3afSVladimir Oltean action gate index 2 \ 28647cfa3afSVladimir Oltean base-time 0 \ 28747cfa3afSVladimir Oltean sched-entry OPEN 50000000 -1 -1 \ 28847cfa3afSVladimir Oltean sched-entry CLOSE 50000000 -1 -1 \ 28947cfa3afSVladimir Oltean action trap 29047cfa3afSVladimir Oltean 29147cfa3afSVladimir OlteanHardware statistics for each flow are also available ("pkts" counts the number 29247cfa3afSVladimir Olteanof dropped frames, which is a sum of frames dropped due to timing violations, 29347cfa3afSVladimir Olteanlack of destination ports and MTU enforcement checks). Byte-level counters are 29447cfa3afSVladimir Olteannot available. 29547cfa3afSVladimir Oltean 296*d27656d0SVladimir OlteanLimitations 297*d27656d0SVladimir Oltean=========== 298*d27656d0SVladimir Oltean 299*d27656d0SVladimir OlteanThe SJA1105 switch family always performs VLAN processing. When configured as 300*d27656d0SVladimir OlteanVLAN-unaware, frames carry a different VLAN tag internally, depending on 301*d27656d0SVladimir Olteanwhether the port is standalone or under a VLAN-unaware bridge. 302*d27656d0SVladimir Oltean 303*d27656d0SVladimir OlteanThe virtual link keys are always fixed at {MAC DA, VLAN ID, VLAN PCP}, but the 304*d27656d0SVladimir Olteandriver asks for the VLAN ID and VLAN PCP when the port is under a VLAN-aware 305*d27656d0SVladimir Olteanbridge. Otherwise, it fills in the VLAN ID and PCP automatically, based on 306*d27656d0SVladimir Olteanwhether the port is standalone or in a VLAN-unaware bridge, and accepts only 307*d27656d0SVladimir Oltean"VLAN-unaware" tc-flower keys (MAC DA). 308*d27656d0SVladimir Oltean 309*d27656d0SVladimir OlteanThe existing tc-flower keys that are offloaded using virtual links are no 310*d27656d0SVladimir Olteanlonger operational after one of the following happens: 311*d27656d0SVladimir Oltean 312*d27656d0SVladimir Oltean- port was standalone and joins a bridge (VLAN-aware or VLAN-unaware) 313*d27656d0SVladimir Oltean- port is part of a bridge whose VLAN awareness state changes 314*d27656d0SVladimir Oltean- port was part of a bridge and becomes standalone 315*d27656d0SVladimir Oltean- port was standalone, but another port joins a VLAN-aware bridge and this 316*d27656d0SVladimir Oltean changes the global VLAN awareness state of the bridge 317*d27656d0SVladimir Oltean 318*d27656d0SVladimir OlteanThe driver cannot veto all these operations, and it cannot update/remove the 319*d27656d0SVladimir Olteanexisting tc-flower filters either. So for proper operation, the tc-flower 320*d27656d0SVladimir Olteanfilters should be installed only after the forwarding configuration of the port 321*d27656d0SVladimir Olteanhas been made, and removed by user space before making any changes to it. 322*d27656d0SVladimir Oltean 32347592097SVladimir OlteanDevice Tree bindings and board design 32447592097SVladimir Oltean===================================== 32547592097SVladimir Oltean 326a11de925SMauro Carvalho ChehabThis section references ``Documentation/devicetree/bindings/net/dsa/nxp,sja1105.yaml`` 32747592097SVladimir Olteanand aims to showcase some potential switch caveats. 32847592097SVladimir Oltean 32947592097SVladimir OlteanRMII PHY role and out-of-band signaling 33047592097SVladimir Oltean--------------------------------------- 33147592097SVladimir Oltean 33247592097SVladimir OlteanIn the RMII spec, the 50 MHz clock signals are either driven by the MAC or by 33347592097SVladimir Olteanan external oscillator (but not by the PHY). 33447592097SVladimir OlteanBut the spec is rather loose and devices go outside it in several ways. 33547592097SVladimir OlteanSome PHYs go against the spec and may provide an output pin where they source 33647592097SVladimir Olteanthe 50 MHz clock themselves, in an attempt to be helpful. 33747592097SVladimir OlteanOn the other hand, the SJA1105 is only binary configurable - when in the RMII 33847592097SVladimir OlteanMAC role it will also attempt to drive the clock signal. To prevent this from 33947592097SVladimir Olteanhappening it must be put in RMII PHY role. 34047592097SVladimir OlteanBut doing so has some unintended consequences. 34147592097SVladimir OlteanIn the RMII spec, the PHY can transmit extra out-of-band signals via RXD[1:0]. 34247592097SVladimir OlteanThese are practically some extra code words (/J/ and /K/) sent prior to the 34347592097SVladimir Olteanpreamble of each frame. The MAC does not have this out-of-band signaling 34447592097SVladimir Olteanmechanism defined by the RMII spec. 34547592097SVladimir OlteanSo when the SJA1105 port is put in PHY role to avoid having 2 drivers on the 34647592097SVladimir Olteanclock signal, inevitably an RMII PHY-to-PHY connection is created. The SJA1105 34747592097SVladimir Olteanemulates a PHY interface fully and generates the /J/ and /K/ symbols prior to 34847592097SVladimir Olteanframe preambles, which the real PHY is not expected to understand. So the PHY 34947592097SVladimir Olteansimply encodes the extra symbols received from the SJA1105-as-PHY onto the 35047592097SVladimir Oltean100Base-Tx wire. 35147592097SVladimir OlteanOn the other side of the wire, some link partners might discard these extra 35247592097SVladimir Olteansymbols, while others might choke on them and discard the entire Ethernet 35347592097SVladimir Olteanframes that follow along. This looks like packet loss with some link partners 35447592097SVladimir Olteanbut not with others. 35547592097SVladimir OlteanThe take-away is that in RMII mode, the SJA1105 must be let to drive the 35647592097SVladimir Olteanreference clock if connected to a PHY. 35747592097SVladimir Oltean 35847592097SVladimir OlteanRGMII fixed-link and internal delays 35947592097SVladimir Oltean------------------------------------ 36047592097SVladimir Oltean 36147592097SVladimir OlteanAs mentioned in the bindings document, the second generation of devices has 36247592097SVladimir Olteantunable delay lines as part of the MAC, which can be used to establish the 36347592097SVladimir Olteancorrect RGMII timing budget. 36447592097SVladimir OlteanWhen powered up, these can shift the Rx and Tx clocks with a phase difference 36547592097SVladimir Olteanbetween 73.8 and 101.7 degrees. 36647592097SVladimir OlteanThe catch is that the delay lines need to lock onto a clock signal with a 36747592097SVladimir Olteanstable frequency. This means that there must be at least 2 microseconds of 36847592097SVladimir Olteansilence between the clock at the old vs at the new frequency. Otherwise the 36947592097SVladimir Olteanlock is lost and the delay lines must be reset (powered down and back up). 37047592097SVladimir OlteanIn RGMII the clock frequency changes with link speed (125 MHz at 1000 Mbps, 25 37147592097SVladimir OlteanMHz at 100 Mbps and 2.5 MHz at 10 Mbps), and link speed might change during the 37247592097SVladimir OlteanAN process. 37347592097SVladimir OlteanIn the situation where the switch port is connected through an RGMII fixed-link 37447592097SVladimir Olteanto a link partner whose link state life cycle is outside the control of Linux 37547592097SVladimir Oltean(such as a different SoC), then the delay lines would remain unlocked (and 37647592097SVladimir Olteaninactive) until there is manual intervention (ifdown/ifup on the switch port). 37747592097SVladimir OlteanThe take-away is that in RGMII mode, the switch's internal delays are only 37847592097SVladimir Olteanreliable if the link partner never changes link speeds, or if it does, it does 37947592097SVladimir Olteanso in a way that is coordinated with the switch port (practically, both ends of 38047592097SVladimir Olteanthe fixed-link are under control of the same Linux system). 38147592097SVladimir OlteanAs to why would a fixed-link interface ever change link speeds: there are 38247592097SVladimir OlteanEthernet controllers out there which come out of reset in 100 Mbps mode, and 38347592097SVladimir Olteantheir driver inevitably needs to change the speed and clock frequency if it's 38447592097SVladimir Olteanrequired to work at gigabit. 38547592097SVladimir Oltean 38647592097SVladimir OlteanMDIO bus and PHY management 38747592097SVladimir Oltean--------------------------- 38847592097SVladimir Oltean 38947592097SVladimir OlteanThe SJA1105 does not have an MDIO bus and does not perform in-band AN either. 39047592097SVladimir OlteanTherefore there is no link state notification coming from the switch device. 39147592097SVladimir OlteanA board would need to hook up the PHYs connected to the switch to any other 39247592097SVladimir OlteanMDIO bus available to Linux within the system (e.g. to the DSA master's MDIO 39347592097SVladimir Olteanbus). Link state management then works by the driver manually keeping in sync 39447592097SVladimir Oltean(over SPI commands) the MAC link speed with the settings negotiated by the PHY. 39544531076SVladimir Oltean 39644531076SVladimir OlteanBy comparison, the SJA1110 supports an MDIO slave access point over which its 39744531076SVladimir Olteaninternal 100base-T1 PHYs can be accessed from the host. This is, however, not 39844531076SVladimir Olteanused by the driver, instead the internal 100base-T1 and 100base-TX PHYs are 39944531076SVladimir Olteanaccessed through SPI commands, modeled in Linux as virtual MDIO buses. 40044531076SVladimir Oltean 40144531076SVladimir OlteanThe microcontroller attached to the SJA1110 port 0 also has an MDIO controller 40244531076SVladimir Olteanoperating in master mode, however the driver does not support this either, 40344531076SVladimir Olteansince the microcontroller gets disabled when the Linux driver operates. 40444531076SVladimir OlteanDiscrete PHYs connected to the switch ports should have their MDIO interface 40544531076SVladimir Olteanattached to an MDIO controller from the host system and not to the switch, 40644531076SVladimir Olteansimilar to SJA1105. 40744531076SVladimir Oltean 40844531076SVladimir OlteanPort compatibility matrix 40944531076SVladimir Oltean------------------------- 41044531076SVladimir Oltean 41144531076SVladimir OlteanThe SJA1105 port compatibility matrix is: 41244531076SVladimir Oltean 41344531076SVladimir Oltean===== ============== ============== ============== 41444531076SVladimir OlteanPort SJA1105E/T SJA1105P/Q SJA1105R/S 41544531076SVladimir Oltean===== ============== ============== ============== 41644531076SVladimir Oltean0 xMII xMII xMII 41744531076SVladimir Oltean1 xMII xMII xMII 41844531076SVladimir Oltean2 xMII xMII xMII 41944531076SVladimir Oltean3 xMII xMII xMII 42044531076SVladimir Oltean4 xMII xMII SGMII 42144531076SVladimir Oltean===== ============== ============== ============== 42244531076SVladimir Oltean 42344531076SVladimir Oltean 42444531076SVladimir OlteanThe SJA1110 port compatibility matrix is: 42544531076SVladimir Oltean 42644531076SVladimir Oltean===== ============== ============== ============== ============== 42744531076SVladimir OlteanPort SJA1110A SJA1110B SJA1110C SJA1110D 42844531076SVladimir Oltean===== ============== ============== ============== ============== 42944531076SVladimir Oltean0 RevMII (uC) RevMII (uC) RevMII (uC) RevMII (uC) 43044531076SVladimir Oltean1 100base-TX 100base-TX 100base-TX 43144531076SVladimir Oltean or SGMII SGMII 43244531076SVladimir Oltean2 xMII xMII xMII xMII 43344531076SVladimir Oltean or SGMII or SGMII 43444531076SVladimir Oltean3 xMII xMII xMII 43544531076SVladimir Oltean or SGMII or SGMII SGMII 43644531076SVladimir Oltean or 2500base-X or 2500base-X or 2500base-X 43744531076SVladimir Oltean4 SGMII SGMII SGMII SGMII 43844531076SVladimir Oltean or 2500base-X or 2500base-X or 2500base-X or 2500base-X 43944531076SVladimir Oltean5 100base-T1 100base-T1 100base-T1 100base-T1 44044531076SVladimir Oltean6 100base-T1 100base-T1 100base-T1 100base-T1 44144531076SVladimir Oltean7 100base-T1 100base-T1 100base-T1 100base-T1 44244531076SVladimir Oltean8 100base-T1 100base-T1 n/a n/a 44344531076SVladimir Oltean9 100base-T1 100base-T1 n/a n/a 44444531076SVladimir Oltean10 100base-T1 n/a n/a n/a 44544531076SVladimir Oltean===== ============== ============== ============== ============== 446