Lines Matching +full:clock +full:- +full:generation
1 * Synopsys HSDK clock generation unit
3 The Synopsys HSDK clock controller generates and supplies clock to various
8 - compatible: should be "snps,hsdk-cgu-clock"
9 - reg: the pair of physical base address and length of clock generation unit
11 - #clock-cells: should be 1.
13 Each clock is assigned an identifier and client nodes can use this identifier
14 to specify the clock which they consume. All available clocks are defined as
15 preprocessor macros in the dt-bindings/clock/snps,hsdk-cgu.h headers and can be
18 Example: Clock controller node:
20 cgu_clk: cgu-clk@f0000000 {
21 compatible = "snps,hsdk-cgu-clock";
23 #clock-cells = <1>;
26 Example: UART controller node that consumes the clock generated by the clock
30 compatible = "snps,dw-apb-uart";
32 reg-shift = <2>;
33 reg-io-width = <4>;