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/openbmc/linux/Documentation/devicetree/bindings/clock/st/
H A Dst,clkgen-pll.txt7 [2] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
12 "st,clkgen-pll0"
13 "st,clkgen-pll0-a0"
14 "st,clkgen-pll0-c0"
15 "st,clkgen-pll1"
16 "st,clkgen-pll1-c0"
17 "st,stih407-clkgen-plla9"
18 "st,stih418-clkgen-plla9"
29 compatible = "st,clkgen-c32";
34 compatible = "st,stih407-clkgen-plla9";
H A Dst,clkgen.txt34 [3] Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
35 [4] Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
46 compatible = "st,clkgen-c32";
51 compatible = "st,clkgen-pll0";
H A Dst,clkgen-mux.txt13 "st,stih407-clkgen-a9-mux"
25 compatible = "st,stih407-clkgen-a9-mux";
/openbmc/linux/arch/riscv/boot/dts/starfive/
H A Djh7100.dtsi161 clkgen: clock-controller@11800000 { label
162 compatible = "starfive,jh7100-clkgen";
178 clocks = <&clkgen JH7100_CLK_I2C0_CORE>,
179 <&clkgen JH7100_CLK_I2C0_APB>;
191 clocks = <&clkgen JH7100_CLK_I2C1_CORE>,
192 <&clkgen JH7100_CLK_I2C1_APB>;
206 clocks = <&clkgen JH7100_CLK_GPIO_APB>;
218 clocks = <&clkgen JH7100_CLK_UART2_CORE>,
219 <&clkgen JH7100_CLK_UART2_APB>;
231 clocks = <&clkgen JH7100_CLK_UART3_CORE>,
[all …]
/openbmc/linux/arch/arm/boot/dts/st/
H A Dstih418-clock.dtsi34 compatible = "st,clkgen-c32";
39 compatible = "st,stih418-clkgen-plla9";
49 compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
70 compatible = "st,clkgen-c32";
75 compatible = "st,clkgen-pll0-a0";
91 compatible = "st,clkgen-c32";
96 compatible = "st,clkgen-pll0-c0";
103 compatible = "st,clkgen-pll1-c0";
145 compatible = "st,clkgen-c32";
168 compatible = "st,clkgen-c32";
[all …]
H A Dstih410-clock.dtsi34 compatible = "st,clkgen-c32";
39 compatible = "st,stih407-clkgen-plla9";
49 compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
70 compatible = "st,clkgen-c32";
75 compatible = "st,clkgen-pll0-a0";
91 compatible = "st,clkgen-c32";
96 compatible = "st,clkgen-pll0-c0";
103 compatible = "st,clkgen-pll1-c0";
145 compatible = "st,clkgen-c32";
168 compatible = "st,clkgen-c32";
[all …]
H A Dstih407-clock.dtsi31 compatible = "st,clkgen-c32";
36 compatible = "st,stih407-clkgen-plla9";
43 compatible = "st,stih407-clkgen-a9-mux";
65 compatible = "st,clkgen-c32";
70 compatible = "st,clkgen-pll0-a0";
86 compatible = "st,clkgen-c32";
91 compatible = "st,clkgen-pll0-c0";
98 compatible = "st,clkgen-pll1-c0";
140 compatible = "st,clkgen-c32";
163 compatible = "st,clkgen-c32";
[all …]
H A Dstih418-b2199.dts103 st,tx-retime-src = "clkgen";
H A Dstih418-b2264.dts109 st,tx-retime-src = "clkgen";
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dadi,axi-clkgen.yaml4 $id: http://devicetree.org/schemas/clock/adi,axi-clkgen.yaml#
7 title: Analog Devices AXI clkgen pcore clock generator
22 - adi,axi-clkgen-2.00.a
23 - adi,zynqmp-axi-clkgen-2.00.a
63 compatible = "adi,axi-clkgen-2.00.a";
H A Dnvidia,tegra20-car.yaml15 Tegra's clocks, and setting their rates. It comprises CLKGEN and RSTGEN units.
17 CLKGEN provides the registers to program the PLLs. It controls most of
20 CLKGEN input signals include the external clock for the reference frequency
23 Outputs from CLKGEN are inputs clock of the h/w blocks in the Tegra system.
H A Dnvidia,tegra124-car.yaml15 Tegra's clocks, and setting their rates. It comprises CLKGEN and RSTGEN units.
17 CLKGEN provides the registers to program the PLLs. It controls most of
20 CLKGEN input signals include the external clock for the reference frequency
23 Outputs from CLKGEN are inputs clock of the h/w blocks in the Tegra system.
H A Dstarfive,jh7100-audclk.yaml52 clocks = <&clkgen JH7100_CLK_AUDIO_SRC>,
53 <&clkgen JH7100_CLK_AUDIO_12288>,
54 <&clkgen JH7100_CLK_DOM7AHB_BUS>;
H A Dstarfive,jh7100-clkgen.yaml4 $id: http://devicetree.org/schemas/clock/starfive,jh7100-clkgen.yaml#
15 const: starfive,jh7100-clkgen
51 compatible = "starfive,jh7100-clkgen";
/openbmc/u-boot/arch/arm/dts/
H A Dstih407-clock.dtsi40 compatible = "st,clkgen-c32";
45 compatible = "st,stih407-clkgen-plla9";
58 compatible = "st,stih407-clkgen-a9-mux";
94 compatible = "st,clkgen-c32";
99 compatible = "st,clkgen-pll0";
132 compatible = "st,clkgen-c32";
137 compatible = "st,clkgen-pll0";
146 compatible = "st,clkgen-pll1";
214 compatible = "st,clkgen-c32";
254 compatible = "st,clkgen-c32";
[all …]
H A Dstih410-clock.dtsi42 compatible = "st,clkgen-c32";
47 compatible = "st,stih407-clkgen-plla9";
60 compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
96 compatible = "st,clkgen-c32";
101 compatible = "st,clkgen-pll0";
138 compatible = "st,clkgen-c32";
143 compatible = "st,clkgen-pll0";
153 compatible = "st,clkgen-pll1";
233 compatible = "st,clkgen-c32";
275 compatible = "st,clkgen-c32";
[all …]
/openbmc/linux/drivers/clk/st/
H A DMakefile2 obj-y += clkgen-mux.o clkgen-pll.o clkgen-fsyn.o clk-flexgen.o
H A Dclkgen-mux.c3 * clkgen-mux.c: ST GEN-MUX Clock driver
16 #include "clkgen.h"
110 CLK_OF_DECLARE(clkgen_a9mux, "st,stih407-clkgen-a9-mux",
H A Dclkgen-pll.c18 #include "clkgen.h"
830 CLK_OF_DECLARE(c32_pll0, "st,clkgen-pll0", clkgen_c32_pll0_setup);
837 CLK_OF_DECLARE(c32_pll0_a0, "st,clkgen-pll0-a0", clkgen_c32_pll0_a0_setup);
844 CLK_OF_DECLARE(c32_pll0_c0, "st,clkgen-pll0-c0", clkgen_c32_pll0_c0_setup);
851 CLK_OF_DECLARE(c32_pll1, "st,clkgen-pll1", clkgen_c32_pll1_setup);
858 CLK_OF_DECLARE(c32_pll1_c0, "st,clkgen-pll1-c0", clkgen_c32_pll1_c0_setup);
865 CLK_OF_DECLARE(c32_plla9, "st,stih407-clkgen-plla9", clkgen_c32_plla9_setup);
872 CLK_OF_DECLARE(c28_plla9, "st,stih418-clkgen-plla9", clkgen_c28_plla9_setup);
/openbmc/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-sti.c51 *| | clk-125/txclk | clkgen |
52 *| | clkgen | |
55 *| | |clkgen/phyclk-in |
68 * clkgen| 1 | 1 | n/a |
155 /* On GiGa clk source can be either ext or from clkgen */ in stih4xx_fix_retime_src()
159 /* Switch to clkgen for these speeds */ in stih4xx_fix_retime_src()
/openbmc/linux/Documentation/devicetree/bindings/hwmon/
H A Dstarfive,jh71x0-temp.yaml63 clocks = <&clkgen JH7100_CLK_TEMP_SENSE>,
64 <&clkgen JH7100_CLK_TEMP_APB>;
/openbmc/linux/drivers/clk/
H A Dclk-axi-clkgen.c3 * AXI clkgen driver
582 .compatible = "adi,zynqmp-axi-clkgen-2.00.a",
586 .compatible = "adi,axi-clkgen-2.00.a",
595 .name = "adi-axi-clkgen",
604 MODULE_DESCRIPTION("Driver for the Analog Devices' AXI clkgen pcore clock generator");
H A DKconfig289 tristate "AXI clkgen driver"
293 Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dsti-dwmac.txt24 possible values from "txclk", "clk_125" or "clkgen".
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dstarfive,jh7100-pinctrl.yaml179 clocks = <&clkgen JH7100_CLK_GPIO_APB>;
180 resets = <&clkgen JH7100_RSTN_GPIO_APB>;

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