Lines Matching full:clkgen
161 clkgen: clock-controller@11800000 { label
162 compatible = "starfive,jh7100-clkgen";
178 clocks = <&clkgen JH7100_CLK_I2C0_CORE>,
179 <&clkgen JH7100_CLK_I2C0_APB>;
191 clocks = <&clkgen JH7100_CLK_I2C1_CORE>,
192 <&clkgen JH7100_CLK_I2C1_APB>;
206 clocks = <&clkgen JH7100_CLK_GPIO_APB>;
218 clocks = <&clkgen JH7100_CLK_UART2_CORE>,
219 <&clkgen JH7100_CLK_UART2_APB>;
231 clocks = <&clkgen JH7100_CLK_UART3_CORE>,
232 <&clkgen JH7100_CLK_UART3_APB>;
244 clocks = <&clkgen JH7100_CLK_I2C2_CORE>,
245 <&clkgen JH7100_CLK_I2C2_APB>;
257 clocks = <&clkgen JH7100_CLK_I2C3_CORE>,
258 <&clkgen JH7100_CLK_I2C3_APB>;
270 clocks = <&clkgen JH7100_CLK_WDTIMER_APB>,
271 <&clkgen JH7100_CLK_WDT_CORE>;
280 clocks = <&clkgen JH7100_CLK_TEMP_SENSE>,
281 <&clkgen JH7100_CLK_TEMP_APB>;