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/openbmc/linux/drivers/scsi/qla2xxx/
H A Dqla_devtbl.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 static char *qla2x00_model_name[QLA_MODEL_NAMES*2] = {
8 "QLA2340", "133MHz PCI-X to 2Gb FC, Single Channel", /* 0x100 */
9 "QLA2342", "133MHz PCI-X to 2Gb FC, Dual Channel", /* 0x101 */
10 "QLA2344", "133MHz PCI-X to 2Gb FC, Quad Channel", /* 0x102 */
11 "QCP2342", "cPCI to 2Gb FC, Dual Channel", /* 0x103 */
12 "QSB2340", "SBUS to 2Gb FC, Single Channel", /* 0x104 */
13 "QSB2342", "SBUS to 2Gb FC, Dual Channel", /* 0x105 */
14 "QLA2310", "Sun 66MHz PCI-X to 2Gb FC, Single Channel", /* 0x106 */
15 "QLA2332", "Sun 66MHz PCI-X to 2Gb FC, Single Channel", /* 0x107 */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/powerpc/fsl/
H A Ddma.txt4 This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx
9 - compatible : must include "fsl,elo-dma"
10 - reg : DMA General Status Register, i.e. DGSR which contains
12 - ranges : describes the mapping between the address space of the
14 - cell-index : controller index. 0 for controller @ 0x8100
15 - interrupts : interrupt specifier for DMA IRQ
17 - DMA channel nodes:
18 - compatible : must include "fsl,elo-dma-channel"
20 - reg : DMA channel specific registers
21 - cell-index : DMA channel index starts at 0.
[all …]
/openbmc/openbmc/meta-openembedded/meta-multimedia/recipes-multimedia/dvb-apps/files/dvb-scan-table/dvb-t/
H A Dnl-All2 # Created from http://radio-tv-nederland.nl/TV 1.251978e-312nderlijst%20Nederland.xls
3 # and http://radio-tv-nederland.nl/dvbt/dvbt-lokaal.html
4 [CHANNEL]
8 CODE_RATE_HP = 1/2
16 [CHANNEL]
20 CODE_RATE_HP = 2/3
28 [CHANNEL]
32 CODE_RATE_HP = 1/2
40 [CHANNEL]
44 CODE_RATE_HP = 2/3
[all …]
H A Dcz-All2 # Created from http://www.ctu.cz/cs/download/plan-vyuziti-radioveho-spektra/rok_2012/pv-p_10-08_201…
4 [CHANNEL]
8 CODE_RATE_HP = 2/3
16 [CHANNEL]
20 CODE_RATE_HP = 2/3
28 [CHANNEL]
32 CODE_RATE_HP = 2/3
40 [CHANNEL]
44 CODE_RATE_HP = 2/3
52 [CHANNEL]
[all …]
H A Dit-All1 # This file lists all frequencies used in Western Europe for DVB-T.
16 ### VHF - Band III ###
18 [CHANNEL]
22 CODE_RATE_HP = 2/3
31 [CHANNEL]
35 CODE_RATE_HP = 2/3
44 [CHANNEL]
48 CODE_RATE_HP = 2/3
57 [CHANNEL]
61 CODE_RATE_HP = 2/3
[all …]
H A Dee-All3 # and http://wiki.wifi.ee/index.php/DVB-T#Tehniline_teave
5 [CHANNEL]
9 CODE_RATE_HP = 2/3
17 [CHANNEL]
21 CODE_RATE_HP = 2/3
29 [CHANNEL]
33 CODE_RATE_HP = 2/3
41 [CHANNEL]
45 CODE_RATE_HP = 2/3
53 [CHANNEL]
[all …]
H A Ddk-All2 # Created from http://www.digi-tv.dk/Indhold_og_tilbud/frekvenser.asp
3 # and http://www.digi-tv.dk/Sendenettets_opbygning/
4 [CHANNEL]
8 CODE_RATE_HP = 2/3
16 [CHANNEL]
20 CODE_RATE_HP = 2/3
28 [CHANNEL]
32 CODE_RATE_HP = 2/3
40 [CHANNEL]
44 CODE_RATE_HP = 2/3
[all …]
/openbmc/openbmc/meta-openembedded/meta-multimedia/recipes-multimedia/dvb-apps/files/dvb-scan-table/dvb-s/
H A DAnik-F3-119W2 #Just DVBS-USB Genpix Sky Walker 1 or 2 works with PSK/8turbo
4 [CHANNEL]
9 INNER_FEC = 2/3
13 [CHANNEL]
18 INNER_FEC = 2/3
22 [CHANNEL]
27 INNER_FEC = 2/3
31 [CHANNEL]
36 INNER_FEC = 2/3
40 [CHANNEL]
[all …]
H A DEchostar-10+11-110W2 #Just DVBS-USB Genpix Sky Walker 1 or 2 works with PSK/8turbo
4 [CHANNEL]
9 INNER_FEC = 2/3
13 [CHANNEL]
18 INNER_FEC = 2/3
22 [CHANNEL]
27 INNER_FEC = 2/3
31 [CHANNEL]
40 [CHANNEL]
45 INNER_FEC = 2/3
[all …]
H A DThaicom5_C-78.5E1 # Thaicom 5 @ 78.5E C-BAND
5 # MPEG-2 & MPEG-4 QPSK (DVBS/S2)
9 [CHANNEL]
19 [CHANNEL]
29 [CHANNEL]
39 [CHANNEL]
48 # RRSat Global Network (MPEG-4 S/2)
49 [CHANNEL]
59 [CHANNEL]
68 # PSI Channel
[all …]
H A DTelstar10_C-76.5E1 # Telstar 10 @ 76.5E C-BAND
5 # MPEG-2 & MPEG-4 QPSK (DVBS/S2)
9 [CHANNEL]
18 # Image Channel
19 [CHANNEL]
29 [CHANNEL]
39 [CHANNEL]
44 INNER_FEC = 2/3
49 [CHANNEL]
54 INNER_FEC = 2/3
[all …]
H A DAsiaSat2_C-100.5E1 # AsiaSat 2 100.5E C-BAND
5 # MPEG-2 & MPEG-4 QPSK (DVBS/S2)
9 [CHANNEL]
19 [CHANNEL]
28 # APTN Global Video Wire (MPEG-4 S/2)
29 [CHANNEL]
34 INNER_FEC = 2/3
39 [CHANNEL]
44 INNER_FEC = 1/2
49 [CHANNEL]
[all …]
/openbmc/linux/sound/soc/codecs/
H A Dtas5086.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * - implement DAPM and input muxing
9 * - implement modulation limit
10 * - implement non-default PWM start
13 * because the registers are of unequal size, and multi-byte registers
18 * it doesn't matter because the entire map can be accessed as 8-bit
21 * routines have to be open-coded.
56 #define TAS5086_CLOCK_RATIO(val) (val << 2)
57 #define TAS5086_CLOCK_RATIO_MASK (0x7 << 2)
68 #define TAS5086_SYS_CONTROL_2 0x05 /* System control register 2 */
[all …]
/openbmc/linux/drivers/hsi/controllers/
H A Domap_ssi_regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
31 #define SSI_MPU_STATUS_REG(port, irq) (0x808 + ((port) * 0x10) + ((irq) * 2))
33 # define SSI_DATAACCEPT(channel) (1 << (channel)) argument
34 # define SSI_DATAAVAILABLE(channel) (1 << ((channel) + 8)) argument
35 # define SSI_DATAOVERRUN(channel) (1 << ((channel) + 16)) argument
40 # define SSI_GDD_LCH(channel) (1 << (channel)) argument
44 # define SSI_WAKE(channel) (1 << (channel)) argument
55 # define SSI_MODE_FRAME 2
62 # define SSI_FULL(channel) (1 << (channel)) argument
71 #define SSI_SST_BUFFER_CH_REG(channel) (0x80 + ((channel) * 4)) argument
[all …]
/openbmc/u-boot/include/
H A Dw83c553f.h1 /* SPDX-License-Identifier: GPL-2.0+ */
9 /* from the winbond data sheet -
10 The W83C553F SIO controller with PCI arbiter is a multi-function PCI device.
81 #define W83C553F_DMA1 CONFIG_SYS_ISA_IO + 0x000 /* channel 0 - 3 */
82 #define W83C553F_DMA2 CONFIG_SYS_ISA_IO + 0x0C0 /* channel 4 - 7 */
89 #define W83C553F_CS_COM_CGE (1<<2) /* channel group enable */
91 #define W83C553F_CS_STAT_CH0REQ (1<<4) /* channel 0 (4) DREQ status */
92 #define W83C553F_CS_STAT_CH1REQ (1<<5) /* channel 1 (5) DREQ status */
93 #define W83C553F_CS_STAT_CH2REQ (1<<6) /* channel 2 (6) DREQ status */
94 #define W83C553F_CS_STAT_CH3REQ (1<<7) /* channel 3 (7) DREQ status */
[all …]
/openbmc/qemu/hw/dma/
H A Dxlnx_dpdma.c12 * the Free Software Foundation, either version 2 of the License, or
47 #define DPDMA_ISR (0x0004 >> 2)
48 #define DPDMA_IMR (0x0008 >> 2)
49 #define DPDMA_IEN (0x000C >> 2)
50 #define DPDMA_IDS (0x0010 >> 2)
51 #define DPDMA_EISR (0x0014 >> 2)
52 #define DPDMA_EIMR (0x0018 >> 2)
53 #define DPDMA_EIEN (0x001C >> 2)
54 #define DPDMA_EIDS (0x0020 >> 2)
55 #define DPDMA_CNTL (0x0100 >> 2)
[all …]
/openbmc/linux/Documentation/devicetree/bindings/input/
H A Diqs626a.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jeff LaBundy <jeff@labundy.com>
13 The Azoteq IQS626A is a 14-channel capacitive touch controller that features
14 additional Hall-effect and inductive sensing capabilities.
19 - $ref: touchscreen/touchscreen.yaml#
31 "#address-cells":
34 "#size-cells":
37 azoteq,suspend-mode:
[all …]
H A Diqs269a.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jeff LaBundy <jeff@labundy.com>
13 The Azoteq IQS269A is an 8-channel capacitive touch controller that features
14 additional Hall-effect and inductive sensing capabilities.
28 "#address-cells":
31 "#size-cells":
34 azoteq,hall-enable:
37 Enables Hall-effect sensing on channels 6 and 7. In this case, keycodes
[all …]
/openbmc/u-boot/board/micronas/vct/
H A Dscc.h1 /* SPDX-License-Identifier: GPL-2.0+ */
17 #define DMA_START 0 /* DMA command - start DMA */
18 #define DMA_STOP 1 /* DMA command - stop DMA */
19 #define DMA_START_FH_RESET 2 /* DMA command - start DMA reset FH */
20 #define DMA_TAKEOVER 15 /* DMA command - commit the DMA conf */
32 #define TO_DMA_CFG 2 /* takeover command for the DMA config*/
36 #define DMA_CMD_START 2
41 #define DMA_STATE_START 2
46 #define STRM_P 2
51 #define RESET_TIME 2 /* cycle calc see in SCC_Reset */
[all …]
/openbmc/linux/sound/pci/emu10k1/
H A Dp16v.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (c) by James Courtier-Dutton <James@superbug.demon.co.uk>
11 /* Audigy2 P16V pointer-offset register set, accessed through the PTR2 and DATA2 registers …
25 #define PLAYBACK_LIST_SIZE 0x01 /* Size of list in bytes << 16. E.g. 8 periods -> 0x00380000 */
41 /* [0:1] Capture input 0 channel select. 0 = Capture output 0.
43 * 2 = Capture output 2.
45 * [3:2] Capture input 1 channel select. 0 = Capture output 0.
47 * 2 = Capture output 2.
49 * [5:4] Capture input 2 channel select. 0 = Capture output 0.
51 * 2 = Capture output 2.
[all …]
/openbmc/linux/drivers/tty/serial/
H A Dip22zilog.c1 // SPDX-License-Identifier: GPL-2.0
6 * This is based on the drivers/serial/sunzilog.c code as of 2.6.0-test7 and the
13 * Copyright (C) 2002 Ralf Baechle (ralf@linux-mips.org)
51 #define ZS_WSYNC(channel) do { } while (0) argument
54 #define NUM_CHANNELS (NUM_IP22ZILOG * 2)
87 #define ZILOG_CHANNEL_FROM_PORT(PORT) ((struct zilog_channel *)((PORT)->membase))
90 (UART_ZILOG(PORT)->curregs[REGNUM])
92 ((UART_ZILOG(PORT)->curregs[REGNUM]) = (REGVAL))
93 #define ZS_IS_CONS(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_CONS)
94 #define ZS_IS_KGDB(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_KGDB)
[all …]
/openbmc/ipmitool/lib/
H A Dipmi_channel.c1 /* -*-mode: C; indent-tabs-mode: t; -*-
22 * PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED.
60 /* _ipmi_get_channel_access - Get Channel Access for given channel. Results are
63 * @intf - IPMI interface
64 * @channel_access - ptr to channel_access_t with Channel set.
65 * @get_volatile_settings - get volatile if != 0, else non-volatile settings.
67 * returns - negative number means error, positive is a ccode.
76 uint8_t data[2]; in _ipmi_get_channel_access()
79 return (-3); in _ipmi_get_channel_access()
81 data[0] = channel_access->channel & 0x0F; in _ipmi_get_channel_access()
[all …]
/openbmc/linux/sound/pci/ca0106/
H A Dca0106.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (c) 2004 James Courtier-Dutton <James@superbug.demon.co.uk>
12 * Removed noise from Center/LFE channel when in Analog mode.
34 * playback periods_min=2, periods_max=8
50 * Implement support for Line-in capture on SB Live 24bit.
73 #define IPR_MIDI_RX_B 0x00020000 /* MIDI UART-B Receive buffer non-empty */
74 #define IPR_MIDI_TX_B 0x00010000 /* MIDI UART-B Transmit buffer empty */
87 #define IPR_MIDI_RX_A 0x00000004 /* MIDI UART-A Receive buffer non-empty */
88 #define IPR_MIDI_TX_A 0x00000002 /* MIDI UART-A Transmit buffer empty */
93 #define INTE_MIDI_RX_B 0x00020000 /* MIDI UART-B Receive buffer non-empty */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dtlv320adcx140.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Texas Instruments TLV320ADCX140 Quad Channel Analog-to-Digital Converter
11 - Andrew Davis <afd@ti.com>
14 The TLV320ADCX140 are multichannel (4-ch analog recording or 8-ch digital
15 PDM microphones recording), high-performance audio, analog-to-digital
16 converter (ADC) with analog inputs supporting up to 2V RMS. The TLV320ADCX140
28 - ti,tlv320adc3140
29 - ti,tlv320adc5140
[all …]
/openbmc/linux/sound/core/oss/
H A Drate.c2 * Rate conversion Plug-In
8 * published by the Free Software Foundation; either version 2 of
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
29 #define R_MASK (BITS-1)
55 unsigned int channel; in rate_init() local
56 struct rate_priv *data = (struct rate_priv *)plugin->extra_data; in rate_init()
57 data->pos = 0; in rate_init()
58 for (channel = 0; channel < plugin->src_format.channels; channel++) { in rate_init()
59 data->channels[channel].last_S1 = 0; in rate_init()
60 data->channels[channel].last_S2 = 0; in rate_init()
[all …]

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